TWI237874B - Method of forming bit-line contact - Google Patents

Abstract

A kind of method for forming bit line contact is provided in the present invention. At first, a semiconductor substrate is provided. On the semiconductor substrate, a transistor is provided, and the transistor has a gate and a source/drain region. Then, a dielectric layer, which has a contact-window exposing the surface of the source/drain region, is formed on the semiconductor substrate. A conductive plug is formed on the contact window, and then a metal layer is formed on the conductive plug surface. After that, an annealing process is conducted onto the metal layer to have reaction between the surfaces of the first metal layer and the conductive layer contact, so as to form a reaction layer. The first metal layer, which is not reacted, is removed; and a bit line is formed on the conductive plug that has reaction layer on its surface.

Description

1237874 V. Description of the Invention (l) Field of the Invention The present invention relates to a method for forming a contact window, and more particularly to a method for forming a bit line contact. Prior art In recent years, in the design of semiconductor circuits, the status of capacitors has become increasingly important and has become an irreplaceable circuit element. For example, dynamic random access memory (DRAM: dynamic random access memory), oscillator (〇3 (^ 11 & 1: 〇1〇), time delay circuitry, analog / digital or Digital / analog converters (AD / DA converters) and many other application circuits. Therefore, stacked S-type capacitor valleys (STC) or trenched capacitor cells have been developed in compact memory devices. Out, it uses the space above the access device in the silicon wafer or the substrate to form the capacitor electrode plate. This structure has the advantage of having a low soft error rate (SER: soft error rate) and can be combined with a high dielectric An insulating layer with a high dielectric constant; at the same time, the memory cell and the bit line need to be connected by a contact window. Please refer to FIG. 1a. First, a semiconductor substrate 101 is provided, and the semiconductor substrate 101 has a peripheral circuit. Layer 102. A gate dielectric layer 103, a conductive layer 104, a hard mask layer 105, and a patterned photoresist layer 106 are sequentially formed on the semiconductor substrate 100m. Huaguang The position of the layer 丨 〇6 is the position where the gate is subsequently formed. The semiconductor substrate 101 is, for example, a silicon substrate; the peripheral circuit layer 102 is, for example, an ion-doped region; and the gate dielectric layer is, for example, 11 1

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II 0548-9072TWF (N1); 91145; Claire.ptd Page 5 1237874 V. Description of the invention (2) Gate oxide layer; conductive layer 104 is, for example, doped polycrystalline silicon layer or doped stone layer; hard mask The layer 105 is, for example, a nitride nitride layer, which is used to protect the conductive hafnium from being destroyed in subsequent processes. Figure 1b of the θ Mingtu test "continue" using the patterned photoresist layer i 〇6 as the narrative sequence to sequentially etch the hard mask layer 105, the conductive layer 104 and the gate dielectric layer 103, To form a gate dielectric layer on the semiconductor substrate 101: a layer 104a and a hard mask layer 05a, a conductive layer 104a and a hard mask layer 105, that is, to serve as a gate; and To remove the patterned photoresist layer. Among them, the method of anisotropic etching is reactive ion etching (Reactiv ^

Ion Etching (RIE) or electro-polymer etching (plasma to pyrene). Please refer to Figure B 'for conformal formation of the semiconductor substrate 101 and the surface of the above-mentioned components-an insulating layer (not shown), and perform an insulating layer An isotropic etching is performed to form a gap wall 107 on the side wall of the gate. In the middle, the gap 3 107 is, for example, a nitrogen-cut layer; the method of anisotropic chirping is, for example, reactive ion etching (Reactive Ion Etchlng). (RIE) or plasma etching ~ (Please refer to the Id diagram, in order to form a dielectric layer 10δ and a picture of the above-mentioned element 101 in order to form a dielectric layer) Resistive layer 109, the resist layer 109 has -open nl1G, a part of the interface is exposed, and the position of the opening U0 is the subsequent formation of the bit surface. Among them, the dielectric layer 108 is, for example, oxidized sound, and The solid oxide layer is solidified. Please refer to Fig. 1 ^, especially tetroxidonic acid, and use the patterned photoresist layer 109 as the mask to etch the dielectric layer 2 0. Etching to form an opening 丨 1 ^, opening m

〇548-9072T1VF (N1)-91145; Claire.ptd Page 6 1237874 V. Description of the invention (3) This is the removal of the bit line that will be formed later. The towel is anisotropic. Second, the patterning photoresist layer u τ r is etched, for example, reactive ion etching (Reactive Ion Etchir ^, etching). g R 1 E) or plasma money engraving (P 1 asma, please refer to Figure 1 f, forming an electrical layer on the right-conductive layer (not shown) and the conductive layer 108 of the dielectric layer 108).露 ;; 4:;: 口 111. Then, the distance to the guide lilt. A predetermined distance; among them, the conductive # 112, and the sound of about 300 to 400 〇A. The use of multi-m ΐ ΐ is a polycrystalline layer or worm crystal Shi Xi ^ ⑴Using the sun and silicon layer or epitaxial stone Xi ® made 丄, the quality is more stable, and there is no leakage ^ ,, and the contact line of the wood wire contact window has a slower. Θ ¥ 电 电 板Generated, but the transmission rate will be higher than that in the figure of §1. On the surface of the dielectric layer 108 = layer 113, the patterned photoresist layer 113 has-opening ⑴ = the position of the dielectric layer 对应 corresponding to the dielectric layer 1G2 of the peripheral circuit layer. On the surface, a contact window is formed as a peripheral metal wire in a subsequent step. Fig. 1 h of the image of ιυζ, using the patterned photoresist layer 1 1 3 as an etching mask to perform anisotropic dielectric layer 1 08 Etch to form a hole 11 5 that exposes the peripheral circuit layer 102; then, remove the patterned photoresist layer 丨 丨 3. Please refer to FIG. A patterned photoresist layer 116 is formed on the layer 108. The patterned photoresist layer 丨 6 covers the surface of the dielectric layer 108 corresponding to the peripheral circuit area, and exposes the memory cells corresponding to the elements including the gate electrode. Surface of the dielectric layer 108 of the region.

〇548-9072TWF (Nl); 91145; Claire.ptd

Figure 1j of the monthly test “Next” with the patterned photoresist layer 1 1 6 as the worm mask ”on the exposed surface corresponding to the memory package area containing the gate and other components V. Description of the invention (4 ) Electrically anisotropically etched at $ 108 to form a groove having a predetermined degree of 100 to 400 A; wherein a groove having a predetermined depth is a position for subsequent formation of a quaternary line. Then, a chemical vapor deposition method (chemica 1 vapor dep0Sitl0n, CVD) is used to conform to the surface of the semiconductor substrate 10i and the hole 115 to form a relatively thin barrier layer 1 1 7, and the barrier layer 1 1 7 Perform the tempering procedure. The barrier layer 17 is, for example, a titanium nitride (τ 丨 n) layer. Please refer to the lk chart of the tea. A tungsten metal layer (not ^ not) is formed on the surface of the dielectric layer 108. The tungsten (W) metal layer will fill the grooves and holes 1 1 5; The layer is subjected to an etch-back step until the surface of the dielectric layer 丨 〇8 is 111 = this ^, and only the tungsten metal layer 11 8a in the grooves and holes 115 is the bit Ϊ and a barrier layer 117a is formed; The contact line of the tungsten metal layer 118a in the groove and the tungsten metal 8b wire in the hole 115 west. The gate n & m records that the resistance value of the tungsten metal layer is low, so the long-term transmission rate is required to use the tungsten metal layer as a guide, which is in line with the peripheral circuit that requires a faster transmission rate. Above 108 ', therefore, at the formation of @ 夕 & I, there will be fluorine ions entering the polycrystalline silicon layer and the pores of the structure of the silicon layer will have pores 119, as shown in Figure 1). To make

0548-9072TWF (Nl); 91145; Claire.ptd Page 8 1237874 V. Description of the invention (5) There is a turtle here. The method of the present invention is mainly by using polycrystalline silicon to provide a bit of fun The combined bit line is connected to the titanium metal layer and the titanium metal and maintains stable quality.妾 Touch® 化 Transfer rate of memory plus memory cell area According to the above purpose, this method includes the following steps: mention; 1 = ”the bit line is in contact with a transistor, the transistor is right, the soil is half a ^ A -dielectric layer is formed on the substrate on the body substrate; =-:: and the polar region, the semiconductor metal layer is in contact with the conductive layer f to the metal layer, and then a tempering step is performed to remove the first metal layer of the first gold ^ Plane reaction to form a reaction layer, and will not react into a bit line. Forming a conductive plug with a reaction layer on the surface According to the above method, including the following steps, this month and then provide a kind of bit line There is a peripheral circuit layer in contact with the semiconductor substrate. The semiconductor substrate has a gate and a bulk body. A transistor, a transistor layer, and a dielectric layer have a drain region. The semiconductor substrate is formed on the semiconductor substrate. On the formation-the dielectric surface, and the first opening is: the opening, the first opening exposing the surface of the source electrode region is formed in sequence-more said: the bit line contact window formed after the performance; -Tempering step with ff-first metal layer; shape the first-metal layer A petrified metal; I. f I is a layer formed on the contact surface of the polycrystalline polycrystalline layer-the second opening ^ except for the unreacted first-the metal layer; touch the window on the dielectric layer; on the dielectric layer # 丄And the surrounding circuit layers are connected to each other-patterned photoresist layer, patterned photoresist layer

0548-9072TWF (Nl); 91145; Claire.ptd

B Page 9 12378874 V. Description of the invention (6) Covering the contact windows of the peripheral circuit layer; using the patterned photoresist layer as an etching mask, etching the dielectric layer to a predetermined depth, and removing the patterned photoresist layer; A barrier layer is conformably formed on the surface of the substrate, the silicided metal layer, and the surrounding metal contact window; a second metal layer is formed on the barrier layer, and the second metal layer fills the surrounding metal contact window and the first opening; and The second metal layer is planarized until the surface of the dielectric layer is exposed. According to the above object, the present invention further provides a method for forming a bit line contact, including the following steps: providing a semiconductor substrate, the semiconductor substrate having a peripheral circuit layer, and a transistor formed on the semiconductor substrate, the transistor having a gate and A source drain region; a dielectric layer and a first patterned photoresist layer are sequentially formed on a semiconductor substrate, the first patterned photoresist layer has a first opening, and a position of the first opening is a subsequent formation bit The position of the line contact window; using the first patterned photoresist layer as an etching mask, performing an anisotropic etching step on the dielectric layer to form a second opening, the second opening exposing the surface of the source drain region, and the first The two openings are subsequent bit line contact windows; the first patterned photoresist layer is removed; a polycrystalline silicon layer is formed on the semiconductor substrate, and the polycrystalline silicon layer fills the second opening; the polycrystalline silicon layer is etched back to the exposed substrate The surface of the electrical layer, and the polycrystalline silicon layer with the second opening has a first predetermined depth; a titanium metal layer is conformably formed on the surfaces of the dielectric layer and the polycrystalline silicon layer; The layer is subjected to a tempering step to form a titanium silicide layer on the surface where the titanium metal layer is in contact with the polycrystalline silicon layer; the unreacted titanium metal layer is removed, leaving titanium polysilicon on the surface of the polycrystalline silicon layer A metal layer; a second patterned photoresist layer is formed on the dielectric layer, the second patterned photoresist layer has a third opening, and the position of the third opening is the position of the contact window for the subsequent formation of the peripheral circuit layer

0548-9072TWF (N1); 91145; Claire.ptd p.10 The light edge circuit is converted into a first layer to a substrate, and a barrier layer is filled on the periphery to expose the surface. A resistive layer is a engraved layer contact window; Two patterned light touch windows; the second predetermined deep stone titaniumized metal barrier layer; the surface of the electrical barrier layer of the metal contact window is described and other preferred embodiments

Mask, non-removing the second barrier layer, the third patterning degree; removing the layer and the surrounding barrier layer and forming the second stop. And features, and cooperate with 1237874 ------ Five 'invention description (7); use a second layer to form a circle on the dielectric layer to cover the surrounding wire curtain' money engraved dielectric layer; on the semiconductor surface The conformable shape is filled with a metal layer of the crane metal layer until the present invention is easy to understand, the following is explained in detail as follows: isotropic etching dielectric patterned photoresist layer; two patterned photoresist layer photoresist layer is an etching cover The surface of the third patterned photoresistive metal contact window is made of a tungsten metal layer, a mouth; and flattened tungsten, and the advantages can be more clearly shown in the drawings, for detailed implementation: Figure 2a-21 of the element line diagram Schematic diagram of the invention's method of forming a wire contact. ~ Take 1π Please refer to Figure 2a. First, the body substrate m has -peripheral ϋ-+ conductor base ㈣1 'semiconductor sequence formation-gate dielectric layer m,-conductive layer 2Q4,-hard and a patterning The photoresist layer 2 0 6 is shown in FIG. 2 and μ ^ η β & & φ, the T ^ body substrate 2 0 1 is, for example, sisami. If it is an ion-doped region, the gate dielectric layer 2 2 "If the electrical layer 204 is, for example, a doped polycrystalline layer or a doped layer, the hard mask layer 2G5 is, for example, a nitrogen-cut layer to protect the conductive layer—

1237874 V. Description of Invention (8) 'Will not be destroyed in subsequent processes. Please refer to FIG. 2b, and then, using the patterned photoresist layer 2 0 6 as the etching mask, the hard mask 2 5, the conductive layer 204, and the gate dielectric layer 203 are sequentially anisotropically etched. The gate dielectric layer 203a, the conductive layer 204a, and the hard mask layer 205a are formed on the semiconductor substrate 201, and the conductive layer 204a and the hard mask layer 205a are used as gates; Then, the patterned photoresist layer 2 q 6 is removed. Among them, the method of anisotropic rice etching is Reactive Ion EtcMng (RIE) or Plasma etching. Please refer to FIG. 2c, conformally forming an insulating layer (not shown) on the surface of the semiconductor substrate 201 and the above-mentioned components, and anisotropically etch the insulating layer to form a gap 2 on the side wall of the gate 〇7. Among them, the interval 207 is, for example, a silicon nitride layer; the non-isotropic tremor etched soil M.., Lirp +. Τ Jingsi direction 14 is etched, for example, by reactive reactive ions (Reactive Ion Ei ~ phinrr ητ ^ , ,, ,, Mehlng (HE) or plasma etching. Please refer to the figure 2d, and sequentially form a dielectric layer m and a two-layer semiconductor substrate on the opening 彡 # 古 一 〇2. The resist layer 2 0 9 has an opening 2 1 0, opening? That is, 2 0, a smooth surface is patterned, and the position of the opening 210 is the position of the dielectric layer 208 of Deting 2 °. Among them, the dielectric layer 208 is an in-situ oxide layer such as e-Gas Line Contact®.疋 Emulsified layer, especially tetraethyl silicate is the interface 211 of the mask cover. The opening 211 will be a patterned photoresist layer such as reactive ions. Isotropic etching, that is, the subsequent formation of bit line contact with the stomach 209 is removed. Among them, anisotropic etching white (

1237874 V. Description of the invention (9) '-Etchlng (ReacUve Ion Etchlng, RIE) or plasma etching (Piasma Etching) °, Shuangfangkou S 2 f picture' on the dielectric layer 2 with the opening 2 i 丄A conductive layer (not shown) is formed on Q 8 and the conductive layer will fill the opening 2 丨]. Next, the conductive layer is etched back until the surface of the dielectric layer 208 is exposed, and the $ electrical layer 2 1 2 in the opening 2 1 1 is a predetermined distance from the top of the opening 2 i, which is 3 0 0 to 40 0 0 A. Among them, the conductive layer 212, such as a polycrystalline silicon layer or a silicon layer, is a bit line contact window formed by using a polycrystalline silicon layer or an epitaxial silicon layer, which has relatively stable quality, and has no leakage current, but The transfer rate will be slower. Please refer to No. 2 ", on the surface of the dielectric layer 208 and the conductive layer 212, a titanium (T 1) metal layer 2 1 3 is formed concentrically and at a temperature of 500 to 800 ° C, ^ Tempering the titanium metal layer 213 to form a titanium silicide (TiSi) metal layer 213a on the surface of the titanium metal layer 213 that is in contact with the conductor 2 to protect the conduction during the step The layer 2 1 2 is not invaded by the fluorine gas. Then, the unreacted titanium metal layer 2 1 3 when removing & Λ 'is removed, as shown in Fig. 2h. Jie Xueen U. ^,, L ^ Electrical layer 208 and titanium silicide layer 21 3a are formed on one side of a photo-wooden photoresist layer 214, and the patterned photoresist layer 214 has an opening 21 5 and an opening 21 5th place. The scholars are widely used. 'It is located on the surface of the dielectric layer 208 corresponding to the peripheral circuit layer 2 0 2 to be used as a peripheral metal.' The contact window of the peripheral circuit layer 2 0 2 of the wire. Please refer to Figure 2j for details such as Hong Yuyi Lei # IA & Case light layer 214 is used as an etching mask for etching. Peripheral lines Hole 202 of the

0548-9072TWF (Nl); 91145 i Claire.ptd page 13 1237874 V. Description of the invention (10) A " --Γ 2 1 6 Then, the patterned photoresist layer 2 丨 4 is removed. Next, a patterned photoresist layer 217 is formed on the dielectric layer 208. The patterned photoresist layer 217 covers the surface of the dielectric layer 208 corresponding to the peripheral circuit area, and exposes the memory corresponding to the components including the gate electrode and the like. The surface of the dielectric layer 208 of the cladding region. Referring to Figure 2k, 'the next step is to use a patterned photoresist layer 2 1 7 as a engraved mask' to perform an anisotropy on the exposed surface of the dielectric layer 2 0 corresponding to the memory envelope containing the gate and other components. The etching is performed to form a groove having a predetermined depth of 0.001 to 4,000a; wherein a groove having a predetermined depth is a position where a bit line is subsequently formed. Then, a chemical vapor deposition (CVD) method is used to conformally form a relatively thin barrier layer 218 on the surface of the semiconductor substrate 201, the titanium silicide layer 2 1 3a, and the hole 2 1 6, and The barrier layer 218 is subjected to a tempering procedure. The barrier layer 2 1 8 is, for example, a titanium nitride (T i N) layer. Please refer to FIG. 21, a tungsten metal layer (not shown) is formed on the surface of the dielectric layer 208. The tungsten (W) metal layer will fill the grooves and holes 2 1 6; then, the tungsten metal layer is returned. The etching step is until the surface of the dielectric layer 208 is exposed. In this way, only the tungsten metal layers 2 1 9 a and 219 b in the grooves and holes 2 丨 6 are left, and a barrier layer 218 & The tungsten metal layer [lb] of the groove is a bit line, and the tungsten metal layer 219b located in the hole 216 is a contact window of the peripheral wire. w Because the tungsten metal layer has a low resistance value, using the tungsten metal layer as the wire has a better transmission rate, which meets the needs of peripheral circuits for faster transmission speeds. However, because the tungsten metal layers 219a and 219b are mainly made of silicon (WF6) is deposited on the dielectric layer 208 as a reactive gas.

0548-9072TWF (N1); 91145; Claire.ptd page 14 1237874 V. Description of invention (11) ---

In the process of the crane metal layer, fluorine ions often enter the polycrystalline silicon layer and cause the structure of the polycrystalline silicon layer to show pores. The titanium silicide metal layer 2 i 3 a formed between gI according to the present invention can effectively block all tungsten: two bit line contact windows to avoid bits; crystal friction shape = ， ... metal layer 2 harness; = f structure Destruction; the wide / boundary of Tonghe metal layer 219a and guide 12: the usefulness of the inter-resistance value, so that the conductive layer 212, titanium B metal layer = low, and the bit line contact window that can be borrowed at the same time is a blessing. Stable quality combined with fa and tungsten metal layer 21 9a. '^ Rate and retain the bit line contact window Although the present invention p-defines the invention, any familiar ::::::: soil: Ran; not for the purpose of seeing the attached patent; or :; protection of the invention " :

0548-9072TWF (N1); 91145; Claire • Ptd Page 15 1237874 Brief description of the drawings Page 1 a-1 1 1 shows the conventional method of forming the bit line contact. Figures 2a to 21 are schematic views showing the method for forming a bit line contact according to the present invention. Explanation of symbols: 1 0 1, 2 01 ~ semiconductor substrate; 1 0 2, 2 0 2 ~ peripheral circuit layer; 1 0 3, 1 0 3 a, 2 0 3, 2 0 3 a ~ gate dielectric layer; 104 , 104a, 112, 204, 204a, 212 ~ conductive layer; 105, 105a, 2 0 5, 2 5a ~ hard cover curtain layer; 1 06, 1 0 9, 11 3, 1 1 6 ~ patterned photoresist Layers; 1 07, 2 07 ~ spacer wall; 108, 2 08 ~ dielectric layer; 110, 111, 114, 115 ~ opening; 117, 117a, 218, 218a ~ barrier layer; 118a, 118b, 219a, 219b ~ tungsten metal layer; 1 1 9 ~ porosity; 206, 209, 214, 217 ~ patterned photoresist layer; 2 1 0, 2 11, 2 1 5, 2 1 6 ~ openings; 213 ~ titanium metal layer; 2 1 3 a ~ Shi Xihua titanium metal layer.

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Claims (1)

1237874 VI. Application Patent Scope 1. A method for forming a bit line contact, including the following steps: providing a semiconductor substrate having a transistor on the semiconductor substrate, the transistor having a gate and a source / anion region; A dielectric layer is formed on the semiconductor substrate, and the dielectric layer has a contact window, which exposes the surface of the source-drain region; a conductive plug is sequentially formed on the contact window; and a conductive plug is formed on the conductive plug surface. A metal layer; performing a tempering step on the metal layer to form a reaction layer on a surface where the first metal layer is in contact with the conductive layer, and removing the unreacted first metal layer; and having the reaction layer on the surface A bit line is formed on the conductive plug. 2. The method for forming a bit line contact as described in item 1 of the patent application scope, wherein the dielectric layer is an oxide layer. 3. The method for forming a bit line contact as described in item 2 of the patent application scope, wherein the oxide layer is a tetraethyl silicate oxide layer. 4. The method for forming a bit line contact as described in item 1 of the patent application scope, wherein the conductive plug is a polycrystalline silicon layer or an epitaxial silicon layer. 5. The method for forming a bit line contact as described in item 1 of the patent application scope, wherein the metal layer is a titanium metal layer. 6. The method for forming a bit line contact as described in item 1 of the scope of patent application, wherein the reaction layer is a titanium metal layer. 7. The method of forming a bit line contact as described in item 1 of the scope of the patent application, wherein the bit line is a tungsten metal layer. 8. A method of forming bit line contacts, including the following steps: 0548-9072TWF (Nl); 91145; Claire.ptd Page 17 1237874 6. The scope of the patent application provides a semiconductor substrate 'the semiconductor substrate has a peripheral circuit layer, and a transistor is formed on the semiconductor substrate, and the transistor has a A gate and a source drain region; forming a dielectric layer on the semiconductor substrate, the dielectric layer having a first opening, the first opening exposing a surface of the source drain region, and the first opening being The bit line contact window formed subsequently; a polycrystalline silicon layer and a first metal layer are sequentially formed on the first opening; and a tempering step is performed on the first metal layer so that the first metal layer and the polycrystalline silicon A petrified metal layer is formed on the surface in contact with the petrified layer; the unreacted first metal layer is removed; a second opening is formed in the dielectric layer, and the second opening is a contact window of the peripheral circuit layer to be formed subsequently; A patterned photoresist layer is formed on the dielectric layer, and the patterned photoresist layer covers the contact window of the peripheral circuit layer. The patterned photoresist layer is #etched the screen, and #etched the dielectric layer to a Given depth, Removing the patterned photoresist layer; compliantly forming a barrier layer on the surface of the semiconductor substrate, the silicided metal layer and the peripheral metal contact window; forming a second metal layer on the barrier layer, and the first metal layer Two metal layers fill the peripheral metal contact window and the first opening; and planarize the second metal layer until the surface of the dielectric layer is exposed. 9. The method for forming a bit line contact as described in item 8 of the scope of the patent application, wherein the peripheral circuit layer is an ion-doped region. 10. The method of forming a bit line contact as described in item 8 of the scope of patent application 0548-9072TWF (Nl); 91145; Claire.ptd Page 18 1237874 6. Patent application method, where the dielectric layer is an oxide layer. 1 1. The method for forming a bit line contact as described in item 8 of the scope of the patent application, wherein the oxide layer is a tetraethyl silicate oxide layer. 1 2. The method for forming a bit line contact as described in item 8 of the patent application, wherein the first metal layer is a titanium metal layer. 1 3. The method for forming a bit line contact as described in item 8 of the scope of the patent application, wherein the petrified metal layer is a matted titanium metal layer. 1 4. The method for forming a bit line contact as described in item 8 of the patent application scope, wherein the barrier layer is a titanium / titanium nitride layer. 1 5. The method for forming a bit line contact as described in item 8 of the patent application scope, wherein the second metal layer is a rhenium metal layer. 16. A method for forming a bit line contact, including the following steps: providing a semiconductor substrate having a peripheral circuit layer, and a transistor formed on the semiconductor substrate, the transistor having a gate and a A source drain region; a dielectric layer and a first patterned photoresist layer are sequentially formed on the semiconductor substrate, the first patterned photoresist layer has a first opening, and a position of the first opening is formed subsequently The position of the bit line contact window; using the first patterned photoresist layer as a post-etch mask, performing an anisotropic etching step on the dielectric layer to form a second opening, the second opening exposing the source The surface of the drain region, and the second opening is the bit line contact window formed subsequently; removing the first patterned photoresist layer; forming a polycrystalline silicon layer on the semiconductor substrate, and filling the polycrystalline silicon layer 0548-9072TWF (Nl); 91145; Claire.ptd page 19 1237874 6. The scope of the patent application is full of the second opening; the polycrystalline silicon layer is etched back to expose the surface of the dielectric layer, and the second opening is The polycrystalline silicon layer has a first predetermined depth; a titanium metal layer is compliantly formed on the surfaces of the dielectric layer and the polycrystalline silicon layer; and a tempering step is performed on the titanium metal layer to form the titanium metal layer. A stone metal drum metal layer is formed on a surface in contact with the polycrystalline stone layer; the unreacted titanium metal layer is removed, leaving the stone metal titanium layer on the surface of the polycrystalline silicon layer; on the dielectric A second patterned photoresist layer is formed on the layer, and the second patterned photoresist layer has a third opening, and the position of the third opening is the position of the contact window of the peripheral circuit layer to be formed subsequently; The photoresist layer is an etching mask. The dielectric layer is anisotropically etched to form a peripheral circuit layer contact window. The second patterned photoresist layer is removed. A third patterned light is formed on the dielectric layer. Barrier layer, the third patterned photoresist Cover the contact window of the peripheral circuit layer; use the third patterned photoresist layer as an etching mask to etch the dielectric layer to a second predetermined depth; remove the third patterned photoresist layer; on the semiconductor substrate, A barrier layer is compliantly formed on the surface of the titanium silicide metal layer and the peripheral metal contact window; a tungsten metal layer is formed on the barrier layer, and the tungsten metal layer fills the peripheral metal contact window and the second Speak; and 0548-9072TWF (Nl); 91145; Claire.ptd Page 20 1237874_ VI. Scope of patent application Flatten the ferrous metal layer until the surface of the dielectric layer is exposed. 17. The method for forming a bit line contact as described in item 16 of the scope of the patent application, wherein the peripheral circuit layer is an ion-doped region. 18. The method for forming a bit line contact as described in item 16 of the scope of patent application, wherein the dielectric layer is an oxide layer. 19. The method for forming a bit line contact as described in item 16 of the scope of patent application, wherein the oxide layer is a tetraethyl silicate oxide layer. 20. The method for forming a bit line contact as described in item 16 of the scope of the patent application, wherein the anisotropic etching step is reactive ion etching or plasma etching. 2 1. The method for forming a bit line contact as described in item 16 of the scope of patent application, wherein the barrier layer is a titanium / titanium nitride layer. 0548-9072TWF (Nl); 91145; Claire.ptd page 21