TWI237338B - Chip carrier capable of testing electric performance of passive components and method for testing the same - Google Patents

Abstract

A chip carrier capable of testing electric performance of passive components and method for testing the same are proposed, which includes at least a tested conductive trace formed on a substrate body for connecting a passive component, wherein the tested conductive trace has first and second conductive segments extended from the first and second contact points to the first and second fingers on the substrate body, respectively; at least a additional conductive trace which connects the second contact point of tested conductive trace with the testing pad formed on the bottom surface of the substrate body; at least a assisted conductive trace free of being connecting with passive components, being used to connect a third finger on the top surface of substrate body and the ball pad on the bottom surface of substrate body; and a solder mask coated on the top surface of substrate body to cover the tested conductive traces, assisted conductive traces and additional conductive trace, with openings formed to expose the first and second contact points, and the first and third fingers. A method for testing electric performance of passive components by using the chip carrier is also provided.

Description

1237338

V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a chip and a test method for the carrier, particularly a chip capable of rapid testing. [Prior technology] Electrical tests of passive components Wafer seeding does not need to change the design of the original wafer carrier and its test method. Ball Grid Array (BGA) technology, because of 苴 1 (: number of pins, heat dissipation capacity, electrical characteristics and surface adhesion yield, etc. ^ has better performance than conventional packages, so the application in semiconductor packaging: It has become widespread and has become the main research and development direction of related industries. In order to enhance the electrical properties of general ball grid array sealing parts, for example, to eliminate signal noise, it is often used in the package such as the substrate (Substrate) and other wafers. Passive components such as capacitors, resistors, and inductors are configured or bonded on the carrier. However, although the configuration of this circuit and electronic components can improve the electrical properties of the package, it is also due to the lower testability of passive components. The problem with the combination of test equipment and electrical testing problems of passive components on the substrate has led to the testing and yield limitation of this type of ball tree array package. Generally, if passive components are connected to the substrate of the package, The conventional surface mount technology (SMT) adheres the designed passive component to a predetermined conductive track (T race) on the substrate and waits for it. After the electrical test of the passive component is correct, the subsequent ball grid array packaging processes such as die bonding, wire bonding, sealing compound and solder ball implantation are performed; and if the passive component to be fixed is a Capacitor element 'generally connects the two ends of the capacitor to a ring ground layer (Grundund) and a ring-shaped power supply layer (P0wer) on the substrate respectively in a jumper manner.

1751] Shi Xipin.ptd Page 8 1237338

R 1 ng) as shown in Figure 1A, at this time, because the capacitor 11 is electrically connected at both ends: not = electrical, so the tester can use the ground layer i 2 and the power supply; Tomb belt. Ground pads 14 (Ground Pad) and power pads 15 (P〇wer pad) formed by 9 i H electric shell holes 16 (Via), as the electric fifth, the description of the invention (2) test points , And as shown in the first, a test adapter 20 (Test) ° and / Zebin probe head 2 1 (Probe Head) respectively connected to the total% grounding pad "and power 塾 15, # can be located by Substrate

Pad) array ’to easily complete the capacitor's smart electrical test steps. For the two passive components of resistance and inductance, the state of the board after connection will form a problem in electrical testing. This dagger is based on the characteristics of the use of resistance and inductance, which are connected in series. The conductive trace on the substrate = an example not shown in the figure. The resistance element 3 is serially connected to the first contact 32a and the second contact 32b of a conductive trace 32, and is arranged according to the wiring. The pads 35 (Finger) electrically connected to the first contact side and the BaU pads 37 (BaU pad) connected to the second contact side are respectively electrically connected to form a chip and a solder ball of the package. (Solder ball) & electrical connection relationship to the outside world; wherein, as shown in FIG. 2B, the bonding pad 35 (Finger) is located on the top surface of the substrate 30 and is connected to a wafer bonding pad on the wafer. Perform-Wire connection, and the solder ball pad 37 formed on the bottom surface of the substrate 30 is electrically connected to the top surface of the substrate 30 via the conductive through hole 36 of the substrate 30. Therefore, To measure the resistance value of the resistor 31 or its welding yield, it is necessary to use the wire pad 35 on the top surface of the substrate 30 and the ball pad 37 on the bottom surface, respectively. Alternatively the first contact 32a and the second contact point 32b of the test, the test probe head with a set of 2

1237338 V. Description of the invention (3) Do not touch the zinc wire pad 35 and the solder ball pad 37, but the situation is as shown in Fig. 3 'The two probe heads 21 are respectively located on the substrate 3 0 Above and below, it is inconsistent with the current 7 automated and standardized probe test system, and this method can only test a passive component twice, nor can it be performed like a conventional test system with a row of needles in the same plane. A fast and extensive electrical test of passive components. Except for this position, if the probe is installed at the base position, the welding wire on this side of the probe head will not change if the probe is installed. The package end contacts the (Ni / Au). The soldering ends are not extended beyond the wafer. The test method shown in Fig. 3 requires the probe head 2 丨 contacting the pad 30 on the top surface of the board 30, and the bonding wire of each conductive trace pad

= The different uses of the parts are different, and the arrangement position of the bottom surface of the solder ball pads 3 30 is generally arranged in a size that is difficult to standardize? Dependency test. At the same time, it may also be caused by the incorrect positioning of the δ Yuan Zhi's seal of the wire pad, resulting in incorrect electrical measurement arrangement. The conventional test method uses a probe head with two μ results. Pads, in addition to the aforementioned operation doors, the quality yield rate of the top of the substrate is reduced. This is due to the problem. When a wire pad is also formed, it is likely to be damaged or caused by the needle-like tip 1 of the probe head. The quality of the welding wire pad is degraded, and the phenomenon that the nickel-gold layer gold wire on the surface is not completely adhered is broken, and then the problem of subsequent welding wires is caused. Poor electricity generation, etc.

'For some resistive or inductive elements, ^ the conductive traces of the wire pad, that is, ^ the stomach is connected in series at both ends to form a fresh ball extending to the bottom surface of the substrate ^' one of the electrical traces is formed on the substrate The top of the line is extended by its two ends to the line pad. For such lines

1237338 V. Description of the invention (4) '— ~ --- Form a road layout, and a fast and standardized passive component is a major bottleneck in testing operations. / Difficulty It can be seen that if you want to improve the current quantity problems, the substrate design and wire-related peripheral costs that have been used for many years have risen sharply. Therefore, how to give up this and six ^; a kind of wafer carrier and its electrical properties Test: And can open another subordinate plan, quickly and automatically carry out the standard: No ^ No: change the bearing · Applicable to a variety of different device loading = cattle test, the same, will have to change the basis and nature that have been used for many years = | The peripheral cost has risen sharply because of & how to give it up :: 'pieces set q is automatically and automatically standardized,-/ π 2 can be applied to a variety of different devices for the test of the carrier cloth, "丨 品 良The rate is indeed for this-important research and development issues in the related field will not affect its J [Summary of the Invention] The text is heart-bound. Therefore, one object of the present invention is to change the design of the crystal moon carrier and test the passive element without substantially changing its test method. Another purpose of the wafer chip cutting parts and this matter is to provide electricity for the passive components in the chip carrier :::: The test method is too raw-the chip carrier and its test purpose Connection test: the wafer carrier of the electrical components of the moving element; another object of the present invention which can perform automatic elimination is two: and its test method. To test the "electrical chip of passive components", another object of the invention that can be quickly caught and r-line is to provide a carrier and its test party: to achieve the aforementioned and other purposes, root, ...; of Electrical measurement of passive components is possible; a test probe head method is available. The chip called “Gong Gong”, “two-touch rabbit a” and its test 1237338 V. Description of the invention (5) The wafer carrier for electrical test of the component includes: a substrate body, which has an upper surface and a lower surface Surface; at least one conductive trace to be tested 'that is intended to be connected to a passive component' includes a first and a second conductor segment which are not connected to each other, and two ends of the first conductor segment form a first contact and a first A wire bonding pad, and two ends of the second wire segment form a second contact and a second wire bonding pad respectively, so as to connect the passive component by the first and second contacts, wherein the first contact , The second contact, the first bonding pad and the second bonding pad are all located on the upper surface of the substrate body; at least one outer guide electrical trace is connected to the second contact of the conductive trace to be tested by A test pad formed on the lower surface of the substrate body; at least one auxiliary test conductive trace not connected to a passive component, two ends of which respectively form a third bonding pad on the upper surface of the substrate body and the substrate body Solder ball pads on the lower surface; And at least one solder resist layer, which is laid on at least the upper surface of the substrate body and covers the conductive trace to be tested, the auxiliary test conductive trace and the external guide electrical trace, and forms a plurality of at least the first contact exposed. Point, second contact, opening of first recording wire, third glow wire, etc. The test method of the present invention capable of electrically testing passive components is applied to a wafer carrier, and the substrate body of the wafer carrier The upper system is provided with a plurality of conductive traces. The method includes the following steps: selecting a conductive trace to be tested that is intended to be connected to a passive component, which comprises a first lead segment and a second lead segment that are not connected to each other. Two ends of the wire segment are respectively formed with a first contact and a first bonding pad, and two ends of the second wire segment are respectively formed with a second contact and a second bonding pad, so that the first 1. The second contact is connected to the passive component, wherein the first contact, the second contact, and the first bonding wire

175] 1 Shi Xipin. Ptd Page 12 1237338 V. Description of the invention (6) The pad and the second wire bonding pad are all located on the upper surface of the substrate body; the second contact of the conductive trace to be tested is externally connected An externally guided electrical trace is extended to the lower surface of the substrate body to form a test pad; an auxiliary test conductive trace that is not connected with a passive component is selected, and its two ends are respectively formed on the upper surface of the substrate body. A third bonding pad and a solder ball pad located on the lower surface of the substrate body; at least one solder resist layer is laid on the conductive trace to be tested, the auxiliary conductive trace and the outer guide electrical trace, and the solder resist layer is Forming a plurality of openings at least exposing the first contact, the second contact, the first bonding pad and the second fresh wire coil, and connecting the passive component to the first and second contacts of the conductive trace to be tested Point; electrically connect the first and third wire bonding pads on the substrate body with a conductive material; and connect the test pads and solder ball pads on the substrate body with two electrical test ends, and perform the passive component Electrical test. The aforementioned passive element refers to a resistive element or an inductive element, and the conductive material used refers to a conductive jig formed of conductive rubber, conductive metal, or other conductive materials; meanwhile, the first, second, At least one nickel-gold layer (Ni / An) is formed on the third wire pad, so as to form an electrical conduction relationship by the conductive material. Therefore, in the present invention, an optional auxiliary test conductive trace is selected from the plurality of conductive traces to connect the conductive jig with the first bonding pad and the third bonding pad on the upper surface of the substrate body. The test pads and solder ball pads on the lower surface of the substrate body respectively replace the electrical test points at the two ends of the passive component, so that the electrical test ends such as the electrical test probes can be in contact with the solder pads. In this case, only the most of the neatly arranged solder ball pads and the additional

] 75] 1 Shi Xipin.ptd Page 13 1237338 V. Description of the Invention (7) :: J is to complete the standardized electrical test of all passive components, and ^ change the design of the * carrier and apply to: tablets? Carriers' fully address the limitations of conventional technology. The door clothes are placed in the same way as [implementation method] 孰 朵 = Iί The specific embodiment is used to explain the implementation of the present invention. The present invention can be easily understood from the content disclosed in this description. Other points and effects, the present invention can also be implemented or applied by other different examples, the details in this specification are also decorated and applied, without departing from the spirit of the present invention Various i

The second part of the wafer carrier that can be used for electrical testing of passive components invented by Jia every t. The top view of the example is shown in Figure 4A, which can be used to test the passive element board. Ball grid array package (BGA) packaging base • It can be a laminated layer substrate or a layered broken jd_up layer multilayer board. The substrate 40 includes a FR4 resin,

A base body 4 1 (core layer) composed of a plate glass resin, a BT resin, an epoxy resin, and polyvinylamine. The substrate body 4 has an upper surface and a relatively lower surface, and the upper surface is arranged on the upper surface. There are a lot of patterned electrical trace layers 4 2, a chip preset area 4, 3, a packaging line 48, and an edge strip area 4 9 outside the packaging line, and the substrate body 41 is provided thereon. At least one preservative layer 4 4 (S ο 1 der M ask) to protect the plurality of conductive traces 4 2 and to prevent electrical interference from the outside. Wherein, the conductive trace layer 42 includes at least one conductive trace to be tested 50 and an auxiliary test conductive trace 70, and the conductive trace to be tested 50 is a series of passive components intended to be provided in series thereon. Conductive trace

17511 硅 品 .ptd Page 14 1237338 V. Description of the invention (8) The two ends respectively extend to the periphery of the chip preset area 43 to form the first glow wire 55 5 and the second bonding wire 塾 6 5 respectively, and the auxiliary The test conductive trace 70 is a conductive trace that is not connected to the passive component. One end is extended to the periphery of the chip preset area 4 3 to form a third bonding pad 75, and the other end is shown in the side view of FIG. 4B Is electrically connected to a solder pad 77 (Bali pad) on the lower surface of the substrate body 41 through its corresponding conductive through hole 76. The passive component is connected in series to the first contact 5 1 a and the second contact 5 1 b on the conductive trace 50 to be tested, as shown in FIG. 4A, so as to zone 50 of the conductive trace to be tested. It is divided into a first lead segment 50a and a second lead segment 50b, so that the first contact 5a and the first bonding pad 55 are the two ends of the first lead segment 50a, and At the two ends of the second contact, where 5 5 and the second bonding wire, the auxiliary measuring peripheral such as the power pad wire pad 7 5 extends the opposite of the bonding wire pad 75 and the electrical connection trace 50 of the boundary. , For the conductive 60 to be tested, as shown in FIG. 4B (Via Hole), the substrate package 5 1 b and the second bonding pad 6 5 become the first contact 5 of the second wire segment 5 0 b 1 a, the second contact 5 1 b, and the first bonding pad 6 5 are all located on the upper surface of the substrate body 4 1; the same test conductive trace 70 may be selected from the chip preset area 43 ( Vcc Finger) and ground pad (Vss Finger), etc. to any of the conductive traces on the lower surface of the substrate body 41, through the bond wire connection relationship of the wafer pads to form the wafer and the outer 'and the auxiliary test conductive traces Line 7 0 with the wait Conducting the test location is not limited. To achieve the purpose of measuring the electrical properties of passive components, the present invention also shows a side view of the second contact 5 1 b of the trace 50, which is externally connected to an outer guide electrical trace, and is thrown through its corresponding conductive through hole 6 6 The test pad 67 is connected to the lower surface of the substrate body 41 and the edge strip area 49 outside the bit line 48 to extend the test pad 67.

17511 石 夕 品 .ptd Page 15 1237338 V. Description of the invention (9) The first conductive wire segment 5 0 a is electrically connected to the external lead electrical trace 60 0 with a passive component. The aforementioned conductive trace layer 4 2 is A solder resist layer 4 4 is laid, which is formed by a plurality of openings through the design of the photomask to expose the predetermined exposed positions of the majority of the conductive trace layers 4 2, including the ends of the majority of the conductive trace layers 4 2. Welding pads 4, 5, 5, 6, 5 and 7 5, wherein the conductive pads of the conductive trace layer are formed at the end of the exposed conductive traces to form at least one nickel-gold layer (N i / Au), 俾The gold dow wire is welded in the subsequent process of Wie Β ο nd; at the same time, the mask of the solder resist layer 44 is also at the first contact 5 1 a and the second contact on the conductive trace 50 to be tested. An opening is formed at the contact 5 1 b position, and the surface is adhered in a subsequent process to connect the predetermined passive component in series. Therefore, when the wafer carrier of this embodiment is shown in FIG. 4B on the conductive trace 50 to be tested as a passive element 80 such as a resistor or an inductor, the first, The third bonding pad 5 5 and 75, so that the auxiliary test conductive trace 70 and the first lead segment 5 0 a of the conductive trace 50 to be tested form an electrical path, and use the auxiliary test The solder ball pad 7 7 of the conductive trace 70 replaces the first contact 5 1 a; at this time, the solder ball pad 7 7 can be used as a substitute test point for the first contact 5 1 a, and then the test Pad 6 7 is an alternative test point for the second contact 5 1 b, and the electrical test of the passive component 40 is completed by the electrical measurement of the ends of the solder ball pad 7 7 and the test pad 6 7 to solve the conventional problem. It is difficult to test smoothly. More specifically, in the present invention, as shown in FIG. 4C, a conductive jig 90 is placed on the solder resist layer 44 to contact and connect the first wire pad 5 5 and the third wire pad, respectively. 7 5 and further pressure steps to enable simultaneous contact

17511 石 夕 品 .ptd Page 16 ----- 5. Description of the invention (10) ---- — = The pad 55 and the third wire pad 75 form an electrical path; of which: material: r: 90 can be a conductive rubber, a conductive metal block, or other conductive jigs, and the shape and position of the conductive jigs 90 can be seen two (two with V child trace 50 and auxiliary test conductive trace 70 design position And $ = the jig used is a conductive metal block, and the tester often needs to change the metal block to resist the wire pad for the design of the identification part. = Φ 5 shape, however, if the jig used is a conductive rubber, Since the glue can be used as required, it can be applied to a variety of different design chip carriers to contact the first and third welding wires located at different positions (55, 1c): No, the conductive fixture is continuously changed 9 G Position to meet the requirements of different wafer bearing components. I | 3 While the machine is in the electrical test of the passive component 80, you can install ^ base = 40 on a conventional test adapter 2 〇 (丁 6 以 Socket) on the substrate 40 and a full review on the substrate 40 古 ^ ^ ^ + +, the seat 2 has a test probe head 21: = with a bottom surface facing the Standard probe spacing (Pr0be pft h) # "Nothing to do-set with ball pad 77, ... test; touch the test pad 67 and solder 4 disciple + judgment point element Electrical measurement of the passive component 40 ^ ^ Does not cause the money needle 21 to contact the substrate with failed solder wires 塾 65 and 75 (see Figure 4A), which affects the quality of the bond pads to help test the position of the conductive trace 70 or the solder ball pad 77 Can be at the auxiliary position, according to the test adapter 2. Above; = the test reaches-fast and accurate positioning test process, or twenty test ball pad positions to be tested formed by the circuit layout, Sheet carrier 1237338 V. Description of the invention ⑴) In accordance with the requirements of the test, please complete the sealing of the conductive part in the follow-up operation. Therefore, it is necessary to test the conductive passive components by testing the conductive parts to be connected with electrical traces to 6 7 in series, and then change all the welding wires in order. For example, test ball pads 7 7 can be replaced in order to reduce the replacement of the hair as described in paragraphs 5A to In the figure, a wafer carrying jig is selected, and then it is formed in the process of encapsulation. In the process of the present invention, the substrate is electrically connected in series with more than passive components by the outer guide trace 50 and the auxiliary electrical components at both ends. The position of the bottom surface of the conductive pad is determined by the complex test to achieve a fast and large number of commercial tests of the passive components 80 on the electrical test and remove, you can use the chip carrier to follow up Encapsulant encapsulation, without the short-circuiting of the conduction relationship or other reliability can be used to make electrical test traces of passive components 60 and conductive fixtures to help test conductive traces 70 to form test point transfer Limitation to the bottom surface of the substrate. This design can also pad 6 7 for another test point. The conductivity of the fixture is clearly shown in the figure 5E. One is scheduled and one passive majority is tested. Test the pilot, and then, the continuous cost and the moving element are the first. If the moving element is connected to the element, the bottom line of the test conductive traces is formed into a full row design, which can be equipped with the bonding pad to form a short test passive component phase to assist the test guide. The time required to perform the passive component test is shown in Figure 5A. The chip under test shown in Fig. 5A bears 9 0 'and is connected to the path to be used. The method is to connect an externally guided electrical test pad to the substrate 40, and at this time, the solderability test of the corresponding test pad electrical trace 70. The test method is used to measure the step diagram and longitudinal section electrical trace. Line 5 0, the

17511 Silicon product. Ptd Page 18 1237338 V. Description of the invention (12) The conductive trace 50 to be tested includes the first lead segment 50a and the second lead segment 50b which are not connected to each other. The two ends of the segment 5 0a form a first contact 5 1 a and a first bonding pad 55 respectively, and the two ends of the second wire segment 5 0b form a second contact 5 1 b and The second wire bonding pad 65 enables the passive component to be connected in series to the first and second contacts 50a and 50b, and at the same time, the first and second contacts 50a and 50b and the first The second and second wire bonding pads 55 and 65 are located on the upper surface of the substrate body 41. In addition, the conductive trace 50 to be tested is externally connected to an external guide electrical trace 60, which is connected by the second connection. Point 5 丨 b is connected to the lower surface of the " Hai substrate body 41, and a test pad 67 is formed on the area of the substrate edge strip area 49 outside the substrate packaging line 48; second, an unconnected passive component is arbitrarily selected The auxiliary test conductive trace 70, the two ends of the auxiliary test conductive trace J ^ respectively extend to the third zinc wire pad 5 of the upper surface of the substrate body 4 and the substrate body 4 1 7 7 On the lower surface of the solder ball pad. Next, as shown in FIG. 5B, at least one flux layer 44 'is laid on the substrate body 4 and a plurality of openings are formed, so that the solder resist layer 44 is exposed = ^ the conductive trace to be tested, the line 50 and Auxiliary tear · H-type conductive trace 70 is formed on the end of several conductive traces to form the glow pad of the conductive trace (not shown: 丨 Tongri Temple 'also exposes the conductive trace to be tested 5). The first contact point of contact-contact 5113 for subsequent passive component bonding; then, as shown in Figure f, a passive component 80 is connected in series to the second contact 518 of the conductive trace 50 to be tested As shown in FIG. 5D, a conductive substrate is connected to the first and third front lines 塾 75 of the anti-brightening agent layer 44 to form a test pad 67 via the passive element 80 and conductivity. The fixture 90 is electrically connected to the solder ball pad 77; finally, as

17511 Silicon products · ptd Page 19 1237338 5. Description of the invention (13), the substrate 40 is mounted on a test adapter 60, and a set of test probe heads 2 are used to contact the substrate respectively. The body = ^ = 塾 咖啡 球 塾 77 'to carry out the test by using the loop formed by the test pad 6 = the right needle 21. The electrical measurement of the passive component 80 is performed on the passive component 40. The passive component 40 is adhered to the exposed first and second contact occupying technology (SMT) and the line is disrupted. The younger brother is connected to 5 1 a, 5 1 b, and the conductive trace layer (two = and: opened at the outer UN 1 / Au) is formed, which are all known from ^ M 丄 invention, test method I won't go into details here. U ... Therefore, this needle is described in the kitchen: 棋 棋 i :: = ϊ This method can test the test probe of the adapter and a number of fresh balls on the TV surface. Standardized electrical tests for different circuit layouts. Fast and load-bearing components of one or more passive components one after another and: $ Trial $: Mingzhi A fast and standardized private chip that can perform electrical tests on passive components. It is indeed possible to perform one without changing the substrate design. The change of the wafer carrier is not caused by the fact that different probe heads have been tested in the test # 4 ~ θ. The test convenience is avoided, which can avoid testing the EC of the wafer carrier. Make sure that it is flat. The above-mentioned embodiments are only used for γ, but not for limiting the f ′, B. This does not explain the principle of the present invention and its effects, and makes the present invention. Anyone familiar with this skill can

17511 Silicon. Ptd Page 20 1237338

17511 Shi Xipin.ptd Page 21 1237338 Brief Description of Drawings [Simplified Description of Drawings] Figure 1 A is a top view of a conventional wafer carrier with a capacitor fixed on it; Figure 1 B is a conventional one with a capacitor fixed on it Figure 2A is a schematic diagram of the test of a capacitor wafer carrier; Figure 2A is a top view of a conventional wafer carrier with a resistor or an inductor fixed; Figure 2B is a side view of a conventional wafer carrier with a resistor or an inductor fixed; And FIG. 3 is not intended to test the conventional chip carrier with resistance or inductance fixedly attached. Figure 4A is a top view of a preferred embodiment of a wafer carrier of the present invention; Figure 4B is a side view of a preferred embodiment of a wafer carrier of the present invention; Figure 4C is a conductive fixture contacting the present invention Figure 4D is a schematic diagram of the electrical test of the wafer carrier of the present invention; Figures 5A to 5E are schematic flowcharts of the electrical test method of the present invention; 10 substrate 11 capacitor 12 Ground layer 13 Power layer 14 Ground pad 15 Power pad 16 Conductive through hole 20 Test adapter 21 Test probe head 30 Substrate 31 Resistance or inductance 32 Conductive trace

175ΠShi Xipin.ptd Page 22 1237338

Brief description of the drawing 3 2a First contact 32b Second contact 35 Welding pad 36 Conductive through hole 37 Solder ball pad 40 Substrate 41 Substrate body 42 Conductive trace layer 43 Wafer preset area 44 Solder resist layer 45 Welding pad 46 Conductive through hole 47 Solder ball pad 48 Encapsulation line 49 Edge strip area 50 Conductive conductive trace to be tested 5 0a First lead segment 50b Second lead segment 51a First contact 51b Second contact 55 First solder pad 60 Outer guide electrical traces 65 Second glow pads 66 Conductive through holes 67 Test 塾 70 Auxiliary test conductive traces 75 Second wire pads 76 Conductive through holes 77 Solder ball pads 80 Passive components 90 Conductive fixtures 17511 Silicon. ptd Page 23

Claims (1)

1237338 VI. Scope of patent application 1. A wafer carrier capable of electrically testing passive components, comprising: a substrate body having an upper surface and a relatively lower surface; at least one of which is scheduled to be connected to the passive component The test conductive trace includes a first lead segment and a second lead segment that are not connected to each other. Two ends of the first lead segment form a first contact and a first bonding pad, respectively, and the second lead The two ends of the segment are respectively formed with a second contact and a second bonding pad, so as to connect the passive component by the first and second contacts, wherein the first contact, the second contact, and the first bonding pad. The wire pad and the second wire bonding pad are both located on the upper surface of the substrate body; at least one outer guide electrical trace is formed by the second contact of the conductive trace to be tested being connected to the lower surface of the substrate body A test pad; at least one auxiliary test conductive trace without a passive component connected at both ends thereof forming a third wire pad on the upper surface of the substrate body and a solder ball pad on the lower surface of the substrate body; and At least one rejection An agent layer is laid on at least the upper surface of the substrate body and covers the conductive trace to be tested, the auxiliary conductive trace and the external guide electrical trace, and forms a plurality of exposed at least the first contact and the second The openings of the contacts, the first bonding wire pad, and the third bonding wire pad. 2. The wafer carrier of item 1 of the patent application scope, wherein the test pad is located on the edge of the carrier outside the packaging line of the wafer carrier. 17511 Shi Xipin · ptd Page 24 1237338 6. Scope of patent application 3. For example, the wafer carrier of the first patent application scope, wherein the passive element is a resistance element. 4. For example, the wafer carrier of the scope of patent application, wherein the passive element is an inductive element. 5. For example, the wafer carrier of the scope of patent application, wherein the wafer carrier is a package substrate. 6. For example, the wafer carrier of the scope of the patent application, wherein the passive component is connected in series on the conductive trace to be tested by surface bonding technology (SMT). 7. A test method capable of electrically testing passive components, which is applied to a wafer carrier. The substrate body of the wafer carrier is provided with a plurality of conductive traces. The method includes the following steps: selecting a predetermined The conductive trace to be tested connected to the passive component includes a first lead segment and a second lead segment that are not connected to each other, and two ends of the first lead segment form a first contact and a first bonding wire, respectively. Pads, and two ends of the second wire segment are respectively formed with a second contact and a second bonding pad, so as to connect the passive component by the first and second contacts, wherein the first contact, the first The two contacts, the first bonding pad, and the second bonding pad are all located on the upper surface of the substrate body; an external guide electrical trace is connected from the second contact of the conductive trace to be tested to extend to the A test pad is formed on the lower surface of the substrate body; an auxiliary test conductive trace without a passive component connected is selected, and two ends of the third bonding wire are respectively formed on the upper surface of the substrate body 1751] 石 夕 品 .ptd page 25 1237338 VI. Patent application pad and solder ball pad located on the lower surface of the substrate body; Laying on the conductive trace to be tested, the auxiliary conductive trace and the outer guide electrical trace At least one solder resist layer, and the solder resist layer forms a plurality of openings at least exposing the first contact, the second contact, the first wire pad and the third wire pad; and connecting the passive component to the The first and second contacts of the conductive trace to be tested; electrically connect the first and third wire pads on the substrate body with a conductive material; and connect the test on the substrate body with two electrical test ends Pads and solder ball pads, and perform electrical tests on the passive components. 8. The test method according to item 7 of the scope of patent application, wherein the test pad is located on the edge strip area of the carrier outside the package line of the wafer carrier. 9. The test method according to item 7 of the scope of patent application, wherein the conductive material is a conductive jig formed of a conductive rubber. 10. The test method according to item 7 of the scope of patent application, wherein the conductive material is a conductive jig formed of a conductive metal block. 1 1. The test method according to item 7 of the scope of patent application, wherein the passive element is a resistance element. 12. The test method according to item 7 of the scope of patent application, wherein the passive element is an inductive element. 13. The test method according to item 7 of the scope of patent application, wherein the wafer carrier is a substrate. 17511 石 夕 品 .ptd Page 26 1237338 VI. Application for patent scope 1 4. If the test method for the scope of patent application item 7 is used, the passive component is connected in series by the surface adhesive technology (SMT) Test the conductive traces. 15. The test method according to item 7 of the scope of patent application, wherein the electrical test terminal is a test probe (P r) of a test system. 175ΠShi Xipin.ptd Page 27