：twf.doc/c 九、發明說明： 【發明所屬之技術領域】 本發明是有關於半導體的製造方法與結構，且特別 是有關於一種在記憶胞區及週邊電路區内具有雙重間隙壁 之記憶體元件的製造方法與結構。 【先前技術】 積體電路是眾所皆知的。積體電路一般被應用在製 造廣泛且多樣化的電子元件’例如記憶體晶片。其中，對 於改變積體電路的大小以便增加個別元件的密度及相對地 提高積體電路的機能性具有強烈的需求。當圖案寬度減 小，元件的密度就增加，而高寬比也隨之增加。然而，較 大的高寬比是起因於小間隙分離於基底上的圖案之形成， 而會降低蝕刻製程及沈積製程的有效的製程窗。舉例來 說，隨著元件密度及造成間隙的記憶胞閘極圖案的高寬比 增加’在積體電路記憶體上之記憶胞區内之时電H 隙填充製程及>5夕化物沈積製程窗會變小。 此外，對兩個以上的電路區所組成的元件， 記憶體元件，電路輯在料财巾 如疋 求。例如，在記憶體元件中，記憶胞區需 密度，而-些週邊的電路則需要高崩潰電壓二又及咼 在製造小圖案的積體電路之製程’就像是奴用 (sidewall spacer)。侧壁間隙壁按照間隙壁的* 土間隙壁 義圖案’且儘可能使間隙壁的寬度小於微“„定 案寬度 '然而，在不同的區域上有不同的=的取小圖 W丁需求，這是 I236l ^f.doc/c 因為例如，用側壁間隙壁所定義出來的圖案可應用在積體 電路中的某個區域，但也許不適合被用在另一區域。 ^ 因此需要一種方法與結構，能在記憶體晶片以及其 =具有多樣化的電路區之積體電路元件上達到這些不同的 執行需求。 【發明内容】 Q此’本發明的結果解決了在以往技術中所存在的 =。:種雙朗隙壁的製程被揭露並應用在製造數個電 的二的1中’例如記憶體元件。而多數電路區有著不同 &二隙ΐ寬度，例如對記憶體元件來說，可同時改善記憶 與週邊70件的功效。對記憶體元件而言，雙重 二 ：：：被使來減少記憶胞的大小及減少製程複雜度， 中屯路區達到所需的高電壓效果。在揭露的範例 士己情^ 的合成間隙壁比週邊電路區的間隙壁薄。而 寬^㈣的間隙壁會增加開 口的寬度，因此會減小高 見比，且改善内介雷Μ 矽化物沈積製裎介（mtedayer di士ctric，ILD)填充與 作下可獲得P‘二:而週邊區内較厚的間隙壁在高電壓操 方面彳友照所;}0¾ 重間隙壁之積雕、、帝u路的技術，提供了一種製造具有雙 為第一區域和品的方法。在這個方法中，一個基底分 鄰的第—半、，辦U區域。其中，第一區域包括至少兩個相 間。而第二^^圖案/且開口介於兩第一半導體圖案之 區域與第—:(則包含〜第二半導體圖案。然後，在第一 〜品域上形成中止層。接著，於第二區域的中止 6 123 67^ j682twf.doc/c 層之上形成間隙壁層。隨後，間隙壁層被圖案化，以在第 二半導體圖案的侧壁上形成一間隙壁。接著，進行一韻刻 製程，以在第一半導體圖案之間的開口内侧的側壁上形^ 一個結果的間隙壁。最後’去除在第一及第二半導體圖案 之頂部表面上之中止層。 μ 依照另一方面，本發明提出一種具有雙重間隙壁之 積體電路。在這個結構中，一個半導體基底具有第一區域 及第二區域。第一區域包含至少兩個相鄰的第一半導體圖 案，且開口介於兩第一半導體圖案之間。而第二區域則包 含第二半導體圖案。其中，中止層在第一半導體圖案間的 開口内侧侧壁上，並在第二半導體圖案側壁以及在第二區 域之基底相鄰部分上。此外，間隙壁位於第二區域的中止 層表面上。 為讓本發明之上述和其他目的、特徵和優點能更明 顯易懂’下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 接下來詳述本發明的實施例，實施例將以附圖解釋。 在儘可能的情況下，圖解中相同或相似的參考數字，用於 描述相同或相似部分。其描繪圖是簡式形式，並非精確的 尺寸大小。以下的描述對於方向的用詞，只是為了方便說 月例如·頂部、底部、左邊、右邊、上、下、在··之上、 之下以及後方’都是搭配圖示說明所使用的，但其非 用乂限疋本發明之應用範圍，而僅為舉例之用。 ：twf.doc/c μ Γ ί ΐ此揭露"'些較佳實施例，.但應知這些實施例 Ρ而非用以限定。雖然詳述舉例用的實施例，但 :述之⑤義是被理解為涵蓋實施例之所有更動、 =目！’並落入後附之申請專利範圍所界定之本發明 的精神和範圍内。 圖1至圖1〇是繪示依照本發明之實施例的詳述示意 圖。 、、:二考圖卜―個半導體結構具有包括記憶胞區3以 及週、^區5的-基底卜其中，記憶胞區3是第一區 域的種㈣’其係被製造成具有薄側㈣㈣，而週邊 5疋，_區域的_種範例，其係被製造成具有厚側 壁間隙壁。藉由介電區域13隔離記憶胞區3及週邊電路 區5。、其中，介電區域13是利用區域氧化法(LOCOS)或 ”他白4之技術，在一溝渠内沈積氧化物或其它介電質而 形成。 、 在圖不6兒明中，記憶胞區3包含至少兩相鄰之快閃 記憶體堆疊閘極9、介於堆疊閘極9間之開口 1Q(亦稱為 二間隙)以及在堆疊閘極9每—侧之基底i中形成的數個 6雜區15，用以作為源極和没極。而其餘的堆疊問極由 一開口 7而與上述之兩相鄰堆疊閘極分隔開。其中，開口 7比上，之開π 1。來得寬’可提供—接觸窗在此形成， 例如疋貫〜例巾提供的可抹除可編程唯讀記憶體穿隨氣化 詹(EPROM W1th tunneling oxide，ΕΤ〇χ)之快閃記憶胞。 另外’堆疊閘極9在實施例上稱為第—半導翻案，且於 I2367^i82twf.d〇c/c 上形成有較薄之側壁間隙辟，、， 9A、多晶石夕浮置間極紐、二亚包括多晶石夕電晶體閉極 介電層9D。此外，在苴他晶矽介電層9C以及穿隧 括但不限於石夕_氧化石夕1、，$施例中的別種記憶胞結構包 胞’其堆疊閘極結構包括>電》::氧化矽·矽(SONOS)記憶 極。在本發明不_實施^认氮化物層而不是浮置間 體層，例如是兩個多轉堆疊間極9包含至少兩道 層。 q或—多晶矽化層及兩多a 此外’週邊電路區5包 以於邏輯、高電壓電路及‘二通道及p通道電晶體， (supporting η +·、 。己^胞區的其他電路維持運作 電晶體，’㈣憶皰區包括—具有代表性之 ::曰二:中此電晶體包含一電 ”屯層11A以及在閘極結構n # ^ ^ -挾k 再11的母一側邊之基底1内的 散的源極和汲極之第一植入15係：來當作雙重擴 , H ^ 币稂八^域。而電晶體閘極結構11 疋夕日日矽，在本貫施例中當作是“第二半導體圖案，，， 二上形成有較厚之侧壁間隙壁。電晶體的問極結構Η包 ^少—導體層’例如是-多㈣層或是—多晶梦層和一 多晶石夕化金屬層。 在形成堆疊閘極(9A-9D)和電晶體閘極（U，11A)圖案 之後，在記憶胞區3和週邊電路區5之半導體基底丨上形 成一介電層19。因此，此介電層19保角地覆蓋堆疊閘極 (9A-9D)和電晶體閘極（11，11A)結構的表面，還包含介於 此堆疊閘極(9A-9D)之間的兩開口（7，1〇)之内側壁。在此實 I23673lJ682twf.doc/c 例中的介電層19是由常見的熱氧化製程所形成的氧化層 膜，其厚度介於20A〜300A。其中，當圖案化堆疊閘極曰9 和電晶體閘極11結構時，典型使用熱氧化製程來成長兩 個氧化層並熱回火半導體基底丨，以修補所造成的損害。 圖2描述於圖丨所示之介電層19上形成一中止層21。 此中止層21是具有不同於被形成的下一層之蝕刻性質的 層。於此實例中，中止層19包括氮化矽膜，其二般 是藉由化學氣相沈積製程所形成。也可用其它適合作為蝕 刻中止用的材料。對氮化矽化學氣相沈積製程而言，合適 ，化學氣相沈積製程之前驅物為二氣矽烷以及氨 氣(NH3)或氮氣(N2)。在這個例子中，中止層2ι的厚度介 於20A 3⑻A之間。此外，在圖4中描述之中止層對製 程而言就像是姓刻中止層。 …ϊί，如圖,3所示，在中止層21上形成-間隙壁層 ς ’ ^間隙壁層包括藉由-般的CVD製程所形成 的=貝，其於這個例子中是TE0S氧化層膜。且在這個 例子中的間隙壁層23的厚度介於5G0A〜2GGGA之間。 列制所"V在魏胞^3㈣隙壁層23是經由钱 刻衣私去除’且較佳係⑽射止層2 程。之後，在保護週邊電路區5的間隙壁声23 ::;:: 一圖案化絲層25， 層2,裸露出之記憶胞區3中二^^23以=光= 而電路區5上的部分間隙壁層23。 除[心月⑶3上的間隙壁23期間，中止層21就是 I23673J682twf.d_ 當作姓刻中止層用。 明參照圖5，一間隙壁27被形成於週邊電路區5之 電晶體閘極結構u的側壁上之中止層21表面上。如圖所 不，一圖案化光阻層53被形成於保護記憶胞區3的中止 ^ 21之上，且暴露出週邊電路區5中的間隙壁層23。接 著，對圖案化光阻層53所暴露出的間隙壁層23進行一第 -姓刻製程’以形成另-間隙壁27 ’其中此触刻製程較 佳係使用非等向性則製程。此外，只要數量控制得宜， 在，邊_步驟中去除—些介電層19及中止層21是可被 fit $外’在侧製程後，完成的間隙壁27寬度是 層23的厚度所決定’其中間隙壁層23的厚度結 口了閘極結構11側邊上的介電層19及中止層21之厚度。 本/施例中關隙壁27在週邊電路電晶體的源極以 ?或疋及極區域中就如同摻質植入區(dopant _lan⑽ t s ~/场成雙重擴散源極和汲極的結構，因此以增加 圖中树製)上的崩潰電壓來改善高電壓運作。而 區5内的間隙壁27，例如是用來製造高電壓 二要可以製造成厚的部位而不影響記憶胞區 —實例中，受限於記憶胞參數限制， W奴間隙壁寬度從驗7微米被增加 至〇· 14 U米而不會犧牲記憶胞密度。 :請t照圖6 ’因為此“的原因，使得第-線 :後進彳-^ 31由介電層19和巾止層21所組成。 ^後進仃H刻製程1移除包括在堆疊閘極9頂 I2367U82_c Γ之結構11以及在記憶胞區3和週邊電路區 底上的介電層19和中止層21。這將留下基 &上、位於記憶胞區的記憶胞之源極與沒極 3^=位於週邊電路區的電晶體之源極與沒極區 的：二而弟一線結構29被形成於堆疊閘極9的側壁 曰1〇及開口 7的内側壁。第二線結構31則 邊電路區5之電晶體間極結構η的側壁上 區3中的土4 ® 曰’弟線結構29是作為記憶胞 中的隹$閘極9側壁上的結果的間隙壁。這個結 二ί d比Γ於週邊電路區5中的電晶體閘極結構11 邊區；得薄。因此’可了解在記憶胞區3與週 %路區5中形成了雙重間隙壁結構。 再於圖7’於圖6所示之結構上形成—覆蓋層33， 来；，:、％路區5的電晶體閘極結構11以及基底1之相 盖層33上形成—圖案化光阻層54在此例 张田土復33包括一種除了在源極區與汲極區上之後 =者的介電質。在本範例中，覆蓋層33是經由一般的 積製程所形成的氮切，且於—已知的抗_ =化物㈣st protective 〇xide，Rp〇)製程中代替二氧化 。而此覆盖層33的厚度較佳係介於2〇人〜3〇〇A之間。 、％路£ 5中被光阻層54裸露之覆蓋層33， 心義週邊電㈣5中的—_化覆蓋層55，以及記憶 123673^2—。 ，區3巾的一合成間_ 34。其巾，此圖案化覆蓋声％ 才形成於電晶體閘極11的表面、間隙壁27的表面以k 邊電路區5的基底1之相鄰部分56上的至少—部分。再 者’由介電層19、中止層21以及覆蓋層33所^的人 成間隙壁34被形成於堆疊閘極9的侧壁上。在此實施二 中，覆蓋層也被由側壁間隙壁27的側壁表面去除只=並 不是所有的情況都是如此。 μ 一: Twf.doc / c IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method and a structure for manufacturing a semiconductor, and more particularly to a method having a double gap wall in a memory cell region and a peripheral circuit region. Manufacturing method and structure of memory element. [Prior art] Integrated circuits are well known. Integrated circuits are generally used in the manufacture of a wide variety of electronic components, such as memory chips. Among them, there is a strong demand for changing the size of an integrated circuit in order to increase the density of individual components and relatively improve the functionality of the integrated circuit. As the pattern width decreases, the density of the component increases, and the aspect ratio increases. However, the larger aspect ratio is due to the formation of the patterns separated on the substrate with small gaps, which will reduce the effective process window of the etching process and the deposition process. For example, as the element density and the height-to-width ratio of the gate pattern of the memory cell that causes the gap increase, the electrical H-gap filling process and the > chemical deposition process in the memory cell area on the integrated circuit memory The window will become smaller. In addition, for components composed of more than two circuit areas, memory components, circuits, etc., as required. For example, in a memory device, the memory cell area needs density, and some peripheral circuits require high breakdown voltages, and the process of manufacturing integrated circuits with small patterns is like sidewall spacers. The side wall partition wall shall follow the * soil partition wall definition pattern of the partition wall and make the width of the partition wall as small as possible as small as possible. However, in different areas, there are different requirements for taking small pictures. It is I236l ^ f.doc / c because, for example, the pattern defined by the side wall spacer can be applied to one area of the integrated circuit, but may not be suitable for use in another area. ^ Therefore, there is a need for a method and structure that can meet these different execution requirements on memory chips and integrated circuit components with diverse circuit areas. [Summary of the Invention] The result of the present invention solves the problem that exists in the prior art. : A double-long gap wall manufacturing process is disclosed and applied in the manufacture of several electric two's such as memory elements. And most circuit areas have different & two gap widths, for example, for memory components, it can improve the memory and the efficiency of 70 peripherals at the same time. For memory components, the dual two :: is used to reduce the size of the memory cell and reduce the complexity of the process, and the Zhongtun Road District achieves the required high-voltage effect. In the example disclosed, the self-made synthetic spacer wall is thinner than that of the peripheral circuit region. The wide wall will increase the width of the opening, so it will reduce the high visibility, and improve the filling and operation of the internal dielectric M silicide deposition system (mtedayer di ctric (ILD)) filling and operation can obtain P'2: The thicker partition wall in the surrounding area can be used in high-voltage operation. You can use the technique of carving and designing the partition wall to provide a method for manufacturing the first area. In this method, a base is adjacent to the first half of the region, which is the U region. The first region includes at least two phases. The second ^^ pattern / and the opening is between the region of the two first semiconductor patterns and the first-:( then contains ~ the second semiconductor pattern. Then, a stop layer is formed on the first ~ product region. Then, in the second region The stop layer 6 123 67 ^ j682twf.doc / c layer is formed on the spacer layer. Subsequently, the spacer layer is patterned to form a spacer wall on the side wall of the second semiconductor pattern. Then, a rhyme-engraving process is performed. To form a gap wall on the inner side wall of the opening between the first semiconductor patterns. Finally, the stop layer is removed on the top surfaces of the first and second semiconductor patterns. Μ According to another aspect, the present invention An integrated circuit with a double gap wall is proposed. In this structure, a semiconductor substrate has a first region and a second region. The first region includes at least two adjacent first semiconductor patterns, and the opening is between the two first regions. Between the semiconductor patterns. The second region includes the second semiconductor pattern. The stop layer is on a sidewall of the inside of the opening between the first semiconductor patterns, and on the sidewall of the second semiconductor pattern and on the first side. On the adjacent part of the base of the second region. In addition, the spacer wall is located on the surface of the stop layer of the second region. In order to make the above and other objects, features, and advantages of the present invention more obvious and easy to understand In conjunction with the accompanying drawings, the detailed description is as follows. [Embodiment] Next, the embodiments of the present invention will be described in detail, and the embodiments will be explained with the drawings. Whenever possible, the same or similar reference numerals in the diagram, It is used to describe the same or similar parts. The drawing is a simplified form, not an exact size. The following description of the wording of the direction is only for convenience to say the month, such as top, bottom, left, right, up, down, Above, below, and behind are used in conjunction with the illustrations, but they are not intended to limit the scope of application of the present invention, but are for example only: twf.doc / c μ Γ ί Here are some of the preferred embodiments, but it should be understood that these embodiments P are not intended to limit. Although the examples are described in detail, the meaning of the description is understood to cover all of the embodiments. Change, = ！ 'And fall within the spirit and scope of the present invention as defined by the scope of the attached patent application. Figures 1 to 10 are detailed schematic diagrams illustrating embodiments according to the present invention. Each semiconductor structure has a base substrate including a memory cell region 3 and a perimeter region 5 where the memory cell region 3 is a species of the first region. Its system is manufactured to have thin side regions, and the periphery 5 regions, _ Examples, which are manufactured to have thick sidewall spacers. The memory cell region 3 and the peripheral circuit region 5 are isolated by a dielectric region 13. Among them, the dielectric region 13 is a region oxidation method (LOCOS) or " The technique of Tab 4 is formed by depositing an oxide or other dielectric in a trench. As shown in Figure 6, the memory cell region 3 contains at least two adjacent flash memory stack gates 9, and The openings 1Q (also referred to as two gaps) between the stacked gates 9 and a number of 6 miscellaneous regions 15 formed in the substrate i on each side of the stacked gates 9 are used as the source and the non-electrode. The remaining stack electrodes are separated from the two adjacent stack gates by an opening 7. Among them, the opening 7 is higher than the opening π 1.来得 宽 ’can be provided—the contact window is formed here, for example, the erasable programmable read-only memory provided by the conventional wiper is a flash memory cell of EPROM W1th tunneling oxide (ETOX). In addition, the stacked gate electrode 9 is referred to as the first semiconducting reversal in the embodiment, and a thinner sidewall gap is formed on I2367 ^ i82twf.d0c / c. The pole electrodes and the two sub-layers include a polycrystalline silicon transistor closed-electrode dielectric layer 9D. In addition, in the Suntar silicon dielectric layer 9C and the tunnel tunnel including but not limited to Shi Xi _ Shi Xi Xi 1, and the other types of memory cell structure in the example embodiment, its stacked gate structure includes:> : Silicon oxide silicon (SONOS) memory pole. In the present invention, a nitride layer is not implemented instead of a floating interlayer, for example, two multi-turn stacked interlayers 9 include at least two layers. qor—Polycrystalline silicon silicide layer and two or more a In addition, the peripheral circuit area 5 packs logic, high-voltage circuits and two-channel and p-channel transistors, (supporting η + ·,. The other circuits in the cell area remain operational Transistor, the “㈣Memory” region includes-representative :: said two: the transistor contains an electric "tunnel 11A" and the gate side of the gate structure n # ^ ^-挟 k and 11 The first implanted 15 series of scattered source and drain electrodes in the substrate 1 are to be treated as double expansion, H ^ coin ^ 域 domain. And the transistor gate structure 11 疋 疋 矽 silicon, in this embodiment It is regarded as "the second semiconductor pattern." A thicker sidewall spacer is formed on the two. The transistor structure of the transistor contains less-the conductor layer is, for example, a polysilicon layer or a polycrystalline dream. Layer and a polycrystalline silicon metal layer. After forming the stacked gate (9A-9D) and transistor gate (U, 11A) patterns, they are formed on the semiconductor substrate of the memory cell region 3 and the peripheral circuit region 5 A dielectric layer 19. Therefore, the dielectric layer 19 covers the surface of the stacked gate (9A-9D) and the transistor gate (11, 11A) structure conformally, and further includes a dielectric The inner side wall of the two openings (7, 10) between the stacked gates (9A-9D). Here, the dielectric layer 19 in the example I23673lJ682twf.doc / c is formed by a common thermal oxidation process The oxide layer film has a thickness between 20A and 300A. Among them, when the stacked gate electrode 9 and the transistor gate 11 structure are patterned, a thermal oxidation process is typically used to grow two oxide layers and thermally temper the semiconductor substrate. The damage caused is repaired. Fig. 2 depicts forming a stop layer 21 on the dielectric layer 19 shown in Fig. 丨. This stop layer 21 is a layer having an etching property different from that of the next layer to be formed. In this example, The stop layer 19 includes a silicon nitride film, and the second is generally formed by a chemical vapor deposition process. Other materials suitable for etching stop can also be used. For the silicon nitride chemical vapor deposition process, a suitable chemical The precursors of the vapor deposition process are digas silane and ammonia (NH3) or nitrogen (N2). In this example, the thickness of the stop layer 2m is between 20A and 3⑻A. In addition, the stop layer is described in FIG. 4 To the process, it is like the suspension of the last name. ... ϊί, such as As shown in FIG. 3, a spacer wall layer is formed on the stop layer 21. The spacer wall layer includes a bead formed by a general CVD process, which is a TEOS oxide film in this example. And in this example The thickness of the interstitial wall layer 23 is between 5G0A to 2GGGA. The train station "V in Wei Wei ^ 3 The interstitial wall layer 23 is removed through money cutting clothes, and it is preferably a two-pass radiographic stop layer. After that, in the gap wall sound 23 protecting the peripheral circuit area 5 ::; :: a patterned silk layer 25, layer 2, and the exposed memory cell area 3 ^^ 23 in the light of the circuit area 5 Part of the gap wall layer 23. Except for the gap wall 23 on [心 月 ⑶3], the suspension layer 21 is I23673J682twf.d_, which is used as the last name for the suspension layer. Referring to Fig. 5, a gap wall 27 is formed on the surface of the stopper layer 21 on the side wall of the transistor gate structure u of the peripheral circuit region 5. As shown in the figure, a patterned photoresist layer 53 is formed on the stop region 21 of the memory cell region 3, and the spacer layer 23 in the peripheral circuit region 5 is exposed. Next, the spacer layer 23 exposed by the patterned photoresist layer 53 is subjected to a first-last engraving process 'to form another spacer wall 27'. The touch-etching process is preferably an anisotropic process. In addition, as long as the quantity is properly controlled, in the edge step, some dielectric layers 19 and stop layers 21 can be removed. The width of the completed spacer 27 after the side process is determined by the thickness of the layer 23 ' The thickness of the spacer layer 23 is the thickness of the dielectric layer 19 and the stop layer 21 on the sides of the gate structure 11. In this embodiment, the gap wall 27 is like a dopant implanted region (dopant_lan⑽ ts ~ / field) in the source or drain region of the peripheral circuit transistor, and the field has a double-diffused source and drain structure. Therefore, the high voltage operation is improved by increasing the breakdown voltage on the tree). The gap wall 27 in zone 5 is used to make high voltages, for example, and it can be made into thick parts without affecting the memory cell area. In the example, due to the limitation of the memory cell parameters, the width of the gap wall from the test 7 Microns are increased to 0.14 U meters without sacrificing memory cell density. : Please refer to Figure 6 'because of this', the first line: post-injection- ^ 31 is composed of the dielectric layer 19 and the stop layer 21. ^ post-induction H-etching process 1 is removed and included in the stack gate 9 top I2367U82_c Γ structure 11 and dielectric layer 19 and stop layer 21 on the bottom of the memory cell area 3 and the peripheral circuit area. This will leave the source of the memory cell on the base & The electrode 3 ^ = the source and non-electrode regions of the transistor located in the peripheral circuit area: the second and first line structure 29 is formed on the side wall of the stacked gate 9 and the inner wall of the opening 7. The second line structure 31 Then the soil 4 ® in the upper region 3 of the side wall of the transistor interelectrode structure η of the side circuit region 5 is referred to as the “brilliant wall structure 29” as a result of the gap on the side wall of the gate 9 in the memory cell. The ratio d is thinner than the edge region of the transistor gate structure 11 in the peripheral circuit area 5; it is thinner. Therefore, it can be understood that a double-spacer structure is formed in the memory cell area 3 and the peripheral circuit area 5. Further, FIG. 7 ' Formed on the structure shown in FIG. 6-a cover layer 33, is formed on the transistor gate structure 11 and the phase cover layer 33 of the substrate 1 The patterned photoresist layer 54 in this example Zhang Tian Tu Fu 33 includes a dielectric other than the source and drain regions. In this example, the cover layer 33 is formed by a general integration process Nitrogen cutting, and replacing the dioxide in the known anti-protective compound (Rp) process. The thickness of the cover layer 33 is preferably between 20 and 300A. The covering layer 33 exposed by the photoresist layer 54 in the% way £ 5, the -_ covering layer 55 and the memory 123673 ^ 2 in the heart electrode 5, a synthesis room of the area 3 towel_34. At least one part of this patterned covering sound is formed on the surface of the transistor gate 11 and the surface of the gap 27 on the adjacent part 56 of the substrate 1 of the k-side circuit region 5. Furthermore, 'dielectric The artificial gap wall 34 formed by the layer 19, the stop layer 21, and the cover layer 33 is formed on the side wall of the stacked gate 9. In this second embodiment, the cover layer is also removed by the side wall surface of the side wall gap wall 27 = This is not the case in all cases. Μ 1
、隨後，請參照圖9，一種例如是鈷化矽之矽化物結構 35被形成在堆疊層閘極9和電晶體閘極結構η的至^一 部分頂部表面上，以及在記憶胞區3和週邊電路區5 ^基 底1的裸露表面上。其中，矽化物結構35的形成減少$ 幵 =成於其上的位元線與字元線的阻值。而減少阻值可以轉 、欠為提鬲運作速度。另外，藉由記憶胞區中的較薄間隙壁， y放寬碎化物形成之階梯覆蓋製程(step coverage proctss) *度，進而得到較好的製造良率。其中，圖案化覆蓋層Μ 防止石夕化物結構在保護區形成。Then, please refer to FIG. 9. For example, a silicide structure 35 of silicon cobaltate is formed on a top surface of the stacked gate 9 and the transistor gate structure η, and on the memory cell area 3 and the periphery. The circuit area 5 is on the exposed surface of the substrate 1. The formation of the silicide structure 35 reduces the resistance of the bit line and the word line formed thereon. And reducing the resistance value can reduce the speed of operation. In addition, through the thinner gaps in the memory cell area, y relaxes the step coverage procts * formed by the fragmentation, thereby obtaining better manufacturing yields. Among them, the patterned cover layer M prevents the petrochemical structure from being formed in the protected area.
接著，請參照圖10，在矽化物結構形成之後，一種 例如是氮化矽的無邊界中止層（borderless stop layer)58被 开^成在基底上。然後’ 一層内介電(interlayer dielectric，ILD) 真充物100被形成在無邊界中止層％之上。典型的内介 =填充物100是由習知的製程所沈積而成，其材質例如 疋一氧化矽。因為在記憶胞區之較薄的間隙壁，增加了内 介電層填充物100的製程窗裕度。舉例來說，在製程中被 填充的間隙由大約011微米增加到0·2微米的話，會大 13 I23673li82twf.d〇c/c 大的改善其可靠性而不 =及接觸窗結構1G1被形成於記憶胞區“ 上，其係藉由包括二I 的接觸祕刻、银刻接觸窗之 層兄以及一接觸窗金屬填 ]内的邊界t止 另外，由於記憶胞區3⑽薄側壁: 接 體。例如，由t厚側壁而維持週邊電路區的高電壓電晶 寬開口，所以益邊5f中胞^及極側根據本發明所供應的較 声，&邊界中層可確實形成較習知更大的厚 又在接觸窗蝕刻過程中有叫好的製程窗裕度。 的雔尤其適合具有小記憶胞尺寸及高密度記憶體 、又s :长壁快閃記憶體之製造，且其在週邊電路區中有 積集的高電壓電路。 綜上所述，本發明之優點包括·· 么丨·本發明提供了一種雙重間隙壁的製程與結構。而記 憶胞與週邊電路有不同的間隙壁寬度。其中，合成間隙壁 ^在週邊電路區之電晶體閘極結構的間隙壁來得薄。而記 憶胞的可靠度及週邊電路元件雜能可同時被改善。元件 上之記憶胞的合成間隙壁得到低應力，並改善資料保持力 (data retention)。而週邊電路區的間隙壁可以得到較 崩潰電壓運作。 2·雙重間隙壁製程與結構滅少了記憶胞的大小以及 低製造的困難性。 14 I2367^82twfdoc/c 3. 、合成間隙壁被形成在堆4閘極之間的開口内側側辟 上。此合成間隙壁降低藉由—般的方法製造的間隙壁寬 度’並增加開口㈣寬度以及導致記憶胞上較低的結構應 力口此~加内^電填充製程、钱刻製程以及石夕化物 積製程窗裕度。 另外，除了快閃記憶體之外，本發明還適用於所有 種類的記憶體元件，例如EPROM，EEPROM，DRAM及Next, referring to FIG. 10, after the silicide structure is formed, a borderless stop layer 58 such as silicon nitride is formed on the substrate. Then a layer of interlayer dielectric (ILD) true charge 100 is formed above the borderless stop layer%. Typical intermediary = filler 100 is deposited by a conventional process, and the material is, for example, silicon oxide. Because of the thinner spacers in the memory cell area, the process window margin of the inner dielectric layer filler 100 is increased. For example, if the gap filled in the process is increased from about 011 microns to 0.2 microns, the reliability will be greatly improved. I23673li82twf.d〇c / c greatly improves the reliability without the contact window structure 1G1 being formed at On the memory cell area, it is defined by the boundary t in the contact region including the two I contacts, the silver-engraved contact window layer, and a contact window metal fill. In addition, the memory cell area has a thin sidewall: a junction. For example, the high-voltage transistor wide openings in the peripheral circuit area are maintained by the t-thick sidewalls, so the cells on the edge 5f and the polar sides according to the present invention are relatively loud, and the middle boundary layer can indeed be formed larger than conventional. The thickness is good for the process window margin during the contact window etching process. 蚀刻 is particularly suitable for the manufacture of long-wall flash memory with small memory cell size and high density, and it is in the peripheral circuit area. There are accumulated high-voltage circuits. In summary, the advantages of the present invention include the following: The present invention provides a process and structure of a double gap wall. The memory cell and the peripheral circuit have different gap wall widths. Among them, the synthetic partition wall ^ at The gap wall of the transistor gate structure in the side circuit area is thin. The reliability of the memory cell and the miscellaneous energy of peripheral circuit components can be improved at the same time. The synthetic gap wall of the memory cell on the component gets low stress and improves data retention. (data retention). The gaps in the peripheral circuit area can be operated at a lower breakdown voltage. 2. The double gap process and structure eliminates the size of the memory cell and the difficulty of manufacturing. 14 I2367 ^ 82twfdoc / c 3. 、 A synthetic spacer wall is formed on the inside of the opening between the gates of the stack 4. This synthetic spacer wall reduces the width of the spacer wall made by the ordinary method and increases the width of the opening and the lower structure on the memory cell. Stress margins ~ plus internal filling process, money engraving process and lithography process window margin. In addition, in addition to flash memory, the present invention is also applicable to all kinds of memory elements, such as EPROM, EEPROM , DRAM and
SRAM°此外’第―半導體圖案和第二半導體圖案包括電 晶體閘極結構，電晶體以及線路。因此，應可以被理解和 領會在此描狀s歸驟及結構並*包含全部的記憶體元 件之製造流程。本發明可以被運用在有關不同的積體電路 製造技術上，以及在此有許多—般的製程步驟及描述對於 支持申請專利範圍來說是必要的，且可提供本發明之理 解。SRAM ° In addition, the first semiconductor pattern and the second semiconductor pattern include a transistor gate structure, a transistor, and a circuit. Therefore, it should be possible to understand and appreciate the manufacturing process of the steps and structure described here and * including all the memory components. The present invention can be applied to different integrated circuit manufacturing technologies, and there are many-general process steps and descriptions necessary to support the scope of patent applications, and can provide an understanding of the present invention.
雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不麟本發明之 神和乾圍内，當可作些許之更動與潤飾，因此本發明之: 護範圍當視後附之申請專利範圍所界定者為準。 Μ 【圖式簡單說明】 圖1繪示為在半導體基底上的記憶胞區及週 區上形成一介電層之示意圖。 私 圖2^示為在介電層上形成薄的中止層之示意圖。 圖3繪示為在中止層上形成間隙壁層之示意圖。 圖4繪示為在週邊電路區上形成圖案化光阻層，且 15 I2367Hd〇c/c 以此光阻層去除裸露之間隙壁層之示意圖。 圖5繪示為在記憶胞區上形成圖案化光阻層，以及 在週邊電路區上形成間隙壁之示意圖。 圖6繪示為形成第一線結構及第二線結構之示意圖。 圖7繪示為在圖6所述之架構上形成覆蓋層，以及 在週邊電路區上形成圖案化光阻層之示意圖。 圖8繪示為蝕刻圖7所述的架構之示意圖。 圖9繪示為形成矽化物結構之示意圖。 圖10繪示為内介電層填充及在矽化物結構上所形成 的接觸窗結構之不意圖。 【主要元件符號說明】 I :半導體基底 3 ·記憶胞區 5 :週邊電路區 7、10 :開口 9 :堆疊閘極 9 A :多晶石夕電晶體閘極 9B :多晶矽浮置閘極 9C :内多晶石夕介電層 9D :穿隧介電層 II :電晶體閘極 11A :閘極介電層 13 :介電區域 15 :摻雜區 16 123 673l|682twf.doc/c 19 :介電層 21 :中止層 23 :間隙壁層 25、53、54 :圖案化光阻層 27 :間隙壁 28 :摻質植入區 29 :第一線結構 31 :第二線結構 33 :覆蓋層 · 34 :合成間隙壁 35 :矽化物結構 55 :圖案化覆蓋層 56 :相鄰部分 58 :無邊界中止層 100 :内介電填充物 101 :接觸窗Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in this art can make some changes and retouching within the spirit and scope of the present invention. Invention: The scope of protection shall be determined by the scope of the attached patent application. Μ [Brief Description of the Drawings] FIG. 1 shows a schematic diagram of forming a dielectric layer on a memory cell region and a peripheral region on a semiconductor substrate. Figure 2 ^ shows a schematic diagram of forming a thin stop layer on the dielectric layer. FIG. 3 is a schematic diagram of forming a spacer layer on the stop layer. FIG. 4 is a schematic diagram of forming a patterned photoresist layer on a peripheral circuit area, and removing the exposed spacer layer by using this photoresist layer as 15 I2367Hdoc / c. FIG. 5 is a schematic diagram of forming a patterned photoresist layer on a memory cell region and forming a spacer wall on a peripheral circuit region. FIG. 6 is a schematic diagram of forming a first line structure and a second line structure. FIG. 7 is a schematic diagram of forming a cover layer on the structure described in FIG. 6 and forming a patterned photoresist layer on a peripheral circuit area. FIG. 8 is a schematic diagram of etching the structure described in FIG. 7. FIG. 9 is a schematic diagram showing the formation of a silicide structure. FIG. 10 is a schematic diagram showing a contact window structure formed by filling the inner dielectric layer and forming a silicide structure. [Description of main component symbols] I: semiconductor substrate 3 · memory cell area 5: peripheral circuit area 7, 10: opening 9: stacked gate 9 A: polycrystalline silicon transistor gate 9B: polycrystalline silicon floating gate 9C: Inner polycrystalline silicon dielectric layer 9D: tunneling dielectric layer II: transistor gate 11A: gate dielectric layer 13: dielectric region 15: doped region 16 123 673l | 682twf.doc / c 19: dielectric Electrical layer 21: Stop layer 23: Spacer wall layers 25, 53, 54: Patterned photoresist layer 27: Spacer wall 28: Doped implanted area 29: First line structure 31: Second line structure 33: Cover layer 34: Synthetic spacer 35: Silicide structure 55: Patterned cover layer 56: Adjacent portion 58: Borderless stop layer 100: Internal dielectric filler 101: Contact window
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