1236583 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係有關一種稱爲 SoC(System on Chip，系統卓 晶片）之例如包含加工程序（Process or)之較大規模的半導 體積體電路的低電力化。 【先前技術】 半導體積體電路（以下簡稱爲LSI)之低電力化由於使 用其之產品的低電力化甚爲重要。今後更進一步微細化， 提升LSI的積體度時，預測增加每一單位面積的發熱量。 因此，從電路的信賴性之觀點來看推測更需提高LSI的低 電力化。 CMOS型LSI的消耗電力係分類成動態成分和洩漏成 分。在現在的加工技術中，伴隨微細化之洩漏少，泰半爲 動態電力。但是’今後隨著微細加工技術的進步，預測洩 漏電力將急遽增加。 實現低電力的手法係藉由因應系統的時空間之處理負 載的變動控制處理性能，實現低電力化之所謂的「系統低 電力化」之手法甚爲有效。該方法的基本發想是在低負載 的情況下’部分地以低處理能力、低消耗電力的模式使系 統動作，抑制不需要的電力消耗。 系統低電力的主要方法（Approach)係如下所示分爲兩 種。 (1 )在低負載時遷移至低速（低電力）。例如： -5- (2) 12365831236583 (1) 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a relatively large-scale semiconductor integrated circuit called a SoC (System on Chip), which includes, for example, a process or process. Low power. [Previous Technology] The low power of semiconductor integrated circuits (hereinafter referred to as LSI) is very important due to the low power of products using them. In the future, further refinement will be made to increase the integration degree of LSI, and it is predicted that the heat generation amount per unit area will increase. Therefore, from the viewpoint of the reliability of the circuit, it is estimated that it is necessary to further reduce the power consumption of the LSI. The power consumption of CMOS-type LSIs is classified into dynamic components and leakage components. In the current processing technology, there is less leakage due to miniaturization, and Thai half is dynamic power. However, in the future, as microfabrication technology advances, leakage power is expected to increase sharply. The method of achieving low power is to control the processing performance in response to changes in the processing load of the system's time and space, and the method of achieving low power is called "system low power", which is very effective. The basic idea of this method is to partially operate the system in a mode of low processing power and low power consumption under a low load condition to suppress unnecessary power consumption. The main method of system low power (Approach) is divided into two types as shown below. (1) Migrate to low speed (low power) at low load. For example: -5- (2) 1236583
CrusoeTM處理程序。 (2 )在無負載（閒置）時遷移至停止模式。例如： ACPI(Advanced Configuration and Power Interface)。 爲了實現這種系統低電力化，必須監視系統負載，選 擇動作模式並進行指示動作之處理的電力控制（以下簡稱 爲 PM)。 隨著LSI的積體度提升，漸漸在單一的LSI內可應用 系統低電力化。換言之，以往一般如個人電腦，以其構成 零件之一即CPU晶片控制由較多零件構成的系統之系統 低電力化。但是，最近，控制側、及被控制側皆可積體在 單一的L S I內。 此外，與系統低電力化有關的技術如下所述。 在日本特開平7 -3 2 5 7 8 8號公報中，藉由導通/截斷控 制記載有由熱效率不同的RISC型處理程序構成的主CPU 與CISC型處理程序構成的副CPU，謀求低電力之技術。 在曰本特開平2002-4 1 1 60號公報中，記載有藉由因 應負載變更CPU的動作模式，最適化消耗電力之技術。 再者’於 ’’Energy-Aware Runtime Scheduling for Embedded Multiprocessor SOCs” IEEE Design &Test of Computers，200 1中，記載有在可並列化處理（Task)之多工 處理程序中，藉由在各處理程序（電源電壓、時脈信號的 頻率）設定最適合的動作模式，最適化消耗電力之技術。 又，”兔、龜處理程序之切換的低消費能源化之提 案 ： "TECHNICAL REPORT OF IEIC E. V L D 2 0 0 2 - (3) 1236583 1 6 1 JCD2002-226 (2003-03)，p.37-42 中，準備處理性能 不同的兩個處理程序，因應要求性能切換兩個處理程序之 手法。 然而，以往的系統低電力化手法，一般係藉由以一個 CPU動作的軟體之處理，進行PM處理。該理由係由於 PM處理需要複雜的判斷處理，故以軟體實現時較容易且 實在。又，爲了掌握CPU的處理負載，自然是活用相同 的 CPU 〇 CPU由於電路規模大，故其自身消耗電力大。又，由 於需要局速動作，故拽漏電力有變大的傾向。今後當微細 加工更進步時，推測這樣的傾向將更爲顯著。 另外，因爲應用的要求，更要求提高C P U的峰値性 能。爲提高CPU的峰値性能，例如所謂搭載快取記憶 體，多使用追加硬體資源之手法。但是，這亦是使洩漏電 力增大的主因，將導致問題更加惡化。 如此，以往由於藉由處理能力高且消耗電力效率低的 CPU進行PM，故難以降低系統動作時的洩漏電力。 又，在具備複數個CPU的系統中，於切換CPU時， 正確檢測出負載的狀態甚爲重要。但是，以往無法充分監 視負載的狀況。再者，亦不充分考慮與半導體晶片的溫度 變化對應的洩漏電流。因此，因應負載的狀態或溫度變 化，期望可充分提升系統的消耗電力效率。 本發明之目的在於提供一種因應負載的狀態或溫度變 化，可降低系統動作時的洩漏電力之半導體裝置。 1236583 (4) 【發明內容】 本發明之半導體裝置的第1樣態係具備有：半導體晶 片；安裝於上述半導體晶片，進行處理的第1 CPU ;及安 裝於上述半導體晶片，峰値性能低於上述第1 CPU且電力 效率較高的第2CPU，上述第2CPU係監視負載，在上述 負載大時，藉由上述第1 CPU進行處理，當上述負載小 時’取代上述第1CPU進行上述處理。 本發明之半導體裝置的第2樣態係具備有：半導體晶 片；安裝於上述半導體晶片，並進行處理的第1CPU ;安 裝於上述半導體晶片，峰値性能低於上述第i CPU且電力 效率較高的第2CPU ;及檢測出上述半導體晶片的溫度之 檢測部’上述第2CPU係因應由上述檢測部檢測出的溫度 使負載的判定基準變化，依據該判定基準，當上述負載大 時，藉由上述第1 C P U進行處理，當上述負載小時，取代 上述第1CPU進行上述處理。 【實施方式】 以下，參照圖面說明本發明之實施形態。 [第1實施形態] 第1圖係有關本發明之第1實施形態，利用非對稱的 多工CPU之SoC的一例。 在第1圖中’在半導體晶片內設置有主CPU12、 -8- (5) 1236583 副C P U 1 3、輸入輸出控制部（I / 〇 ) 1 4、計時器1 5、中斷控 制器（interrupt controller ) 1 6、及未圖示的記憶體等。 此等主CPU12、副CPU13、輸入輸出控制部（1/0)14、計 時器1 5、中斷控制器1 6係藉由系統匯流排1 7連接。主 CPU12係具有以休眠模式（sleep mode)、執行模式（run m 〇 d e )、及峰値性能動作的快速模式（s p r i n t m 〇 d e )， 副C P U 1 3及輸入輸出控制部1 4係具有休眠模式、執行模 式。執行模式與快速模式相比爲低速動作。計時器1 5及 中斷控制器1 6係具有執行模式。 畐IJ CPU13係構成 PM單元，且在低負載時，副 CPU13係可實行主CPU12的應用處理。副CPU13與主 C P U 1 2相比設爲小型的構成。亦即，主C P U 1 2係例如具 有快取記憶體、多段的管線，更具有分歧預測功能。相對 於此，副CPU 1 3係例如不具有快取記憶體以及分歧預測 功能，管道的段數亦設計爲比 CPU12小。因此，副 CPU13之消耗電力效率與主CPU12相比設計爲較高。換 言之，主CPU 12係峰値性能高，消耗電力效率低，副 CPU 13之峰値性能與主CPU12相比較低，消耗電力效率 設計爲較高。 第2圖係主CPU12與副CPU13的性能與消耗電力的 關係與各動作模式對應之圖。 主CPU 1 2係例如在快速模式中，將時脈頻率設爲最 大頻率Fmax，施加主體電壓Vbb。又，在執行模式中， 將時脈頻率設爲最大頻率的1/2，不施加主體電壓Vbb。 (6) 1236583 再者，在快速模式中，停止時脈頻率，停止時脈頻率，亦 不施加主體電壓Vbb。 又’主CPU12的消耗電力係在快速模式中，洩漏電 力例如l〇〇mW，動態電力爲ioOmW，總電力爲2 00mW， 在執行模式中，拽漏電力例如 20mW，動態電力爲 5 0 m W，總電力爲7 0 m W，在休眠模式中，洩漏電力例如 1 OmW，動態電力爲OmW，總電力爲1 OmW。 畐！J CPU 1 3例如在執行模式中，將時脈頻率設爲最大 頻率的1 /4，在休眠模式中，停止時脈頻率。副CPU 1 3係 不施加主體電壓Vbb。 又，畐U CPU13之消耗電力係在執行模式中，洩漏電 力例如4 m W，動態電力爲1 〇 m W，總電力爲1 4 m W，在休 眠模式中，洩漏電力例如1 m W，動態電力爲〇 m W，總電 力爲lmW。 第3A圖至第3D圖係藉由副CPU實現PM之例。在 第3 A圖至第3 D圖中，資源係包含上述快取記憶體、分 歧預測、命令記憶體等。 第3 A圖係顯示基本構成，如第1圖中所說明，顯示 改變系統的資源之構成。亦即，與副CPU 1 3連接的資源 2 1與和主CPU 1 2連接的資源22相比，規模較小且爲低洩 漏的構成。 第3B圖係顯示在主CPU12與畐!1 CPU13使用兼容的 命令裝置之情況。此時，藉由最適化命令記憶體等資源 23，主CPU12與副CPU13可共享資源23。藉由設爲這種 (7) 1236583 構成，可減輕主 CPU12與副 CPU13之額外負擔 (Overhead)。 第3C圖係使用具有可實行主CPU所使用的命令裝置 之仿真（emulation)功能的副 CPU13之情況。藉由設爲這 種構成，副C P U 1 3可共享主C P U1 2所使用的程式，與第 3 B圖的構成相同，可共享資源2 3。 第3D圖係第3B圖的變形者，顯示設置有複數個主 C P U 1 2之情況。如此，藉由設置複數個主C P U 1 2，可提升 峰値性能。 第4圖係顯示第1圖、第3A圖至第3D圖所示的第1 實施形態的基本構成之動作例。如上所述，主CPU12係 具有休眠模式與快速模式，副 CPU 1 3係監視負載的狀 態，因應負載的大小，切換控制主CPU與副CPU的動作 模式。 在第4圖中，例如藉由主CPU(M-CPU)12開始處理多 媒體（Multimedia)處理等的應用（APP) (S1)。首先，即使 負載在最重最差的條件下亦可進行處理，主CPU 1 2藉由 快速模式進行處理（S2)。然後，例如中斷主CPU1 2的應用 處理（S3)。於是，藉由副CPU13判斷應用處理是否已結束 (S 4 )。結果，當應用處理結束時，結束主c P U 1 2的動作。 另外，當未結束處理時，藉由副C P U ( S - C P U) 1 3，開 始電力控制處理（PM)(S5)。亦即，藉由副CPU13監視負 載（S6)。在該狀態下，當負載大時與上述相同，藉由主 CPU12再開始應用處理（S8)，然後，藉由主CPU12以快 1236583 (8) 速模式進行應用處理（S9)，之後中斷處理（S10)。 又，當負載判斷爲中程度時，藉由主C P U 1 2再開始 應用處理（SI 1)，然後，藉由主CPU12以執行模式進行應 用處理（S 12)，之後中斷處理（S 13)。 再者，當負載判斷爲小時，藉由副C P U 1 3再開始應 用處理（S14)，然後，藉由主CPU13以執行模式進行應用 處理（S15)，之後中斷處理（S16)。 又，當判斷負載爲極小時，畐ij CPU 1 3設爲固定期間 休眠模式（休止）（S 1 7 )。 於上述各處理的中斷以及休眠模式之後，藉由副 CPU13判斷是否再度結束應用處理（S4)，因應該結果反覆 上述動作。 在上述負載監視時例如考慮兩個方法。第一方法係以 應用處理的實行期間作爲負載的指標之方法，第二方法係 以應用處理的待機時間作爲負載的指標之方法。 在第一方法中，應用程式的構成係在應用程式的主要 處理之例如最前面的一處設定呼叫P Μ啓動函數（用來啓 動ΡΜ處理的函數）之命令。在第4圖所示的應用處理開 始時（S 1 )，啓動第1圖所示的計時器1 5。在應用處理中呼 叫 ΡΜ啓動函數時，在第 4圖所示的步驟 S3、S10、 S13、S16中斷應用處理，移至副CPU13的ΡΜ處理。亦 即，在步驟S6的負載監視動作中，副CPU13係讀取計時 器1 5的値，以上次的ΡΜ處理計算所讀取的値之差。在 步驟S6計算出的計時器之時間差相當於相同的處理步驟 -12- (9) 1236583 所需的應用處理之實行時間。因而，當該値大時，應用處 理的負載變大。 另外，在第二方法中’應用程式的構成係從應用程式 與PM處理兩方設定可存取的全體變數，在等待第1圖所 不來自1/014之資料輸入時’以增大全體變數之方式進行 程式設計（Programming )。在第4圖所示的應用處理開 始時（S 1) ’以在每一固定時間間隔中斷的方式，設定計時 器15與中斷控制器16。在應用處理中產生中斷時，如第 4圖所示的步驟S3、S10、S13、S16般，中斷應用處理， 並移至副CPU13之PM處理。亦即，在步驟S6的負載監 視動作中，副C P U 1 3讀取全體變數。該全體變數係在特 定的期間內計測應用處理成爲資料的輸入等待所浪費的時 間。因此’當所讀取的全數變數之値大時，由於應用程式 之待機時間變長’故相對的負載變小。 根據上述的第1實施形態，在半導體晶片1 1內與主 C P U 1 2相比，組裝峰値性能低且電力效率高的副C P U 1 3， 藉由該副CPU 1 3監視負載的狀態，在低負載時取代主 CPU12並藉由副CPU13進行應用處理。因此，除了需要 高性能的功能之外’藉由消耗電力高的副C P U 1 3進行處 理，故可大幅降低系統動作時的消耗電力。 第5圖係顯示藉由一個CPU進行PM處理之以往半導 體裝置之流程圖。第5圖所示的以往半導體裝置的情況， 係因應負載的大、小、極小，將一個CPU設定爲快速模 式（S 8 - S 1 〇)，執行模式（s 2 1 - 2 3 )、休眠模式（S 1 7)。 1236583 (10) 第6圖係顯示以往與第1實施形態之Cpu的動作 例，橫軸係顯示時間軸，模式顯示動作模式時間性遷移之 狀況。第6A圖所示之以往的情況，係將一個Cpu因應負 載的狀態設定爲快速模式（Sp)、執行模式（R)、休眠模式 (S 1)。相對於此，第6 B圖所示的第1實施形態之情況， 可知主CPU與副CPU之兩個CPU因應負載的狀態切換爲 快速模式（Sp)、執行模式（R)、休眠模式（S1)。 第6A圖所示之以往的控制動作係結合與在第7圖的 主CPU 1 2所示的曲線之快速模式、執行模式、休眠模式 對應的點之折線狀的控制。相對於此，第6圖所示之第1 實施形態的狀況，係成爲結合主C P U 1 2的快速模式、執 行模式、休眠模式對應的點之折線狀的控制。因此，以平 均的負載小、低的相對性能，在可處理的期間較長的應用 中，可抑制消耗電力。 第8圖係表示以往與第1實施形態的平均消耗電力。 如此，在各忙碌的比率中，可知本實施形態的平均消耗電 力比以往低。因此，根據第1實施形態，平均消耗電力與 以往相比可減低至1/3至2/3。 此外，在第1實施形態時，藉由電腦的結構程序改變 主CPU12與副CPU13的性能。但是，替換該手法，可改 變半導體製造上的資料館（Library)。例如，構成副CPU1 3 的加法器或閂鎖電路（L a t c h c i r c u i t)與構成主C P U 1 2的加 法器或閂鎖電路相比，在低速、低消耗電力動作可應用調 準（tuning)等的手法。亦即，以高速資料館構成主 -14- (11) 1236583 CPU12，與主CPU12相比可以低速且低洩漏資料館構成副 CPU13。 (第2實施形態） 第9圖係顯示本發明的第2實施形態。在第9圖中， 與第1圖相同部份附加相同符號，僅說明不同的部分。 如上所述，半導體元件的洩漏電流係隨著溫度上昇而 增加。又，將溫度設爲固定時，當閘極長爲愈微細的半導 體元件則洩漏電流愈大。因此，在管理半導體裝置的消耗 電力時，考慮半導體晶片的溫度更可最適化。因此，第2 實施形態係在半導體晶片1 1內配置溫度檢測部3 1，因應 該溫度檢測部3 1的輸出信號管理半導體裝置的消耗電 力。 在消耗電力的管理中，物理性的開爾文（Kelvin)溫度 較不重要，洩漏電流對動作電流的比（以下稱爲洩漏比）較 爲重要。因此，溫度檢測部31不僅測定開爾文（Kelvin)溫 度，藉由測定洩漏比相對地檢測出溫度。 第1 〇圖係顯示溫度檢測部3 1之一例。該溫度檢測部 3 1係具有：洩漏電流源3 2、電晶體的直流電流或動作電 流源3 3、及比較器3 4。比較器3 4係比較來自洩漏電流源 3 2的洩漏電流、電晶體的直流電源或來自動作電流源3 3 的電流，測定洩漏比。該所測定的洩漏比之溫度係供給至 副CPU ] 3。副CPU ] 3係因應該已測定的溫度適應切換動 作模式之算法（algorithm)。 (12) 1236583 第1 1圖係顯示溫度檢測部31的其他例。該溫度 部3 1係例如由串聯的邏輯電路3 $與洩漏電流源3 6 成’測定因應邏輯電路3 5的動作之洩漏比。該已測 洩漏比係供給至副C P U 1 3。畐[J c P u 1 3係因應該已測 洩漏比適應切換動作模式之算法。 第1 2圖係顯示溫度與洩漏電流的關係。溫度檢 3 1係在溫度例如大致爲5 0 °C時，以洩漏電流與D C (ON電流）或AC電流相等的方式設計。 第1 3 A圖、第1 3 B圖係顯示洩漏電流源3 2之一 第1 3 A圖、第1 3 D圖係顯示直流電流源的一例。第 圖係由設爲經常OFF狀態的P通道MOS電晶體32 A 成。第13B圖係由P通道MOS電晶體32B所構成。 Vdd供給至該電晶體32B的閘極，供給控制信號至源 該控制信號係在測定時設爲電源電壓Vdd，在休眠時 接地電位。第1 3 C圖係接地閘極，藉由設爲經常〇 N 之P通道Μ 0 S電晶體3 3 A所構成。第1 3 D圖係藉由 道MOS電晶體33B所構成。對該電晶體33B的源極 控制信號，閘極係接地。該控制信號在測定時設爲電 壓Vdd，在休眠時設爲接地電位。構成洩漏電流源的 體 32 A、32B之通道寬度與構成 DC電流源之電 3 3 A、3 3 B的通道寬度係根據元件的特性決定，現在 最前端的閘極長〇 · 〇 9 - 〇 · 1 8 // m由於一般D C電流比洩 流大得多，故前者設爲較大。又’爲第1 3B圖、第 圖所示的電路構成時’由於休眠日寸笔晶體設爲〇 F F ’ 檢測 所構 定的 定的 測部 電流 例， 1 3 A 所構 電源 極。 設爲 狀態 P通 供給 源電 電晶 晶體 設爲 漏電 1 3D 故可 1236583 (13) 切斷不需要的電流。 第14圖係顯示AC (交流）電流源33之一例。該AC電 流源3 3係例如藉由串聯之反相電路3 3 C、電阻3 3 D、電 容器3 3 E所構成。在反相電路3 3 C的輸入端例如供給有 系統時脈信號C L K。反相電路3 3 C的輸出信號係介以由 電阻3 3 D及電容器3 3 E構成的濾波器電路供給至比較器 3 4。比較器3 4係比較洩漏電流源3 2的輸出信號與濾器波 電路的輸出信號。此等的濾波器電路及比較器34係構成 將溫度資訊當作數位信號輸出的1位元之AD變換電路。 第1 5 A圖、第1 5 B圖係顯示洩漏電流源3 2、D C電流 源3 3或是動作電流源之其他例。第1 5 A圖係串並聯複數 個P通道MOS電晶體，藉由控制信號導通控制此等電晶 體，控制輸出電流。第1 5 B圖係藉由控制信號導通控制並 聯的複數個P通道MOS電晶體，可控制電流能力。 藉由設爲這種構成，可改變電流源的能力。因此，可 改變溫度（洩漏比）的變化點之設定。又，在使用元件特性 不同的製造技術時亦可使用相同的電路。 第1 6圖係顯示溫度檢測部3 1的具體電路之一例，在 與第1 〇圖相同部份附加相同符號。該電路係全部藉由N 通道MOS電晶體構成。DC電流源33係藉由所串聯的複 數個電晶體3 3 C、3 3 D、3 3 E以及與此等的電晶體並聯的 電晶體3 3 F所構成。電晶體3 3 C、3 3 D、3 3 E之閘極係供 給經常導通電晶體的高位準信號（Vdd)，電晶體33C、33F 之汲極供給有允許（enable)信號EN。該允許信號EN係在 (14) 1236583 溫度測定時設爲高爲準（Vdd)。又，在增加直流電流時， 將電晶體3 3 F設爲導通。又，洩漏電流源3 2係藉由電晶 體3 2 C所構成，比較器3 4係藉由已串聯的反相電路 IV1、IV2 構成。 在上述構成中，當溫度高時，在洩漏電流源3 2流動 的電流會變多，使比較器3 4的輸入端成爲低位準。因 此，比較器3 4的輸出信號成爲低位準。另外，當溫度較 低時，由於洩漏電流減少，故比較器3 4的輸入端充電成 高位準。因此，比較器3 4的輸出信號成爲高位準。 第1 7圖係顯示使用第1 1圖所示的邏輯電路與洩漏電 流源之溫度檢測部3 1的例。在該溫度檢測部3 1中，邏輯 電路35係藉由可變脈衝產生器41 A、P通道MOS電晶體 4 1 B、比較器4 1 C、驅動器4 1 D所構成。洩漏電流源3 6 係由通道寬度大的N通道MOS電晶體41E所構成。可變 脈衝產生器41A係與P通道MOS電晶體41B之閘極連 接。在P通道MOS電晶體41B與N通道MOS電晶體41E 之連接閘極連接有比較器4 1 C的一方輸入端。該比較器 41C的另一方輸入端係與比較器41C的輸出端連接。該輸 出端係連接有驅動器4 1 D。該驅動器4 1 D的輸出端係連接 有計數器42。該計數器42係計數從驅動器41D輸出的脈 衝信號。 第1 8圖係顯示上述可變脈衝產生器4 1 A的一例。該 可變脈衝產生器4 1 A係由參照寄存器5 1、計數器5 2、比 較器5 3所構成。參照寄存器5 1係例如保持顯示來自副 -18· (15) 1236583 CPU13所供給的脈衝週期（PULSE DUTY)之參照値。計數 器52係因應允許信號EN計數時脈信號CLK °該計數在 全部成爲” 1 ”時，重設爲” 0 ”。比較器5 3係在計數器5 2的 計數値大於參照寄存器5 1所保持的參照値時’輸出資料 ，，1”，較小時，輸出資料，，0 ”。亦即，該可變脈衝產生器 4 1 A係輸出頻率低的脈衝信號。 第19A圖、第19B圖係顯示第17圖、第18圖的動 作。第1 9 A圖係溫度高之情況，亦即表示洩漏電流多之 情況，第1 9B圖係溫度低之情況，亦即表示洩漏電流少之 情況。 在第1 7圖中，從可變脈衝產生器4 1 A輸出因應參照 値的週期之脈衝信號NA。P通道MOS電晶體41B係在該 脈衝信號ΝΑ的低位準期間充電連接節點ΝΒ。當溫度高 時，使洩漏電流源3 6流動的電流多。因此，連接節點ΝΒ 之充電電荷係如第1 9 Α圖所示，快速放電。因而，從輸 出節點NC輸出高位準之週期短的脈衝信號。 另外，當溫度低時，在洩漏電流源3 6流動的電流變 少。因此，保持連接節點NB的電荷，連接節點NB係維 持高位準。因而，從輸出節點NC輸出高位準之週期長的 脈衝信號。 例如藉由計數器42計數來自上述輸出節點NC所輸 出的脈衝信號，可檢測出溫度。該計數器42的計數値係 供給至上述副C P U 1 3。 第2 〇圖係顯示第2實施形態的動作者，顯示使用上 -19- 1236583 (16) 述溫度檢測部3 1的輸出信號之動作例。在第2 0圖中，與 第4圖相同的部分附加相同符號。 在第20圖中，副CPU13係在中斷主CPU12的處理 時，因應溫度檢測部3 1的輸出信號監視半導體晶片的溫 度（S 3 1)。再者，副C P U 1 3係監視負載的大小（S 3 2 )。然 後，判斷溫度是否高於基準値，負載是否小於基準値 (S33)。亦即，在高溫中，啓動洩漏電流大的主CPU12之 補償（Penalty)大。因此，當負載小時，藉由將主CPU12 的啓動設爲最小之極細的P Μ處理，更期待可抑制這種複 合條件下的消耗電力。因而，當溫度高負載小時，電力控 制（ΡΜ)的啓動間隔縮短，增加負載的判斷基準値（S3 5)。 又，當未滿上述步驟S 3 3的條件時，判斷溫度是否比 基準値低，負載是否大於基準値（S34)。亦即，在低溫 下，啓動洩漏電流大的主CPU12之週期相對變小，當負 載大時，啓動副 CPU13的電力控制（ΡΜ)之額外負擔相對 變大。因此，在這種複合條件下，藉由抑制副CPU 1 3的 啓動之PM處理更可抑制消耗電力。因而，增加PM的啓 動間隔，減少負載的判斷基準値（S 3 6)。 在未滿上述步驟S34的條件之情況下，不變更PM的 啓動間隔、及負載的判斷基準値。如此，在控制PM的啓 動間隔、及負載的判斷基準値之後，與第1實施形態相同 判斷負載的大小，因應所判斷的負載控制主CPU 1 3及副 C P U 1 3的動作模式。 根據上述第2實施形態，在半導體晶片1 1內設計溫 -20- (17) 1236583 度檢測部3 1，因應藉由該溫度檢測部3 1所檢測的溫度’ 控制PM的啓動間隔、及負載的判斷基準値’在胃彳犬態 下，因應負載的大小，控制主CPU12及副CPU13的動作 模式。因而，藉由因應半導體晶片1 1內的溫度’切換第 1、第2 C P U 1 2、1 3的動作，可將洩漏電流抑制在最小 限，且可抑制處理能力的降低。 此外，在上述第1、第2實施形態中，說明主cpU、 副CPU具有快速模式、執行模式、休眠模式之2至3的 動作模式之情況。但是，並不限定於此，亦可具有三個以 上的動作模式。亦即，不限於離散的複數個動作模式’在 具有連續的動作模式之CPU亦可應用第1、第2實施形 態。 另外，本發明係不限定於上述各實施形態者’在不改 變發明的要旨之範圍內當然可進行種種的變形。 [產業上之可利用性] 如以上所詳述，本發明係因應負載的狀態或溫度變 化，由於提供一種可降低系統在動作時的洩漏電力之半導 體裝置，故在包含稱爲SoC之加工程序（Processor)的比較 大規模的半導體積體電路領域中可有效利用。 【圖式簡要說明】 第1圖係有關第1實施形態之半導體裝置的構成圖。 第2圖係主CPU與副CPU的性能與消耗電力的關係 (18) 1236583 與各動作模式對應之圖。 第3A圖至第3D圖係第1實施形態的主CPU與副 CPU之變形例。 第4圖係第1實施形態的動作之一例的流程圖。 第5圖係以往的半導體裝置之動作流程圖。 第6A圖至第6B圖係槪略顯示以往與第1實施形態 的動作圖。 第7圖係槪略顯示以往與第1實施形態的相對性能與 消耗電力之關係圖。 第8圖係表示以往與第1實施形態之忙碌（Busy)與平 均消費電力的關係。 第9圖係有關本發明的第2實施形態之半導體裝置的 構成圖。 第1 〇圖係溫度檢測部的一例之構成圖。 第11圖係溫度檢測部的另一例之構成圖。 第1 2圖係溫度與洩漏電流的關係圖。 第1 3 A圖至第1 3 D圖係顯示洩漏電流源及D C或動作 電流源的一例之電路圖。 第1 4圖係AC電流源的一例之電路圖。 第1 5 A圖及第1 5 B圖係顯示洩漏電流源及D C或動作 電流源的其他例之電路圖。 第1 6圖係’k度檢測部的具體一例之電路圖。 第1 7圖係使用邏輯電路與洩漏電流源的溫度檢測部 之具體例的電路圖。 -22- 1236583 (19) 第1 8圖係顯示可變脈衝產生器之一例的構成圖。 第19A圖及第19B圖係顯示第17圖及第18圖的動 作之波形圖。 第2 0圖係顯示第2實施形態的動作之一例的流程 圖。 主要元件對照表 11 半導體晶片 12 主CPU 13 畐！] CPU 14 輸入輸出控制部 15 計時器 16 中斷控制器 17 系統匯流排 3 1 溫度檢測部 32 浅漏電流源 32A、32B、33 A、33B、41B P通道MOS電晶體 33 D C電流源 33C 反相電路 33D 電阻 33E 電容器 33F 電晶體 34 、 41C > 53 比較器 35 邏輯電路CrusoeTM handler. (2) Migrate to stop mode when there is no load (idle). For example: ACPI (Advanced Configuration and Power Interface). In order to reduce the power consumption of such a system, it is necessary to monitor the system load, select an operation mode, and perform power control (hereinafter referred to as PM) for processing to instruct the operation. As the integration of LSIs increases, the system can be used with low power in a single LSI. In other words, a conventional system such as a personal computer, which uses one of its constituent parts, that is, a CPU chip, to control a system composed of a large number of parts, has reduced power consumption. However, recently, both the control side and the controlled side can be integrated in a single L S I. The technologies related to system power reduction are described below. In Japanese Patent Application Laid-Open No. 7 -3 2 5 7 8 8, the on / off control records a main CPU composed of a RISC-type processing program with a different thermal efficiency and a sub-CPU composed of a CISC-type processing program. technology. Japanese Patent Application Laid-Open No. 2002-4 1 1 60 describes a technique for optimizing power consumption by changing the operation mode of the CPU according to the load. Furthermore, in "Energy-Aware Runtime Scheduling for Embedded Multiprocessor SOCs" IEEE Design & Test of Computers, 2001, it is described in a multiplexing processing program that can be parallelized (Task), by each processing The program (power supply voltage, frequency of the clock signal) sets the most suitable operation mode and the technology that optimizes the power consumption. In addition, the proposal of "lower energy consumption for switching between rabbit and turtle processing programs": " TECHNICAL REPORT OF IEIC E VLD 2 0 0 2-(3) 1236583 1 6 1 In JCD2002-226 (2003-03), p.37-42, two processing programs with different performances are prepared, and the method of switching the two processing programs according to the required performance . However, in the past, the low-power method of the system generally performed PM processing by processing using software operated by one CPU. This reason is because PM processing requires complicated judgment processing, so it is easy and practical to implement it in software. In addition, in order to grasp the processing load of the CPU, it is natural to use the same CPU. The CPU consumes a large amount of power because of its large circuit scale. In addition, since local speed operation is required, the leakage power tends to increase. In the future, as microfabrication progresses further, it is speculated that this tendency will become more significant. In addition, because of the requirements of the application, it is further required to improve the peak-pull performance of C P U. In order to improve the peak performance of the CPU, for example, the so-called cache memory is used to add hardware resources. However, this is also the main cause of the increased leakage power, which will make the problem worse. As described above, conventionally, PM is performed by a CPU having a high processing power and a low power consumption efficiency. Therefore, it is difficult to reduce leakage power during system operation. Moreover, in a system having a plurality of CPUs, it is important to accurately detect the state of the load when the CPUs are switched. However, in the past, the condition of the load could not be fully monitored. Furthermore, the leakage current corresponding to the temperature change of the semiconductor wafer is not sufficiently considered. Therefore, it is expected that the power consumption efficiency of the system can be sufficiently improved in response to changes in load conditions or temperature. An object of the present invention is to provide a semiconductor device capable of reducing power leakage when a system is operated in response to a load state or temperature change. 1236583 (4) [Summary] The first aspect of the semiconductor device of the present invention includes: a semiconductor wafer; a first CPU mounted on the semiconductor wafer for processing; and a semiconductor chip mounted on the semiconductor wafer, the peak performance is lower than The first CPU and the second CPU with higher power efficiency, the second CPU monitors the load. When the load is large, the first CPU performs processing, and when the load is small, the first CPU performs the processing instead of the first CPU. The second aspect of the semiconductor device of the present invention includes: a semiconductor wafer; a first CPU mounted on the semiconductor wafer and processed; and mounted on the semiconductor wafer, the peak performance is lower than the i-th CPU and the power efficiency is high A second CPU; and a detection unit that detects the temperature of the semiconductor wafer. The second CPU changes the determination criterion of the load in accordance with the temperature detected by the detection unit. The first CPU performs processing. When the load is small, the first CPU performs the processing instead of the first CPU. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. [First Embodiment] Fig. 1 is an example of an SoC using an asymmetric multiplexed CPU according to the first embodiment of the present invention. In the first figure, 'the main CPU12, -8- (5) 1236583 sub-CPU 1 are installed in the semiconductor chip 1 3. input / output control unit (I / 〇) 1 4. timer 1 5. interrupt controller (interrupt controller ) 16 and memory (not shown). The main CPU 12, sub CPU 13, input / output control unit (1/0) 14, timer 15 and interrupt controller 16 are connected through a system bus 17. The main CPU 12 has a sleep mode, an execution mode (run m ode), and a fast mode (sprint m ode) that operates in peak performance. The sub CPU 1 3 and the input / output control unit 14 have a sleep mode. , Execution mode. The execution mode is a low-speed operation compared to the fast mode. Timer 15 and interrupt controller 16 have execution modes.畐 IJ CPU13 series constitutes PM unit, and under low load, sub CPU13 series can implement application processing of main CPU12. The sub CPU 13 has a smaller configuration than the main CPU 1 U 1 2. That is, the main C P U 1 2 series has, for example, a cache memory and a multi-segment pipeline, and it also has a branch prediction function. On the other hand, the sub CPUs 1 and 3, for example, do not have a cache memory and a branch prediction function, and the number of pipeline sections is also designed to be smaller than that of the CPU 12. Therefore, the power consumption efficiency of the sub CPU 13 is designed to be higher than that of the main CPU 12. In other words, the main CPU 12 has high peak performance and low power consumption efficiency. The sub CPU 13 has lower peak performance than the main CPU 12 and is designed to have higher power consumption efficiency. Fig. 2 is a graph corresponding to the relationship between the performance and power consumption of the main CPU 12 and the sub CPU 13 and the respective operation modes. The main CPU 1 2 sets the clock frequency to the maximum frequency Fmax in the fast mode, for example, and applies the main body voltage Vbb. In the execution mode, the clock frequency is set to 1/2 of the maximum frequency, and the body voltage Vbb is not applied. (6) 1236583 In the fast mode, the clock frequency is stopped, the clock frequency is stopped, and the body voltage Vbb is not applied. The power consumption of the main CPU 12 is in the fast mode, and the leakage power is 100 mW, the dynamic power is 100 mW, and the total power is 200 mW. In the execution mode, the leakage power is 20 mW, and the dynamic power is 50 m W. , The total power is 70 m W. In the sleep mode, the leakage power is, for example, 1 OmW, the dynamic power is OmW, and the total power is 1 OmW. Huh! J CPU 1 3 For example, in the execution mode, the clock frequency is set to 1/4 of the maximum frequency. In the sleep mode, the clock frequency is stopped. Sub CPU 1 3 Series No body voltage Vbb is applied. In addition, the power consumption of 畐 U CPU13 is in the execution mode, and the leakage power is, for example, 4 m W, the dynamic power is 10 m W, and the total power is 14 m W. In the sleep mode, the leakage power is, for example, 1 m W, the dynamic The power is 0 mW, and the total power is lmW. 3A to 3D are examples in which PM is implemented by a sub CPU. In Figures 3A to 3D, the resources include the cache memory, disambiguation prediction, and command memory. Figure 3A shows the basic structure. As shown in Figure 1, it shows the structure of the resources that change the system. That is, the resource 21 connected to the sub CPU 1 3 is smaller in size and has a lower leakage than the resource 22 connected to the main CPU 1 2. Fig. 3B shows the case where the main CPU 12 and the CPU 1 use a compatible command device. At this time, by optimizing the resources 23 such as the command memory, the main CPU 12 and the sub CPU 13 can share the resources 23. By setting it as (7) 1236583, the overhead of the main CPU 12 and the sub CPU 13 can be reduced. Fig. 3C shows a case where a sub CPU 13 having an emulation function capable of executing a command device used by the main CPU is used. With this configuration, the sub C P U 1 3 can share the program used by the main C P U1 2, which is the same as the configuration in FIG. 3B and can share the resources 2 3. Fig. 3D is a deformer of Fig. 3B and shows a case where a plurality of main C P U 1 2 are provided. In this way, by setting a plurality of main C P U 1 2, peak peak performance can be improved. Fig. 4 shows an operation example of the basic configuration of the first embodiment shown in Figs. 1, 3A to 3D. As described above, the main CPU 12 has a sleep mode and a fast mode, and the sub CPUs 1 and 3 monitor the status of the load, and switches the operation modes of the main CPU and the sub CPU according to the size of the load. In FIG. 4, for example, the main CPU (M-CPU) 12 starts an application (APP) that processes multimedia processing (S1). First, even if the load is processed under the heaviest and worst conditions, the main CPU 12 performs processing in fast mode (S2). Then, for example, the application processing of the main CPU 12 is interrupted (S3). Then, it is judged by the sub CPU 13 whether the application processing has ended (S4). As a result, when the application process ends, the operation of the main c P U 1 2 ends. When the process is not completed, the power control process (PM) is started by the sub-C P U (S-C P U) 1 3 (S5). That is, the load is monitored by the sub CPU 13 (S6). In this state, when the load is large, it is the same as the above, and the application processing is restarted by the main CPU 12 (S8), and then the application processing is performed by the main CPU 12 in the fast 1236583 (8) speed mode (S9), and then the processing is interrupted ( S10). When the load is judged to be moderate, the application processing (SI 1) is resumed by the main CPU 12 and then the application processing is executed in the execution mode by the main CPU 12 (S 12), and then the processing is interrupted (S 13). When the load is judged to be small, the application processing is resumed by the sub CPU 13 (S14), and then the application processing is executed by the main CPU 13 in the execution mode (S15), and then the processing is interrupted (S16). When it is judged that the load is extremely small, 畐 ij CPU 1 3 is set to a fixed period sleep mode (suspended) (S 1 7). After the interruption of each of the processes described above and the sleep mode, the sub CPU 13 determines whether or not to end the application process again (S4), and repeats the above actions according to the results. In the above-mentioned load monitoring, for example, two methods are considered. The first method is a method using the execution period of the application process as an indicator of the load, and the second method is a method using the standby time of the application process as an indicator of the load. In the first method, the composition of the application program is to set a command for calling a PM activation function (a function for starting PM processing) in the main processing of the application program, for example, the first place. At the start of the application process (S1) shown in Fig. 4, the timer 15 shown in Fig. 1 is started. When the PM start function is called in the application process, the application process is interrupted at steps S3, S10, S13, and S16 shown in FIG. 4 and the process is shifted to the PM process of the sub CPU 13. That is, in the load monitoring operation in step S6, the sub CPU 13 reads the frame of the timer 15 and calculates the difference between the frames read by the previous PM processing. The time difference of the timer calculated in step S6 is equivalent to the execution time of the application processing required for the same processing step -12- (9) 1236583. Therefore, when the load is large, the load of application processing becomes large. In addition, in the second method, "the composition of the application is set from the application and the PM process to access all the variables, while waiting for data input from the 1/014 in Figure 1" to increase the overall Programming. At the start of the application process (S1) 'shown in Fig. 4, the timer 15 and the interrupt controller 16 are set so as to be interrupted at regular intervals. When an interrupt occurs in the application process, the application process is interrupted as in steps S3, S10, S13, and S16 shown in FIG. 4, and the process is moved to the PM process of the sub CPU 13. That is, in the load monitoring operation in step S6, the sub-C P U 1 3 reads the entire variables. This global variable is a waste of time in which measurement application processing becomes data input waiting in a specific period. Therefore, when the readout of all the variables is large, the relative load becomes smaller because the standby time of the application becomes longer. According to the first embodiment described above, compared with the main CPU 12 in the semiconductor wafer 11, the sub CPU 1 3 with low peak performance and high power efficiency is assembled, and the status of the load is monitored by the sub CPU 1 3. When the load is low, the main CPU 12 is replaced and the sub CPU 13 performs application processing. Therefore, in addition to the need for high-performance functions, the processing is performed by the secondary C P U 1 3 with high power consumption, so that the power consumption during system operation can be significantly reduced. Fig. 5 is a flowchart showing a conventional semiconductor device that performs PM processing by a CPU. In the case of the conventional semiconductor device shown in FIG. 5, a CPU is set to a fast mode (S 8-S 1 〇), an execution mode (s 2 1-2 3), and a sleep mode in response to a large, small, and extremely small load. Mode (S 1 7). 1236583 (10) Fig. 6 shows an example of the operation of the CPU in the past and the first embodiment. The horizontal axis shows the time axis, and the mode shows the state of time transition of the operation mode. In the conventional case shown in Fig. 6A, a CPU is set to a fast mode (Sp), an execution mode (R), and a sleep mode (S 1) in response to a load. In contrast, in the case of the first embodiment shown in FIG. 6B, it can be seen that the two CPUs of the main CPU and the sub CPU switch to the fast mode (Sp), the execution mode (R), and the sleep mode (S1) in accordance with the state of the load. ). The conventional control operation shown in FIG. 6A is a combination of points-like control that combines points corresponding to the fast mode, execution mode, and sleep mode of the curve shown in the main CPU 12 in FIG. 7. In contrast, the situation of the first embodiment shown in FIG. 6 is a polyline control that combines the points corresponding to the fast mode, the execution mode, and the sleep mode of the main CPU 1 2. Therefore, with a small average load and low relative performance, power consumption can be suppressed in applications where the processing period is long. Fig. 8 shows the average power consumption of the conventional and first embodiments. In this way, it can be seen that the average power consumption of this embodiment is lower than the conventional ones in each busy ratio. Therefore, according to the first embodiment, the average power consumption can be reduced to 1/3 to 2/3 compared with the conventional power consumption. In the first embodiment, the performance of the main CPU 12 and the sub CPU 13 is changed by a configuration program of a computer. However, replacing this method can change the library in semiconductor manufacturing. For example, compared with the adder or latch circuit constituting the main CPU 1 2, the adder or latch circuit constituting the sub CPU 1 3 can perform tuning and other operations at low speed and low power consumption. . In other words, the main -14- (11) 1236583 CPU12 is composed of a high-speed library, and the sub-CPU13 can be composed of a low-speed and low-leakage library compared to the main CPU12. (Second Embodiment) Fig. 9 shows a second embodiment of the present invention. In FIG. 9, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described. As described above, the leakage current of a semiconductor device increases as the temperature increases. When the temperature is fixed, the finer the semiconductor element is, the larger the leakage current will be. Therefore, when managing the power consumption of the semiconductor device, the temperature of the semiconductor wafer can be optimized in consideration of the temperature. Therefore, in the second embodiment, the temperature detection section 31 is arranged in the semiconductor wafer 11 and the power consumption of the semiconductor device is managed in accordance with the output signal of the temperature detection section 31. In the management of power consumption, the physical Kelvin temperature is less important, and the ratio of leakage current to operating current (hereinafter referred to as leakage ratio) is more important. Therefore, the temperature detecting section 31 not only measures the Kelvin temperature, but also relatively detects the temperature by measuring the leak ratio. Fig. 10 shows an example of the temperature detecting section 31. The temperature detecting section 31 includes a leakage current source 3 2, a direct current or operating current source 3 of a transistor 3, and a comparator 34. The comparator 34 compares the leakage current from the leakage current source 32, the DC power of the transistor, or the current from the operating current source 33, and measures the leakage ratio. The temperature of the measured leak ratio is supplied to the sub CPU] 3. The sub-CPU] 3 is an algorithm that adapts to the operating mode according to the measured temperature. (12) 1236583 Fig. 11 shows another example of the temperature detecting section 31. The temperature section 31 is, for example, a logic ratio of a serially connected logic circuit 3 $ and a leakage current source 36 to measure the leakage ratio in accordance with the operation of the logic circuit 35. This measured leak ratio is supplied to the secondary C P U 1 3. J [J c P u 1 3 is an algorithm that adapts to the switching operation mode based on the measured leakage ratio. Figure 12 shows the relationship between temperature and leakage current. The temperature check 3 1 is designed so that the leakage current is equal to DC (ON current) or AC current at a temperature of approximately 50 ° C, for example. Figures 1 A and 1 B show one of the leakage current sources 3 2 and Figures 1 A and 1 D show an example of a DC current source. The figure shows a 32-A P-channel MOS transistor set to the OFF state. FIG. 13B is composed of a P-channel MOS transistor 32B. Vdd is supplied to the gate of the transistor 32B, and a control signal is supplied to the source. This control signal is set to the power supply voltage Vdd during measurement, and is grounded during sleep. Fig. 1 C is a grounded gate, which is composed of a P channel M 0 S transistor 3 3 A which is set to be always ON. Figure 1 3D is composed of a MOS transistor 33B. The gate of the transistor 33B is grounded. This control signal is set to the voltage Vdd during measurement, and is set to the ground potential during sleep. The channel widths of the bodies 32 A and 32B constituting the leakage current source and the channel widths of the electricity 3 3 A and 3 3 B constituting the DC current source are determined according to the characteristics of the element. · 1 8 // m Because the general DC current is much larger than the leakage, the former is set to be larger. In the case of the circuit configuration shown in FIGS. 1B and 3B, since the dormant pen-type pen crystal is set to 0 F F ′, an example of a certain current measurement section is configured, and the power supply electrode is configured as 1 3 A. Set to state P-pass supply source transistor Crystal set to leakage 1 3D, so 1236583 (13) can cut off unnecessary current. FIG. 14 shows an example of an AC (alternating current) current source 33. The AC current source 3 3 is constituted by, for example, an inverter circuit 3 3 C, a resistor 3 3 D, and a capacitor 3 3 E connected in series. An input terminal of the inverter circuit 3 3 C is supplied with a system clock signal C L K, for example. The output signal of the inverter circuit 3 3 C is supplied to the comparator 34 through a filter circuit composed of a resistor 3 3 D and a capacitor 3 3 E. The comparator 3 4 compares the output signal of the leakage current source 32 with the output signal of the filter wave circuit. These filter circuits and comparators 34 constitute a 1-bit AD conversion circuit that outputs temperature information as a digital signal. Figures 15A and 15B show other examples of leakage current source 3 2, DC current source 33, or operating current source. Figure 15A is a series of parallel P-channel MOS transistors. These transistors are controlled by the control signal to control the output current. Figure 15B shows the control of a plurality of P-channel MOS transistors connected in parallel by the control signal conduction, which can control the current capacity. With this configuration, the capability of the current source can be changed. Therefore, the setting of the change point of the temperature (leak ratio) can be changed. The same circuit can also be used when manufacturing technologies with different element characteristics are used. Fig. 16 shows an example of a specific circuit of the temperature detecting section 31, and the same reference numerals are attached to the same portions as those in Fig. 10. The circuit is all composed of N-channel MOS transistors. The DC current source 33 is constituted by a plurality of transistors 3 3 C, 3 3 D, 3 3 E connected in series, and a transistor 3 3 F connected in parallel with these transistors. The gates of the transistors 3 3 C, 3 3 D, and 3 3 E are used to supply the high-level signal (Vdd) of the crystal which is always turned on, and the drains of the transistors 33C and 33F are provided with an enable signal EN. This enable signal EN is set to high (Vdd) during (14) 1236583 temperature measurement. When the DC current is increased, the transistor 3 3 F is turned on. The leakage current source 32 is constituted by an electric crystal 3 2 C, and the comparator 34 is constituted by inverter circuits IV1 and IV2 connected in series. In the above configuration, when the temperature is high, the current flowing in the leakage current source 32 will increase, and the input terminal of the comparator 34 will become a low level. Therefore, the output signal of the comparator 34 becomes a low level. In addition, when the temperature is low, the input of the comparator 34 is charged to a high level because the leakage current is reduced. Therefore, the output signal of the comparator 34 becomes a high level. Fig. 17 shows an example in which the temperature detection section 31 using the logic circuit and the leakage current source shown in Fig. 11 is used. In this temperature detecting section 31, the logic circuit 35 is constituted by a variable pulse generator 41 A, a P-channel MOS transistor 4 1 B, a comparator 4 1 C, and a driver 4 1 D. The leakage current source 36 is composed of an N-channel MOS transistor 41E having a large channel width. The variable pulse generator 41A is connected to the gate of the P-channel MOS transistor 41B. One input terminal of the comparator 4 1 C is connected to the connection gate of the P-channel MOS transistor 41B and the N-channel MOS transistor 41E. The other input terminal of the comparator 41C is connected to the output terminal of the comparator 41C. A driver 4 1 D is connected to this output. A counter 42 is connected to the output terminal of the driver 4 1 D. This counter 42 counts pulse signals output from the driver 41D. Fig. 18 shows an example of the above-mentioned variable pulse generator 4 1 A. The variable pulse generator 4 1 A is composed of a reference register 51, a counter 51, and a comparator 53. The reference register 51 holds, for example, a reference frame that displays the pulse period (PULSE DUTY) supplied from the sub-18 (15) 1236583 CPU13. The counter 52 counts the clock signal CLK in response to the enable signal EN. When the count becomes "1", it resets to "0". The comparator 5 3 outputs data when the count of the counter 5 2 is greater than the reference time held by the reference register 51, 1 ”, and outputs data when it is smaller, 0”. That is, the variable pulse generator 4 1 A outputs a pulse signal having a low frequency. Figures 19A and 19B show the operations of Figures 17 and 18. Figure 19A shows a case where the temperature is high, which means that the leakage current is large, and Figure 19B shows a case where the temperature is low, which means that the leakage current is small. In Fig. 17, a variable pulse generator 4 1 A outputs a pulse signal NA corresponding to the period of reference 値. The P-channel MOS transistor 41B charges the connection node NB during the low level of the pulse signal NA. When the temperature is high, a large amount of current flows through the leakage current source 36. Therefore, the charging charge of the connected node NB is quickly discharged as shown in Fig. 19A. Therefore, a high-level pulse signal with a short period is output from the output node NC. When the temperature is low, the current flowing through the leakage current source 36 decreases. Therefore, the charge of the connection node NB is maintained, and the connection node NB is maintained at a high level. Therefore, a pulse signal with a high level and a long period is output from the output node NC. For example, the counter 42 counts the pulse signal output from the output node NC to detect the temperature. The count of the counter 42 is supplied to the sub C P U 1 3 described above. Fig. 20 shows an example of the operation of the second embodiment and the use of the output signal of the temperature detection unit 31 described in -19-1236583 (16). In Fig. 20, the same parts as those in Fig. 4 are assigned the same reference numerals. In Fig. 20, when the sub CPU 13 interrupts the processing of the main CPU 12, the temperature of the semiconductor wafer is monitored in accordance with the output signal of the temperature detecting section 31 (S 3 1). In addition, the secondary C P U 1 3 monitors the magnitude of the load (S 3 2). Then, it is judged whether the temperature is higher than the reference value and whether the load is lower than the reference value (S33). That is, at high temperatures, the compensation (Penalty) of the main CPU 12 with a large startup leakage current is large. Therefore, when the load is small, it is expected that the power consumption under such a composite condition can be suppressed by the extremely fine PM processing that minimizes the startup of the main CPU 12. Therefore, when the temperature is high and the load is small, the startup interval of the power control (PM) is shortened, and the judgment criterion of the load is increased (S35). When the conditions in step S 3 3 are not satisfied, it is judged whether the temperature is lower than the reference value and whether the load is greater than the reference value (S34). That is, at a low temperature, the cycle of starting the main CPU 12 with a large leakage current becomes relatively small, and when the load is large, the additional burden of starting the power control (PM) of the sub CPU 13 becomes relatively large. Therefore, under such a composite condition, the PM processing by suppressing the start of the sub CPU 1 3 can further suppress power consumption. Therefore, the starting interval of the PM is increased, and the judgment criterion of the load is reduced (S 3 6). When the conditions of the above step S34 are not satisfied, the start interval of the PM and the determination criterion of the load are not changed. In this way, after the start interval of the PM and the determination criterion of the load are controlled, the magnitude of the determination load is the same as in the first embodiment, and the operation modes of the main CPU 13 and the sub CPU 13 are controlled in accordance with the determined load. According to the second embodiment described above, the temperature of the semiconductor wafer 11 is designed to be -20- (17) 1236583 degrees. The detection unit 31 is controlled according to the temperature detected by the temperature detection unit 31, and the start-up interval and load of the PM are controlled. The judgment criterion 値 ′ controls the operation mode of the main CPU 12 and the sub CPU 13 in accordance with the magnitude of the load in the dog's stomach state. Therefore, by switching the operations of the first and second C P U 1 2, 1 3 according to the temperature in the semiconductor wafer 11, the leakage current can be suppressed to a minimum, and the reduction in the processing capacity can be suppressed. Further, in the first and second embodiments described above, the case where the main cpU and the sub CPU have operation modes 2 to 3 of the fast mode, the execution mode, and the sleep mode will be described. However, it is not limited to this, and may have three or more operation modes. That is, it is not limited to a plurality of discrete operation modes, and the first and second implementation modes can be applied to a CPU having a continuous operation mode. The present invention is not limited to those described in the above embodiments, and various modifications can be made without departing from the scope of the invention. [Industrial Applicability] As described in detail above, the present invention provides a semiconductor device capable of reducing the power leakage of the system during operation in response to a load state or temperature change. Therefore, a processing program called SoC (Processor) can be effectively used in the field of relatively large-scale semiconductor integrated circuits. [Brief Description of the Drawings] FIG. 1 is a configuration diagram of a semiconductor device according to a first embodiment. Figure 2 is the relationship between the performance and power consumption of the main and sub CPUs. (18) 1236583 Corresponding to each operation mode. 3A to 3D are modified examples of the main CPU and the sub CPU in the first embodiment. Fig. 4 is a flowchart showing an example of the operation of the first embodiment. Fig. 5 is a flowchart showing the operation of a conventional semiconductor device. Figures 6A to 6B are diagrams showing the operation of the conventional and first embodiments. Fig. 7 is a diagram showing the relationship between the relative performance and power consumption in the conventional and first embodiments. Fig. 8 is a graph showing the relationship between Busy and average power consumption in the conventional and first embodiment. Fig. 9 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a configuration diagram of an example of a temperature detection section. Fig. 11 is a configuration diagram of another example of the temperature detection section. Figure 12 shows the relationship between temperature and leakage current. Figures 1 A through 13 D are circuit diagrams showing examples of leakage current sources and DC or operating current sources. Fig. 14 is a circuit diagram of an example of an AC current source. Figures 15A and 15B are circuit diagrams showing other examples of leakage current sources and DC or operating current sources. Fig. 16 is a circuit diagram of a specific example of the 'k-degree detecting section. Fig. 17 is a circuit diagram of a specific example of a temperature detecting section using a logic circuit and a leakage current source. -22- 1236583 (19) Figure 18 is a block diagram showing an example of a variable pulse generator. Figures 19A and 19B are waveform diagrams showing the operations of Figures 17 and 18. Fig. 20 is a flowchart showing an example of the operation of the second embodiment. Main component comparison table 11 Semiconductor wafer 12 Main CPU 13 畐! ] CPU 14 I / O control section 15 Timer 16 Interrupt controller 17 System bus 3 1 Temperature detection section 32 Shallow leakage current source 32A, 32B, 33 A, 33B, 41B P-channel MOS transistor 33 DC current source 33C Inverter Circuit 33D resistor 33E capacitor 33F transistor 34, 41C > 53 comparator 35 logic circuit
-23- (20) 1236583 3 6 洩漏電流源 4 1 A 可變脈衝產生電路 4 1 D 驅動器 42 > 5 2 計數器 NC 輸出節點 NB 連接節點 Vdd 電流源 CLK 系統時脈信號 EN 允許信號 IV1、IV2 反相電路 24--23- (20) 1236583 3 6 Leakage current source 4 1 A Variable pulse generating circuit 4 1 D driver 42 > 5 2 Counter NC output node NB Connection node Vdd Current source CLK System clock signal EN enable signal IV1, IV2 Inverting circuit 24-