JP2004280378A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power leakage during system operation in dependence on a load state and a temperature variation. <P>SOLUTION: A semiconductor chip 11 has therein a sub CPU 13 lower in throughput and higher in power consumption efficiency than a main CPU 12, and the sub CPU 13 controls power during system operation. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to reducing the power of a relatively large-scale semiconductor integrated circuit including, for example, a processor called an SoC (System on Chip).
[0002]
[Prior art]
It is important to reduce the power consumption of a semiconductor integrated circuit (hereinafter, abbreviated as LSI) in order to realize low power consumption of a product using the same. In the future, when miniaturization is further advanced and the degree of integration of the LSI is improved, it is expected that the amount of heat generated per unit area will increase. For this reason, from the viewpoint of circuit reliability, it is expected that demand for lower power of LSIs will be further increased.
[0003]
The power consumption of the CMOS LSI is classified into a dynamic component and a leak component. In current processing technology, leakage due to miniaturization is small, and most of the dynamic power is used. However, it is expected that the leak power will increase rapidly as the fine processing technology further advances. In optimizing various processing parameters of the CMOS transistor, the operating speed and the leak power generally have a positive correlation. That is, the leakage power is increased by improving the operation speed. Furthermore, it is known that the leak power has a temperature dependency, and the leak increases as the temperature rises.
[0004]
As a technique for realizing low power, a so-called “system low power” technique for realizing low power by controlling processing performance in accordance with a spatio-temporal variation in processing load of a system is effective. The basic idea of this method is to reduce unnecessary power consumption by operating the system in a low-power, low-power mode at low load.
[0005]
The main approaches for system low power are roughly classified into the following two.
[0006]
(1) Transition to low speed (low power) mode at low load. Example: Crusoe ^TM Processor
(2) Transition to stop mode with no load (idle). Example: ACPI (Advanced Configuration and Power Interface)
In order to realize such system power reduction, power control (hereinafter abbreviated as PM) for performing processing of monitoring a system load, selecting an operation mode, and instructing operation is required.
[0007]
As the degree of integration of LSIs has been improved, system power reduction has become applicable within a single LSI. That is, in the past, it has been general to reduce the power consumption of a system such as a personal computer in which a system composed of many components is controlled by a CPU chip which is one of the components. However, recently, both the controlling side and the controlled side can be integrated in a single LSI.
[0008]
In addition, there are the following technologies related to system power reduction.
[0009]
A technique for reducing power consumption by controlling on / off of a main CPU composed of a RISC processor and a sub CPU composed of a CISC processor having different thermal efficiencies (for example, see Patent Document 1).
[0010]
A technology that optimizes power consumption by changing the operation mode of a CPU according to a load (for example, see Patent Document 2).
[0011]
Furthermore, in a multiprocessor capable of parallelizing processes (tasks), a technology for optimizing power consumption by setting an optimal operation mode (power supply voltage, frequency of a clock signal) for each processor (for example, Non-Patent Document 1) reference).
[0012]
Also, there is a method in which two processors having different processing performances are prepared, and the two processors are switched according to the required performance (for example, see Non-Patent Document 2).
[0013]
[Patent Document 1]
JP-A-7-325788
[0014]
[Patent Document 2]
JP-A-2002-41160
[0015]
[Non-patent document 1]
“Energy-Aware Runtime Scheduling for Embedded Multiprocessor SOCs” IEEE Design & Test of Computers, 2001
[0016]
[Non-patent document 2]
“Proposal of Low Energy Consumption by Switching Rabbit / Turtle Processor” TECHNICAL REPORT OF IEICE. VLD2002-161, ICD2002-226 (2003-03), p. 37-42
[0017]
[Problems to be solved by the invention]
By the way, in the conventional system low power method, PM processing is generally performed by processing of software operated by one CPU. The reason for this is that the PM process requires a complicated determination process, so that it is easier and more realistic to realize it by software. Also, it is natural to utilize the same CPU to grasp the processing load of the CPU.
[0018]
Since the CPU has a large circuit scale, the power consumption itself is large. Further, since it is necessary to operate at a high speed, there is a tendency that the leak power increases. It is expected that this tendency will become more prominent as microfabrication proceeds in the future. As a result, when PM is performed by software processing, power consumed by PM that does not directly involve the CPU in application processing increases.
[0019]
On the other hand, there is a growing demand from applications to improve the peak performance of the CPU. In order to increase the peak performance of the CPU, a method of adding a hardware resource, such as mounting a cache memory, is often used. However, this also causes an increase in the leakage power, and exacerbates the problem.
[0020]
As described above, conventionally, since PM is performed by a CPU having a high processing capability and a low power consumption efficiency, it has been difficult to reduce leak power during system operation.
[0021]
In a system including a plurality of CPUs, when switching the CPU, it is important to accurately detect the state of the load. However, conventionally, the state of the load has not been sufficiently monitored. Furthermore, a leak current corresponding to a temperature change of a semiconductor chip has not been sufficiently considered. Therefore, there is a demand for sufficiently improving the power consumption efficiency of the system according to the state of the load and a change in temperature.
[0022]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of reducing leakage power during system operation according to a load state or a temperature change. It is something to offer.
[0023]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor device according to the present invention has a semiconductor chip, a first CPU mounted on the semiconductor chip and executing a process, and a peak performance mounted on the semiconductor chip and higher than the first CPU. Low, the second CPU with high power efficiency, the second CPU monitors the load, if the load is large, causes the first CPU to execute processing, if the load is small, The processing is executed in place of the first CPU.
[0024]
Further, the semiconductor device of the present invention includes a semiconductor chip, a first CPU mounted on the semiconductor chip and executing a process, and a peak performance lower than the first CPU mounted on the semiconductor chip and lowering power efficiency. And a detection unit for detecting the temperature of the semiconductor chip, wherein the second CPU changes a load criterion according to the temperature detected by the detection unit, When the load is large, the first CPU executes the process when the load is large, and when the load is small, the process is executed instead of the first CPU.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0026]
(1st Embodiment)
FIG. 1 shows an example of an SoC using an asymmetric multi-CPU according to the first embodiment of the present invention.
[0027]
In FIG. 1, a semiconductor chip 11 includes a main CPU 12, a sub CPU 13, an input / output control unit (I / O) 14, a timer 15, an interrupt controller 16, a memory (not shown), and the like. The main CPU 12, the sub CPU 13, the input / output control unit (I / O) 14, the timer 15, and the interrupt controller 16 are connected by a system bus 17. The main CPU 12 has a sleep mode, a run mode, and a sprint mode operating at peak performance, and the sub CPU 13 and the input / output control unit 14 have a sleep mode and a run mode. The run mode operates at a lower speed than the sprint mode. The timer 15 and the interrupt controller 16 have a run mode.
[0028]
The sub CPU 13 constitutes a PM unit, and is capable of executing the application processing of the main CPU 12 when the load is low. The sub CPU 13 has a more compact configuration than the main CPU 12. That is, the main CPU 12 has, for example, a cache memory and a multi-stage pipeline, and further has a branch prediction function. On the other hand, the sub CPU 13 does not have, for example, a cache memory and a branch prediction function, and is designed to have a smaller number of pipeline stages than the main CPU 12. For this reason, the sub CPU 13 is designed to have higher power consumption efficiency than the main CPU 12. That is, the main CPU 12 is designed to have high peak performance and low power consumption efficiency, and the sub CPU 13 is designed to have low peak performance and high power consumption efficiency as compared with the main CPU 12.
[0029]
FIG. 2 shows a relationship between the performance and the power consumption of the main CPU 12 and the sub CPU 13 corresponding to each operation mode.
[0030]
In the main CPU 12, for example, in the sprint mode, the clock frequency is set to the maximum frequency Fmax, and the body voltage Vbb is applied. In the run mode, the clock frequency is set to 1/2 of the maximum frequency, and the body voltage Vbb is not applied. Further, in the sleep mode, the clock frequency is stopped, and the body voltage Vbb is not applied.
[0031]
The power consumption of the main CPU 12 in the sprint mode is, for example, 100 mW of leak power, 100 mW of dynamic power, and 200 mW in total power. In the run mode, the power consumption is, for example, 20 mW, 50 mW of dynamic power, and 70 mW of total power. In the sleep mode, the leak power is, for example, 10 mW, the dynamic power is 0 mW, and the total power is 10 mW.
[0032]
For example, the clock frequency of the sub CPU 13 is set to １ ／ of the maximum frequency in the run mode, and the clock frequency is stopped in the sleep mode. The sub CPU 13 does not receive the body voltage Vbb.
[0033]
In the run mode, the power consumption of the sub CPU 13 is, for example, 4 mW, the dynamic power is 10 mW, and the total power is 14 mW. In the sleep mode, the leakage power is, for example, 1 mW, the dynamic power is 0 mW, and the total power is 1 mW. It is.
[0034]
FIGS. 3A to 3D show an example in which PM is realized by the sub CPU. 3A to 3D, the resources include the cache memory, the branch prediction, the instruction memory, and the like.
[0035]
FIG. 3A shows a basic configuration, and shows a configuration for changing system resources as described in FIG. That is, the resources 21 connected to the sub CPU 13 are configured to be smaller and have a lower leak than the resources 22 connected to the main CPU 12.
[0036]
FIG. 3B shows a case where a compatible instruction set is used for the main CPU 12 and the sub CPU 13. In this case, the main CPU 12 and the sub CPU 13 can share the resource 23 by optimizing the resource 23 such as the instruction memory. With such a configuration, it is possible to reduce overhead of the main CPU 12 and the sub CPU 13.
[0037]
FIG. 3C shows a case where a sub CPU 13 having an emulation function capable of executing an instruction set used by the main CPU is used. With such a configuration, the sub CPU 13 can share the program used by the main CPU 12, and can share the resources 23 as in the configuration of FIG.
[0038]
FIG. 3D is a modification of FIG. 3B and shows a case where a plurality of main CPUs 12 are provided. By providing a plurality of main CPUs 12 as described above, peak performance can be improved.
[0039]
FIG. 4 shows an example of the operation in the basic configuration of the first embodiment shown in FIGS. 1 and 3A to 3D. As described above, the main CPU 12 has the sleep mode and the sprint mode, and the sub CPU 13 monitors the state of the load, and switches between the operation modes of the main CPU and the sub CPU according to the magnitude of the load.
[0040]
In FIG. 4, for example, an application (APP) such as multimedia processing is started by the main CPU (M-CPU) 12, for example (S1). First, the main CPU 12 performs processing in the sprint mode so that processing can be performed even under the worst condition under the heaviest load (S2). Next, for example, the application processing of the main CPU 12 is interrupted (S3). Then, the sub CPU 13 determines whether the application process has been completed (S4). As a result, when the application processing ends, the operation of the main CPU 12 ends.
[0041]
On the other hand, if the processing is not completed, the sub CPU (S-CPU) 13 starts the power control processing (PM) (S5). That is, the load is monitored by the sub CPU 13 (S6). In this state, when the load is large, the application processing is restarted by the main CPU 12 (S8), and thereafter, the application processing is executed by the main CPU 12 in the sprint mode (S9), and then the processing is interrupted. Is performed (S10).
[0042]
When it is determined that the load is moderate, the application processing is restarted by the main CPU 12 (S11). Thereafter, the application processing is executed in the run mode by the main CPU 12 (S12), and then the processing is interrupted (S12). S13).
[0043]
Further, when it is determined that the load is small, the application processing is restarted by the sub CPU 13 (S14), and thereafter, the application processing is executed in the run mode by the main CPU 13 (S15), and then the processing is interrupted (S16). ).
[0044]
When it is determined that the load is extremely small, the sub CPU 13 is set to the sleep mode (pause) for a certain period (S17).
[0045]
After the interruption of each process and the sleep mode, the sub CPU 13 determines again whether or not the application process has been completed (S4), and the above operation is repeated according to the result.
[0046]
For the load monitoring, for example, two methods can be considered. The first method is a method using the execution time of the application process as an index of the load, and the second method is the method using the waiting time of the application process as the index of the load.
[0047]
In the first method, as the configuration of the application program, an instruction to call a PM activation function (a function for activating PM processing) is set at, for example, one of the main processes of the application program. When the application process shown in FIG. 4 starts (S1), the timer 15 shown in FIG. 1 is started. When the PM start function is called during the application processing, the application processing is interrupted in steps S3, S10, S13, and S16 shown in FIG. That is, in the load monitoring operation in step S6, the sub CPU 13 reads the value of the timer 15 and calculates the difference from the value read in the previous PM process. The time difference of the timer calculated in step S6 corresponds to the execution time of the application processing required for the same processing procedure. Therefore, when this value is large, the load of application processing is large.
[0048]
On the other hand, in the second method, as a configuration of the application program, a global variable accessible from both the application program and the PM process is set, and when waiting for data input from the I / O 14 shown in FIG. Is programmed to increment. At the start of the application process (S1) shown in FIG. 4, the timer 15 and the interrupt controller 16 are set so as to be interrupted at regular time intervals. When an interrupt occurs during the application processing, the application processing is interrupted and the processing shifts to the PM processing by the sub CPU 13 as in steps S3, S10, S13, and S16 shown in FIG. That is, in the load monitoring operation of step S6, the sub CPU 13 reads a global variable. This global variable measures the dead time during which the application process has been waiting for data input within a specific period. For this reason, when the value of the read global variable is large, the application program has a long standby time, and the load is relatively small.
[0049]
According to the first embodiment, the sub CPU 13 having lower peak performance and higher power efficiency than the main CPU 12 is incorporated in the semiconductor chip 11, and the sub CPU 13 monitors the load state. Application processing is executed by the sub CPU 13 instead of the CPU 12. Therefore, except when a high-performance function is required, processing is performed by the sub CPU 13 having high power consumption efficiency, so that power consumption during operation of the system can be significantly reduced.
[0050]
FIG. 5 shows a flowchart of a conventional semiconductor device in which PM processing is performed by one CPU. In the case of the conventional semiconductor device shown in FIG. 5, one CPU is set to a sprint mode (S8-S10), a run mode (S21-23), and a sleep mode (S17) in accordance with a large, small, or minimal load. You.
[0051]
FIG. 6 illustrates an example of the operation of the CPU according to the related art and the first embodiment. The horizontal axis indicates a time axis, and schematically illustrates a state in which the operation mode changes with time. In the case of the related art shown in FIG. 6A, one CPU is set to a sprint mode (Sp), a run mode (R), and a pause mode (S1) according to the load state. On the other hand, in the case of the first embodiment shown in FIG. 6B, the two CPUs of the main CPU and the sub CPU are operated in the sprint mode (Sp), the run mode (R), and the sleep mode according to the load state. It can be seen that it has been switched to (S1).
[0052]
The conventional control operation shown in FIG. 6A is a polygonal control that connects points corresponding to the sprint mode, the run mode, and the sleep mode of the curve shown by the main CPU 12 in FIG. On the other hand, in the case of the first embodiment shown in FIG. 6B, a polygonal line control connecting points corresponding to the sprint mode and the run mode of the main CPU 12 and the run mode and the sleep mode of the sub CPU 13 is used. Become. For this reason, in an application having a small average load, low relative performance, and a long processable period, power consumption can be suppressed.
[0053]
FIG. 8 shows the average power consumption of the conventional and the first embodiment. As described above, it can be seen that the average power consumption of the present embodiment is lower than that of the related art at each busy ratio. Therefore, according to the first embodiment, the average power consumption can be reduced to 1/3 to 2/3 as compared with the conventional case.
[0054]
In the case of the first embodiment, the performance of the main CPU 12 and the sub CPU 13 is changed depending on the architecture of the computer. However, instead of this method, it is also possible to change a library in semiconductor manufacturing. For example, it is also possible to apply a method of tuning the adder and the latch circuit constituting the sub CPU 13 to a low speed and low power consumption operation as compared with those of the main CPU 12. That is, the main CPU 12 can be configured with a high-speed library, and the sub CPU 13 can be configured with a low-speed and low-leakage library as compared with the main CPU 12.
[0055]
(Second embodiment)
FIG. 9 shows a second embodiment of the present invention. 9, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.
[0056]
As described above, the leak current of the semiconductor element increases as the temperature rises. In addition, when the temperature is kept constant, the leak current increases as the gate length of the semiconductor device becomes smaller. For this reason, the power consumption of the semiconductor device can be further optimized by taking the temperature of the semiconductor chip into consideration in managing the power consumption. Therefore, in the second embodiment, the temperature detection unit 31 is disposed in the semiconductor chip 11, and the power consumption of the semiconductor device is managed according to the output signal of the temperature detection unit 31.
[0057]
In managing power consumption, the physical Kelvin temperature is not so important, and the ratio of leakage current to operating current (hereinafter referred to as leakage ratio) is important. For this reason, the temperature detector 31 detects the temperature relatively by measuring the leak ratio instead of measuring the Kelvin temperature.
[0058]
FIG. 10 illustrates an example of the temperature detection unit 31. The temperature detecting section 31 includes a leak current source 32, a DC current or operating current source 33 of a transistor, and a comparator. The comparator 34 compares the leak current from the leak current source 32 with the DC current of the transistor or the current from the operating current source 33 to measure a leak ratio. The measured temperature as the leak ratio is supplied to the sub CPU 13. The sub CPU 13 applies an algorithm for switching the operation mode according to the measured temperature.
[0059]
FIG. 11 shows another example of the temperature detection unit 31. The temperature detecting unit 31 includes, for example, a logic circuit 35 and a leak current source 36 connected in series, and measures a leak ratio according to the operation of the logic circuit 35. The measured leak ratio is supplied to the sub CPU 13. The sub CPU 13 applies an algorithm for switching the operation mode according to the measured leak ratio.
[0060]
FIG. 12 shows the relationship between the temperature and the leak current. The temperature detecting section 31 is designed so that the leak current and the DC current (ON current) or the AC current become equal at a temperature of, for example, about 50 ° C.
[0061]
FIGS. 13A and 13B show an example of the leak current source 32, and FIGS. 13C and 13D show an example of the DC current source. FIG. 13A includes a P-channel MOS transistor 32A which is always off. FIG. 13B includes a P-channel MOS transistor 32B. The power supply Vdd is supplied to the gate of the transistor 32B, and the control signal is supplied to the source. This control signal is set to the power supply voltage Vdd at the time of measurement, and is set to the ground potential at the time of suspension. FIG. 13C shows a P-channel MOS transistor 33A whose gate is grounded and which is always on. FIG. 13D includes a P-channel MOS transistor 33B. A control signal is supplied to the source of the transistor 33B, and the gate is grounded. This control signal is set to the power supply voltage Vdd at the time of measurement, and is set to the ground potential at the time of suspension. The channel width of the transistors 32A and 32B constituting the leakage current source and the channel width of the transistors 33A and 33B constituting the DC current source are determined by the characteristics of the device. Since the DC current is generally much larger than the leak current, the former is larger. In addition, in the case of the circuit configurations illustrated in FIGS. 13B and 13D, unnecessary current can be cut because the transistor is turned off at the time of suspension.
[0062]
FIG. 14 shows an example of an AC (alternating current) current source 33. The AC current source 33 includes, for example, an inverter circuit 33C, a resistor 33D, and a capacitor 33E connected in series. For example, a system clock signal CLK is supplied to an input terminal of the inverter circuit 33C. The output signal of the inverter circuit 33C is supplied to the comparator 34 via a filter circuit including a resistor 33D and a capacitor 33E. The comparator 34 compares the output signal of the leak current source 32 with the output signal of the filter circuit. The filter circuit and the comparator 34 constitute a 1-bit AD conversion circuit that outputs temperature information as a digital signal.
[0063]
FIG. 15 shows another example of the leak current source 32, the DC current source 33, or the operating current source. In FIG. 15A, the output current is controlled by connecting a plurality of P-channel MOS transistors in series / parallel and controlling the conduction of these transistors by a control signal. FIG. 15B shows that the current capability can be controlled by controlling the conduction of a plurality of P-channel MOS transistors connected in parallel with a control signal.
[0064]
With such a configuration, the capability of the current source is made variable. Therefore, it is possible to change the setting of the changing point of the temperature (leak ratio). Also, the same circuit can be used when manufacturing technologies having different device characteristics are used.
[0065]
FIG. 16 shows an example of a specific circuit of the temperature detection unit 31, and the same parts as those in FIG. 10 are denoted by the same reference numerals. This circuit is composed entirely of N-channel MOS transistors. The DC current source 33 includes a plurality of transistors 33C, 33D, and 33E connected in series, and a transistor 33F connected in parallel to these transistors. A high-level signal (Vdd) for constantly turning on the transistors is supplied to the gates of the transistors 33C, 33D, and 33E, and an enable signal EN is supplied to the drains of the transistors 33C and 33F. This enable signal EN is set to a high level (Vdd) during temperature measurement. When increasing the DC current, the transistor 33F is turned on. The leak current source 32 is configured by a transistor 32C, and the comparator 34 is configured by inverter circuits IV1 and IV2 connected in series.
[0066]
In the above configuration, when the temperature is high, the current flowing through the leak current source 32 increases, and the input terminal of the comparator 34 becomes low level. Therefore, the output signal of the comparator 34 becomes low level. On the other hand, when the temperature is low, the input terminal of the comparator 34 is charged to a high level because the leak current decreases. Therefore, the output signal of the comparator 34 becomes high level.
[0067]
FIG. 17 shows an example of the temperature detector 31 using the logic circuit and the leak current source shown in FIG. In the temperature detector 31, the logic circuit 35 includes a variable pulse generator 41A, a P-channel MOS transistor 41B, a comparator 41C, and a driver 41D. The leak current source 36 is constituted by an N-channel MOS transistor 41E having a large channel width. The variable pulse generator 41A is connected to the gate of a P-channel MOS transistor 41B. One input terminal of a comparator 41C is connected to a connection node between the P-channel MOS transistor 41B and the N-channel MOS transistor 41E. The other input terminal of the comparator 41C is connected to the output terminal of the comparator 41C. The driver 41D is connected to this output terminal. A counter 42 is connected to the output terminal of the driver 41D. This counter 42 counts pulse signals output from the driver 41D.
[0068]
FIG. 18 shows an example of the variable pulse generator 41A. The variable pulse generator 41A includes a reference register 51, a counter 52, and a comparator 53. The reference register 51 holds, for example, a reference value indicating a pulse duty supplied from the sub CPU 13. The counter 52 counts the clock signal CLK according to the enable signal EN. This counter is reset to "0" when all become "1". The comparator 53 outputs data “1” when the count value of the counter 52 is larger than the reference value held in the reference register 51, and outputs data “0” when the count value is smaller. That is, the variable pulse generator 41A outputs a pulse signal having a low frequency.
[0069]
FIG. 19 shows the operation of FIGS. FIG. 19A shows a case where the temperature is high, that is, a case where the leak current is large, and FIG. 19B shows a case where the temperature is low, that is, a case where the leak current is small.
[0070]
17, a variable pulse generator 41A outputs a pulse signal NA having a duty corresponding to the reference value. P-channel MOS transistor 41B charges connection node NB during the low-level period of pulse signal NA. When the temperature is high, the current flowing through the leak current source 36 is large. Therefore, the charge of the connection node NB is rapidly discharged as shown in FIG. Therefore, a pulse signal having a short high-level cycle is output from output node NC.
[0071]
On the other hand, when the temperature is low, the current flowing through the leak current source 36 decreases. Therefore, the charge of the connection node NB is held, and the connection node NB maintains the high level. Therefore, a pulse signal having a long high-level cycle is output from output node NC.
[0072]
The temperature can be detected by counting the pulse signal output from the output node NC by, for example, the counter 42. The count value of the counter 42 is supplied to the sub CPU 13.
[0073]
FIG. 20 shows an operation of the second embodiment, and shows an example of an operation using an output signal of the temperature detection unit 31. 20, the same components as those in FIG. 4 are denoted by the same reference numerals.
[0074]
In FIG. 20, when the processing of the main CPU 12 is interrupted, the sub CPU 13 monitors the temperature of the semiconductor chip according to the output signal of the temperature detecting unit 31 (S31). Further, the sub CPU 13 monitors the magnitude of the load (S32). Thereafter, it is determined whether the temperature is higher than the reference value and the load is lower than the reference value (S33). That is, at a high temperature, a penalty for starting the main CPU 12 having a large leak current is large. For this reason, when the load is small, it is expected that power consumption under such complex conditions can be further suppressed by a fine PM process that minimizes the activation of the main CPU 12. Therefore, when the temperature is high and the load is small, the start interval of the power control (PM) is shortened, and the load determination reference value is increased (S35).
[0075]
If the condition in step S33 is not satisfied, it is determined whether the temperature is lower than the reference value and the load is higher than the reference value (S34). That is, at low temperatures, the penalty for starting the main CPU 12 having a large leak current is relatively small, and when the load is large, the overhead for starting the power control (PM) of the sub CPU 13 is relatively large. Therefore, under such complex conditions, the power consumption can be further suppressed by the PM process in which the activation of the sub CPU 13 is suppressed. Therefore, the start interval of PM is increased, and the load determination reference value is reduced (S36).
[0076]
If the condition in step S34 is not satisfied, the PM activation interval and the load criterion value are not changed. After the start interval of the PM and the load determination reference value are controlled in this manner, the magnitude of the load is determined in the same manner as in the first embodiment, and the main CPU 12 and the sub CPU 13 are determined in accordance with the determined load. Is controlled.
[0077]
According to the second embodiment, the temperature detection unit 31 is provided in the semiconductor chip 11, and according to the temperature detected by the temperature detection unit 31, the start interval of the PM and the load determination reference value are controlled. In this state, the operation modes of the main CPU 12 and the sub CPU 13 are controlled according to the magnitude of the load. Therefore, by switching the operations of the first and second CPUs 12 and 13 in accordance with the temperature in the semiconductor chip 11, the leak current can be minimized, and the decrease in processing capability can be suppressed.
[0078]
In the first and second embodiments, the case where the main CPU and the sub CPU have two or three operation modes such as the sprint mode, the run mode, and the sleep mode has been described. However, the present invention is not limited to this, and it is possible to have three or more operation modes. That is, the first and second embodiments can be applied not only to a plurality of discrete operation modes but also to a CPU having a continuous operation mode.
[0079]
In addition, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the invention.
[0080]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a semiconductor device capable of reducing leakage power during operation of a system according to a load state or a temperature change.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a semiconductor device according to a first embodiment.
FIG. 2 is a diagram illustrating a relationship between performance and power consumption of a main CPU and a sub CPU in correspondence with each operation mode.
FIG. 3 is a diagram showing a modification of the main CPU and the sub CPU in the first embodiment.
FIG. 4 is a flowchart showing an example of the operation of the first embodiment.
FIG. 5 is a flowchart showing the operation of a conventional semiconductor device.
FIG. 6 is a diagram schematically showing operations of the conventional and the first embodiment.
FIG. 7 is a diagram schematically showing a relationship between relative performance and power consumption of the conventional and the first embodiment.
FIG. 8 is a diagram illustrating a relationship between a busy ratio and an average power consumption according to the related art and the first embodiment.
FIG. 9 is a configuration diagram showing a semiconductor device according to a second embodiment of the present invention.
FIG. 10 is a configuration diagram illustrating an example of a temperature detection unit.
FIG. 11 is a configuration diagram showing another example of the temperature detection unit.
FIG. 12 is a graph showing a relationship between temperature and leakage current.
FIG. 13 is a circuit diagram showing an example of a leak current source and a DC or operating current source.
FIG. 14 is a circuit diagram showing an example of an AC current source.
FIG. 15 is a circuit diagram showing another example of a leak current source and a DC or operating current source.
FIG. 16 is a circuit diagram showing a specific example of a temperature detection unit.
FIG. 17 is a circuit diagram showing a specific example of a temperature detector using a logic circuit and a leak current source.
FIG. 18 is a configuration diagram showing an example of a variable pulse generator.
FIG. 19 is a waveform chart showing the operation of FIGS. 17 and 18.
FIG. 20 is a flowchart illustrating an example of an operation according to the second embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Semiconductor chip, 12 ... Main CPU, 13 ... Sub CPU, 21, 22, 23 ... Resource, 31 ... Temperature detection part, 32 ... Leakage current source, 33 ... DC or operating current source, 34 ... Comparator, 35 ... Logic circuit, 36: leak current source, 41A: variable pulse generator.

Claims (15)

A semiconductor chip,
A first CPU mounted on the semiconductor chip and executing a process;
A second CPU mounted on the semiconductor chip and having lower peak performance than the first CPU and higher power efficiency;
The second CPU monitors a load, and causes the first CPU to execute a process when the load is large, and executes the process instead of the first CPU when the load is small. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the first and second CPUs have a plurality of operation modes. The semiconductor device according to claim 1, wherein the first CPU and the second CPU share resources. 2. The semiconductor device according to claim 1, wherein the first and second CPUs are instruction-compatible CPUs. 2. The semiconductor device according to claim 1, wherein the second CPU has a function of emulating an instruction set of the first CPU. 2. The semiconductor device according to claim 1, wherein the first CPU includes a plurality of CPUs. 2. The semiconductor device according to claim 1, wherein the second CPU monitors a load by detecting an execution time of an application process. 2. The semiconductor device according to claim 1, wherein the second CPU monitors a load by detecting a waiting time of an application process. A semiconductor chip,
A first CPU mounted on the semiconductor chip and executing a process;
A second CPU mounted on the semiconductor chip and having lower peak performance and higher power efficiency than the first CPU;
A detecting unit for detecting the temperature of the semiconductor chip,
The second CPU changes a load criterion in accordance with the temperature detected by the detection unit. If the load is large based on the criterion, the second CPU causes the first CPU to execute a process. When the size is smaller, the semiconductor device executes the processing in place of the first CPU. The detection unit,
A leak current source;
A direct current source or an alternating current source,
10. The semiconductor device according to claim 9, further comprising: a comparator that compares an output of the leakage current source with an output of the DC current source or the AC current source and outputs temperature information. The leakage current source includes a plurality of transistors connected in series and parallel, and a control signal controls the conduction of these transistors to control the amount of leakage current. 11. The semiconductor device according to claim 10, wherein the transistors include the transistors described above, and the control signal controls the conduction of these transistors to control the amount of direct current. The leak current source includes a plurality of transistors connected in series and parallel, these transistors are turned off by a control signal except during measurement, and the DC current source includes a plurality of transistors connected in series and parallel. 11. The semiconductor device according to claim 10, wherein the semiconductor device is turned off by a control signal other than at the time of measurement. The detection unit includes a leak current source and an AC current source,
The AC current source is
A logic circuit for receiving a system clock signal;
A filter circuit connected in series to the logic circuit,
A comparator to which an output signal of the filter circuit and an output signal of the leak current source are supplied,
10. The semiconductor device according to claim 9, wherein the filter circuit and the comparator constitute an AD conversion circuit that outputs temperature information as a digital value. The detection unit,
A logic circuit;
A leakage current source connected in series to the logic circuit,
The logic circuit includes a variable pulse generator capable of changing a duty ratio of a pulse signal, and outputs temperature information according to an output signal of the variable pulse generator. 10. The semiconductor device according to item 9. The variable pulse generator,
A register for holding a reference value supplied from the second CPU;
A counter for counting clock signals,
15. The semiconductor device according to claim 14, further comprising: a comparator that compares the reference value from the register with a count value from the counter and outputs the pulse signal.

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