1236205 ⑴ 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 相關申請案之交叉參考 本申請案主張200 1年12月10曰提出申請，美國申請案字 號60/33 8,923，由G〇米勒等人所寫之’’使用單石N通道上 FET之有效率的整塊拓樸直流至直流功率級”之好處，指 派至本申請案之受讓人，及併此揭示。 技術領域 本發明概言之係關於一種電子電路及其'部件，且尤其係 關於整塊拓樸型直流-直流轉換器之新及改良的功率切 換級架構，該種轉換器具有一上功率切換N通道裝置場效 電晶體，與切換驅動器整合在同一個半導體電路晶片中， 而下功率切換亦是一 N通道場效電晶體，但位於該驅動器 晶片之外。此外，此二功率切換場效電晶體兩者或其一均 可設計成包含一先導場效電晶體單元，使控制器之電流i 測更為容易。 先前技術 積體電路（IC)之電力典型地由一或多個直流電源供應 ，這種電源譬如，圖1所未之整塊模式，脈寬調變（PWM) 型直流-直流型式。如圖中所示，一控制器1 0供應一同步 PWM信號至驅動器20，用以控制一對電子功率切換裝置 之導通及關閉，此對裝置在驅動器電路2 0之外部；並連接 至功率負載6 5。在所繪之直流-直流轉換器中，該外部電 子功率切換裝置繪成一上（或高側）功率N金氧半場效電晶 體（或NFET)裝置30，以及一下（或低側）功率NFET裝置40 1236205 _ (3) 發明說明績頁 1.2-1.5 VDC等級之輸出電壓）。在此狀況中，該上功率FET( 其典型地操作在相對較低之工作週期（譬如，在百分之十 至十二等級）會引入明顯的切換損失，特別是因為其為外 部裝置，具有實質的寄生阻抗。另一方面，下FET操作在 相對較高的工作週期，不會遭受切換型功率散逸之苦。 應付此問題之提案是將上、下FET整合至一般具驅動器 之積體電路晶片中，如圖4所繪。圖中有兩個N通道裝置 ，或如圖5所示其中上裝置是P通道裝置，下裝置是N通道 裝置。此法的缺點是最終之積體電路要容納兩個功率切換 裝置有相當可觀的製作成本。另一種方案，示於圖6，乃 將上P通道整合在與驅動器同一晶片中，但將下N通道FET 留置作為外部裝置。 此法之好處在於上FET相關的工作週期低，可降低切換 損失，必須將裝置整合在通用電路晶片之成本亦可降低 (以閘驅動的觀點來看，P通道裝置較易施行）。此亦取下 列之優點，即下NFET裝置操作在相對較高之工作週期， 其施行相當地標準化。 現在，雖然圖6之部份積體化的方法較圖1 - 5之全在外 部或全積體化的方法改良，但使用P通道FET作為上功率 切換裝置將有相當明顯的較高導通電阻及矽所佔面積很 大。 發明内容 根據本發明，上述傳統功率切換級拓樸之缺點，可用新 及改良的架構實質地改善，此架構的組成是，將上功率切 1236205 (4) 發明說明續頁 換N通道裝置FET與驅動器整合在相同的半導體電 中，而下功率切換也是一 N通道F E T，但位於驅動 的外部。此外，兩功率切換F Ε τ或兩者其一可設計 ，先導，F Ε Τ單元，以便使控制器的電流感測更為容 、f施方式 現在注意圖7，其圖I之電路架構’為本發明整 型直流-直流轉換器’部份地集成N通道功率切換 圖1架構相似的，控制器7 1 0供應同步P WM信號至 7 2 0。然而，根據本發明’驅動器7 2 0乃用以控制項 功率切換裝置7 3 0及7 4 0之導通及關閉’此對裝置接 負載765。與圖1至6中架構有所不同的是，圖7之直 流轉換器中，上（或高側）功率NM0SFET 730乃集成 的半導體晶片700中，成為驅動器72〇。另一方面， 通道F Ε T 7 3 0之下功率切換裝置’則在晶片7 0 〇的外 先前所述之拓樸，該上及不功率NFET於一對電源 (VIN及GND)間，具沒極-源極電流流動串聯路徑< 上閘極切換信號U G AT E控制著上積體NFET裝3 導通及關閉，内部驅動器7 2 0所供應出之下閘極切 L G AT E則控制著下外部N F Ε T裝置7 4 0之導通及關 ，在圖7之具體實施例中，上NFET裝置730之閘驅 乃勒：帶式，但可直接地以高於電壓v 1N之源極電壓 動。上内部NFET 730及下外部NFET 740間之共節J 透過電感器7 5 0，連接至負載貯積電容器，以地為 。電感器7 5 0及電容器7 6 0間之連結7 5 5則充作輸 路晶片 器晶片 成包含 易。 塊拓樸 級。與 驅動器 對電子 至功率 流-直 於相同 包含N 部。如 供應器 [7 3 0 的 換信號 丨。雖然 動電壓 直接驅 站7 3 5則 參考點 出節點 1236205 (6) 發明說明續頁 所以吾人不希望限制所示之細節及此處之說明，而欲涵蓋 習於此藝人士之所有的此種變更及修改。 圖式之簡單說明 圖1說明傳統的整塊模式，脈寬調變（PWM)型直流-直 流轉換器； 圖2乃圖1之PWM型直流-直流轉換器，具功率切換裝置 之靴帶式閘驅動； 圖3是圖1之PWM型直流-直流轉換器的修正型，具P通 道上切換裝置； 圖4是圖1之PWM型直流-直流轉換器的修正型，其上及 下功率切換裝置均整合在驅動器晶片中； 圖5是圖4之PWM型直流-直流轉換器的修正型，其上功 率切換裝置是P通道裝置； 圖6是圖5之PWM型直流-直流轉換器的修正型，其中該 下功率切換裝置乃在驅動器晶片之外； 圖7是本發明之PWM型直流-直流轉換器之第一具體實 施例，其中上功率切換NFET與驅動器晶片整合在一起， 而該下功率切換NFET則位於驅動器晶片之外； 圖8說明多個N NFET單元，内含Μ先導NFET單元，用於 圖7架構中之電路感測；以及 圖9說明圖7之具體實施例，具先導NFET單元包含於該 外部下N F E T中。1236205 玖 玖, description of the invention (the description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and a brief description of the drawings) Cross-reference to related applications Application, US Application No. 60/33 8,923, written by Go Miller et al. "The benefits of using a single monolithic N-channel FET with an efficient monolithic topology DC to DC power stage" are assigned to this The assignee of the application, and the disclosure thereof. FIELD OF THE INVENTION The present invention relates generally to an electronic circuit and its components, and more particularly to a new and improved power switching of a topological DC-DC converter. Level architecture, this converter has an upper power switching N-channel device field effect transistor, which is integrated with the switching driver in the same semiconductor circuit chip, and the lower power switching is also an N channel field effect transistor, but is located on the driver chip Besides, in addition, both or two of the two power switching field effect transistors can be designed to include a pilot field effect transistor unit, which makes the current i measurement of the controller easier. The power of the prior art integrated circuit (IC) is typically supplied by one or more DC power sources, such as the whole block mode not shown in Figure 1, the pulse width modulation (PWM) type DC-DC type. As shown in the figure, a controller 10 supplies a synchronous PWM signal to the driver 20 to control the on and off of a pair of electronic power switching devices, which are external to the driver circuit 20; and are connected to a power load 6 5 In the drawn DC-DC converter, the external electronic power switching device is depicted as an upper (or high-side) power N-metal-oxide-semiconductor (or NFET) device 30 and a lower (or low-side) power NFET Device 40 1236205 _ (3) Invention description page 1.2-1.5 VDC output voltage level. In this case, the upper power FET (which typically operates at a relatively low duty cycle (for example, at ten percent To the twelfth level) will introduce significant switching losses, especially because it is an external device with substantial parasitic impedance. On the other hand, the lower FET operates at a relatively high duty cycle and will not suffer from the switching power dissipation Should The proposal to solve this problem is to integrate the upper and lower FETs into a general integrated circuit chip with a driver, as shown in Figure 4. There are two N-channel devices in the figure, or the upper device is a P-channel as shown in Figure 5. Device, the lower device is an N-channel device. The disadvantage of this method is that the final integrated circuit has a considerable manufacturing cost to accommodate two power switching devices. Another solution, shown in Figure 6, is to integrate the upper P channel with the The driver is in the same chip, but the lower N-channel FET is left as an external device. The advantage of this method is that the duty cycle of the upper FET is low, which can reduce switching losses. The cost of integrating the device into a general circuit chip can also be reduced From a driving perspective, P-channel devices are easier to implement). This also has the advantage that the lower NFET device operates at a relatively high duty cycle and its implementation is fairly standardized. Now, although the partial integration method of Fig. 6 is improved compared to the external or full integration method of Figs. 1-5, using a P-channel FET as the upper power switching device will have a significantly higher on-resistance. And silicon occupies a large area. SUMMARY OF THE INVENTION According to the present invention, the shortcomings of the traditional power switching stage topology described above can be substantially improved with a new and improved architecture. The composition of this architecture is to cut the upper power to 1236205. (4) Description of the invention Continuation page for the N-channel device FET and The driver is integrated in the same semiconductor, and the lower power switch is also an N-channel FET, but located outside the driver. In addition, two power switching F E τ or one of them can be designed, the pilot, F E T unit, in order to make the controller's current sensing more capacitive, f method. Now pay attention to Figure 7, the circuit architecture of Figure I ' In the present invention, the integral DC-DC converter is partially integrated with N-channel power switching. The structure shown in FIG. 1 is similar. The controller 7 10 supplies a synchronous P WM signal to 7 2 0. However, according to the present invention, the 'driver 7 2 0 is used to control the turning on and off of the power switching devices 7 3 0 and 7 4 0'. This pair of devices is connected to the load 765. Different from the architecture in Figs. 1 to 6, in the DC converter of Fig. 7, the upper (or high-side) power NMOSFET 730 is integrated into the semiconductor wafer 700 and becomes the driver 72. On the other hand, the power switching device 'under the channel F E T 7 3 0 is the topology previously described outside the chip 7 0 0. The upper and lower power NFETs are between a pair of power sources (VIN and GND). The non-polar-source current flow series path < the upper gate switching signal UG AT E controls the upper integrated body NFET device 3 to be turned on and off, and the lower gate LG AT E supplied by the internal driver 7 2 0 controls The lower external NF ET device 7 4 0 is turned on and off. In the specific embodiment of FIG. 7, the gate driver of the upper NFET device 730 is a tape type, but it can directly use a source voltage higher than the voltage v 1N. move. The joint J between the upper internal NFET 730 and the lower external NFET 740 is connected to the load storage capacitor through the inductor 7 50, with ground being. The connection 755 between the inductor 750 and the capacitor 760 is used as a transmission chip, and the chip is easy to include. Block topology. Same as driver-to-electron to power flow-as long as it contains N parts. Such as the supplier [7 3 0 change signal 丨. Although the dynamic voltage directly drives the station 7 3 5 the reference point is out of the node 1236205 (6) Continued description of the invention So I do not want to limit the details shown and the description here, but I want to cover all such people Changes and modifications. Brief Description of the Drawings Figure 1 illustrates the traditional one-piece mode, a pulse width modulation (PWM) DC-DC converter; Figure 2 is the PWM DC-DC converter of Figure 1, a shoelaced type with a power switching device Brake drive; Figure 3 is a modified version of the PWM DC-DC converter of Figure 1 with a switching device on the P channel; Figure 4 is a modified version of the PWM DC-DC converter of Figure 1 with its upper and lower power switching The devices are integrated in the driver chip; Figure 5 is a modified version of the PWM DC-DC converter of Figure 4, the power switching device is a P-channel device; Figure 6 is a modified version of the PWM DC-DC converter of Figure 5 Type, in which the lower power switching device is outside the driver chip; FIG. 7 is a first specific embodiment of the PWM-type DC-DC converter of the present invention, in which the upper power switching NFET is integrated with the driver chip, and the lower The power-switching NFET is located outside the driver chip; Figure 8 illustrates multiple N NFET cells containing M-pilot NFET cells for circuit sensing in the architecture of Figure 7; and Figure 9 illustrates the specific embodiment of Figure 7 with a pilot NFET cell is included in the external In N F E T.