TWI235431B - Method for fabricating deep trench semiconductor component - Google Patents

Abstract

A method for fabricating a deep trench typed semiconductor component is disclosed. The method includes providing a substrate and a mask structure on the substrate. The mask structure has an oxide layer, a pad nitride layer, and a patterned dielectric layer. The substrate is etched by using the patterned dielectric layer as a mask to form a deep trench. A conformal dielectric layer containing arsenic is formed, and the conformal dielectric layer covers the mask structure and the deep trench. A photoresist layer is formed in a portion of the deep trench. A portion of the conformal dielectric layer and the patterned dielectric layer are striped by using the photoresist layer as an etching stop layer. The photoresist layer and a portion of the conformal dielectric layer are striped. A dielectric layer is formed to fill the deep trench. With the thermal process, the arsenic atoms diffuse into the substrate to form a buried plate.

Description

1235431 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for forming a trench-type semiconductor element, and more particularly to a method for forming a trench-type capacitor. [Prior art] ^ Trench semiconductor devices are widely used in today's semiconductor processes, such as trench capacitors. A. A good deep trench is formed on the substrate. Basically, a mask structure is used to etch a deep trench. However, as the size of 70 cow conductors becomes smaller, the traditional trench semiconductor device manufacturing process is not easy to control and control, especially the material of the mask layer that is seen from the step of removing the mask layer. For example, Boron Silicate Glass (BSG), the traditional method is to use a high selectivity etching method to remove the borosilicate glass layer, such as gaseous hydrofluoric acid (Vapor

Hydrofluoric acid (VHF). However, in the process of deep trenches with a small size, the borosilicate glass layer is generally heat-treated to obtain better-quality sapphire glass. However, after the deep trench is formed, the heat-treated acid-glass layer may have the disadvantage of being difficult to remove. As shown in FIG. 9A, a deep trench is formed on the substrate 902, the oxide layer 904, and the nitride layer 9G6, and then the mask is removed with a high selectivity engraving method. Acid glass layer 908. For example, removing the heat-treated borosilicate glass layer with gaseous hydrofluoric acid will leave a thickness of about 5,000 angstroms of glass. In order to completely remove the phosgene glass layer 9 08, another conventional technique is to use a shoe engraving agent with a low selectivity ratio, which is called a low selectivity ratio.

4NTC04006TW.ptd

Page 8 1235431 V. Description of the invention (2) Although the borosilicate glass 9 08 can be completely removed when the etchant is used, it will be in the oxide layer at the same time when the borosilicate glass 9 08 is etched because of the low selection ratio. 9 〇 4 undercut phenomenon, as shown in Figure 9B. Therefore, it is necessary to provide a method for forming a trench-type semiconductor device with a small size and to remove a mask layer after heat treatment. [Summary of the Invention] The present invention is to provide a method for forming a trench-type semiconductor device, which can be applied to a deep trench process with a small size, which can not only retain the good properties of the mask layer, but also completely remove the mask layer after heat treatment. No residue or undercut. The present invention provides a forming method including the following steps: forming a nitrided nitrogen pad on a substrate; partially patterning a structure and a deep trench; and removing a layer of money and a boron-containing dielectric layer photoresist layer as a famous insect Steps: forming a layer; engraving a boron-containing dielectric channel with the name of Tunan, and removing a part of the stop layer; removing the engraved and terminated trench-type semiconductor element to provide a substrate; a shaped layer; Than etching a patterned electrical layer; forming a photoresist layer to cover a deep trench-shaped gadolinium-containing dielectric layer to a deep arsenic-containing layer; forming an oxide layer to cover a patterned boron-containing dielectric layer to remove a portion of the optical layer; As a mask, a boron-containing meso-kun-meso-conform-containing kun-contains an electric layer in one of the predetermined electric layers in the trench; to form an electric layer, the electric layer covers the dielectric layer depth; part and predetermined deep light removal Resistive substrate; electrical layer covering deep trenches to remove cover masks and filling with photoresist patterning degree; layer; shape 1235431

Forming an electric layer to fill a deep trench; and thermally diffusing the ions of the arsenic-containing dielectric layer to form a lower electrode plate on the substrate. [Embodiment] The present invention provides a method for forming a trench-type semiconductor device, and can effectively remove a hard mask for forming a deep trench. Figures 8 through 8 illustrate a method of forming a trench-type semiconductor device according to an embodiment of the invention. In this embodiment, the trench-type semiconductor device 100 is a trench-type capacitor device. This method first provides a substrate 102 and forms a mask structure on the substrate 102. The mask structure includes an oxide layer 104, a pad nitride layer 106, and a patterned dielectric layer 108. In this embodiment, the material of the patterned dielectric layer 108 is borosilicate glass (BSG). Next, the patterned dielectric layer 108 is used as a mask, and a deep trench 11 is carved and generated. Please refer to FIG. 1. Those skilled in the art should know that the substrate 1 02 generally includes an array region 101 and a support region 103, and the deep trenches are formed in the array region 101 of the substrate 102. In addition, those skilled in the art should know that When the dielectric layer 108 is patterned to form the deep trench 110, the patterned dielectric layer 108 is higher in the support region than the array region, but this does not affect the implementation of the present invention. The other details about the array area 101 and the support area 103 are known, and will not be repeated here. As described in the above description, although the conventional technique uses a sintering process to obtain better properties of the patterned dielectric layer 108. In this embodiment, in a DRAM process with a thickness of less than or equal to μm, it is necessary to sinter the borosilicate acid glass (annea 1) at a temperature exceeding 700 ° C to improve the borosilicate acid glass In progress

1235431 V. Description of the invention (4) Process quality of deep trenches. The bran & and 0-1 > f elements are fW w ..., and, after undergoing the high-temperature sintering process, the patterned dielectric layer 108 may be said: ,,, + „Buried + μ 丨 + is more difficult to remove, and cannot be completely removed using a highly selected U method. The etchant shown in Figure 2 is used to etch the patterned medium. 厗] ns ml will use the gate and select the ratio, v ^ 卞Billion, for the electrical layer 108, for example, gaseous hydrofluoric acid (Vapor Hydrofluoric nr ΐ H vum 丄 丄 ga acid ^ acid, VHF) as the etchant. Due to the high selection

The relationship between ratios does not make negative 1 n 1+ L ^ ^ Hi ^ Bl ^ ^ y. Dagger layer 104 produces an undercut image. However, because the sintering process changes the patterned dielectric layer * 1 n Q from g, the electrical layer 108 丨 biomass, and the remaining patterned dielectric layer is formed. 1 As shown in Figure 2, 'Generally in the array area 101 compared to the branch area冓, 冓 / Semiconductor:-There are relatively few dielectric layers 109, but this does not affect the fabrication of subsequent trench semiconductor 70 pieces 100 ^ μμ ^ „U ’s pre-implementation uses a high selection 70 king The patterned dielectric layer 108 is removed, but it is helpful to the back, right, and right. In this case, it is necessary to note the sound of sl and / Wang Xin, 疋, in other embodiments of the present invention, the high selection ratio etching can also be omitted. Yv + = Γ, FIG. 3, forming a conformal arsenic-containing dielectric layer 11 2 to cover the remaining patterning ”s 09 and deep trench 11 〇. In this embodiment, the material of the conformal arsenic-containing dielectric layer 112 is Arsenic SiHcate Glass.

(ASG) As those skilled in the art know, the conformal arsenic-containing dielectric layer 2 is used to form a power-down and buried plate 122, which is shown in FIG. 8 and will be described in more detail below. FIGS. 4 to 5 Shows the step of forming a photoresist layer in some deep trenches. Firstly, a photoresist layer 114 is formed to cover the conformal arsenic-containing dielectric layer 112 and fill the deep trench 11 ′ with reference to FIG. 4. Then, remove a part of the photoresist layer 114 to the deep trench / J 〇 / predetermined degree, as shown in FIG. 5. The photoresist layer 115 in some deep trenches 110 is exposed to a surface 116. The predetermined depth of the surface 11 6 can be according to the manufacturing process

1235431 V. Description of the invention (5) To be adjusted, it must be above the patterned dielectric layer 109 and the gasification layer 104. As shown in FIG. 6, the photoresist layer 115 is used as an etch stop layer, a portion of the arsenic-containing dielectric layer 112, and the patterned dielectric layer 109. According to the method disclosed by Zhao Ming, using the photoresist layer 115 as an etch stop " Figure X, the dielectric layer 109 will be completely removed without oxidizing. ^ Ι〇4θ production 12 phenomenon. With the present invention, the residual edge phenomenon caused by high selection ratio ㈣ can be solved, and the undercut phenomenon caused by low selection ratio etching can be avoided.

7 and 8 illustrate the steps of forming the lower electrode plate 122. First, the photoresist layer 115 is removed. Then use the remaining photoresist layer 丨 7 as the etching stop sound,

A portion of the engraved conformal rhenium-containing dielectric layer 113 is shown in FIG. 7. ^ Lower body Remove the photoresist layer 11 7 and then form a dielectric layer 12 to fill the deep trenches. Finally, the trench-type semiconductor device 100 is heat-treated ', so that the arsenic ions of the arsenic-containing dielectric sound 118 are diffused to the substrate 1002 to form the lower electrode plate 122. In the embodiment, the trench type semiconductor element 00 is a trench type capacitor, and it must be noted here that the remaining processes after the formation of the lower electrode plate 122 are familiar to those skilled in the art, and will not be described here. More details. ... As can be seen from this embodiment, the present invention provides a method for forming a trench-type semiconductor element, which not only uses the photoresist layer used when forming the lower electrode plate to completely remove the borosilicate glass used as a mask. Without adding complicated g steps, it can retain good borosilicate glass properties. Party in accordance with the invention

1235431 V. Description of the invention (6) The method can obtain a good deep trench structure, which can be further applied to finer semiconductor processes. The above embodiments are used to describe the present invention, but the technology of the present invention can still have many modifications and changes. Therefore, the present invention is not limited to the description of the above specific embodiments. The scope of patent application of the present invention is intended to include all such modifications and changes, so as to truly conform to the spirit and scope of the present invention.

4NTC04006TW.ptd Page 13 1235431 Brief description of the drawings [Simplified illustration of the drawings] FIG. 1 shows a method for forming a deep trench according to a specific embodiment of the present invention; FIG. 2 shows a step of etching with a high selectivity; FIG. 3 Figure 4 shows the steps of forming a conformal arsenic-containing oxide layer; Figure 4 shows the steps of forming a photoresist layer to fill a deep trench; Figure 5 shows the steps of removing the photoresist layer to a predetermined depth in a deep trench; Figure 6 shows the steps of removing the patterned dielectric layer Steps; FIG. 7 shows a step of removing a part of the arsenic-containing dielectric layer; FIG. 8 shows a step of forming a lower electrode plate; FIG. 9A shows a conventional method; and FIG. 9B shows another conventional method. Symbol descriptions of icons 100 trench semiconductor device 101 array area 102 substrate 103 support area 104 oxide layer 106 pad nitride layer 108 patterned dielectric layer 109 residual patterned dielectric layer 110 deep trench 112 conformal arsenic-containing dielectric Electrical layer 113 Partially conformal arsenic-containing dielectric layer 114 Photoresistive layer 115 Photoresistive layer 116 Surface 117 Photoresistive layer 118 Thorium-containing dielectric layer 120 Dielectric layer 122 Lower electrode plate 902 Substrate 904 Oxide layer

4NTC04006TW.ptd Page 14 1235431 908 Residual borosilicate glass layer Simple illustration 90 6 Pad nitride layer ΐϋΗ 4NTC04006TW.ptd Page 15

Claims (1)

1235431 6. The scope of the patent application includes: the method of channel semiconductor devices, f a mask structure on the substrate, the mask: f nitrided layer and a patterned dielectric layer; the h-shaped $ 2 dielectric layer is A mask is formed to form a deep trench on the substrate jf. A conformal arsenic-containing dielectric layer covers the mask structure and the deep trench to form a photoresist layer in part of the deep trench; the layer is terminated by the photoresist layer as an etch Layer, removing a portion of the conformal arsenic-containing dielectric layer and the patterned dielectric layer; removing a photoresist layer and a portion of the remaining conformal Kun-containing dielectric layer; forming a dielectric layer Filling the deep trench; and thermally diffusing arsenic ions of the conformal arsenic-containing dielectric layer to form a lower electrode plate on the substrate. 2. The method according to item 1 of the scope of patent application, wherein before the step of forming the conformal arsenic-containing dielectric layer, a method is further included to etch the patterned dielectric layer with a high etching selectivity ratio to remove part of the Patterned dielectric layer. 3. The method according to item 1 of the scope of patent application, wherein the step of forming the photoresist layer comprises: forming the photoresist layer to cover the conformal arsenic-containing dielectric layer and filling the deep trench; and removing a portion of the light Resist the layer to a predetermined depth within the deep trench. 4NTC04006TW.ptd Page 16 1235431 VI. Application for Patent Scope 4 · The method described in item 1 of the patent claim scope, wherein the photoresist layer and the remaining part of the conformal arsenic-containing dielectric layer are removed The method includes: removing a part of the photoresist layer; using the far photoresist layer as an etch stop layer, etching the arsenic-containing dielectric layer; and removing the photoresist layer. 5. The method according to item 1 of the scope of patent application, wherein the material of the patterned dielectric layer comprises Boron Silicate Glass (BSG). The method described in item 1 of the patent application range of ti, wherein the conformal arsenic-containing material includes arsenic silicate glass (hob) 〇7. A method for forming a trench-type semiconductor element provides a substrate; Layer mask structure on the substrate, the mask structure includes an oxide pad nitride layer and a patterned boron-containing dielectric layer; the patterned boron-containing dielectric layer is used as a mask: w 、 番 1 # Qt formed a deep trench early on the base dielectric layer to cover the mask structure and the deep trench rod. A first resistive layer was formed in part of the deep trench; wood, using the photoresistive layer as an etch stop layer, Portions and the patterned boron-containing dielectric layer; * ^ removal of the photoresist layer and the rest of the conformal arsenic-containing dielectric layer:-part of the conformal stone-containing dielectric layer; K35431 6. Scope of patent application Forming a dielectric layer to fill the deep trench; and thermally diffusing exhalation ions of the arsenic-containing dielectric layer to form a buried plate on the substrate. ^ 8. The method described in item 7 of the scope of the patent application, the complex arsenic medium is: * this 乂 into 〃 T Kai > forming the conformal containing = step Li, and further comprising-step to highly pattern boron containing medium Electrical layer 'to remove a portion of the patterning containing: electricity; M 9 · The method described in item 7 of the scope of the patent application, step i includes: forming the first resistive layer channel, the photoresistive layer covering the common layer A dielectric layer is formed and the deep trench is filled to remove a part of the photoresist layer to a predetermined depth in the deep trench. ^ Check the method described in item 7 of the scope of the patent application, which removes Xi # Ρ 曰 r and the remaining conformal basis into 20% > ^, removes the 4 first resistance layer, 仏 s dielectric layer A part of the steps includes: removing part of the photoresist layer; 2f photoresist layer is an etch stop layer, etching the arsenic-containing dielectric layer; and removing the photoresist layer. The method described in item 7 of the patent scope, where the patterning contains. Said materials include Shi Peng Shi Xi glass (B〇r〇n Silicate Glass, Page 18 1235431 VI. Scope of patent application 1 2. The method described in item 7 of the scope of patent application, wherein the material of the conformal arsenic-containing dielectric layer comprises Arsenic Silicate Glass (ASG). 13. A method of forming a trench-type semiconductor device, comprising: providing a substrate; forming an oxide layer to cover the substrate; forming a pad nitride layer to cover the oxide layer; forming a patterned shed dielectric layer cover The hafnium nitride layer; using the patterned boron-containing dielectric layer as a mask, forming a deep trench on the substrate to etch the patterned boron-containing dielectric layer with a high etching selectivity ratio to remove a portion of the patterned Boron dielectric layer; forming a conformal arsenic-containing dielectric layer to cover the mask structure and the deep trench; forming a photoresist layer to cover the conformal arsenic-containing dielectric layer and filling the deep trench; removing part of the photoresist layer To a predetermined depth in the deep trench; using the photoresist layer as an etch stop layer, removing a portion of the conformal arsenic-containing dielectric layer and the patterned boron-containing dielectric layer; removing a portion of the photoresist layer; Using the photoresist layer as the #engraving stop layer, engraving the hafnium-containing dielectric layer; removing the photoresist layer; forming a dielectric layer to fill the deep trench; and thermally diffusing the arsenic ion of the arsenic-containing dielectric layer, To form an electrode plate 4NTC04006TW.ptd Page 19 1235431 4NTC04006TW.ptd Page 20