1234933 九、發明說明： 【發明所屬之技術領域】 本發明係指一種延遲鎖定迴路裝置，尤指一種藉一鎖定偵測 器提示正確鎖定以避免阻塞鎖定及同諧鎖定’並擴大工作範圍的 延遲鎖定迴路裝置。 【先前技術】 數位積體電路的快速發展，舉凡個人電腦、行動電話，甚至 手錶、計算機...等皆屬數位積體電路應用的範#。然而，隨著數 位積體電路高速化、微型化、多I化的發展，—倾雜的數位積 體電路通常包含許多不同的組件’而各組件對於同—參考時脈會 有不同的延遲量。因此，需要一延遲鎖定迴路(Delay-Locked Loop) 以維持各組件的同步。 、心考第1圖’第1圖為習知延遲鎖定迴路裝置1〇之示意圖。 ^遲鎖疋迴路裝置1G包含有—相位侧器12、—電荷栗1心一 加濾波為16、-電壓控制延遲電路18以及一參考相位產生器 >考相位產生裔2〇可產生一參考相位&至電壓控制延遲電 18及相位偵測器12，電壓控制延遲電路18包含有複數個延遲 1234933 單^22 ’每-延遲單元22可受迴路_ __㈣控 Ί翏考相位Fr的延遲量。賴控制延遲電路賴虞迴路 細^輸出之賴Ve將參考她&延遲勤繼制延遲電 最後、、及延遲單兀22輪出為一延遲相位抑至相位侧器 12相位偵測為12可比較參考相位丹與延遲相位抑之相位差以 判斷輕控觀遲電㈣是否正麵參考她叫遲一固定 ,，並根據參考她㈣延遲她Fd之相位差以控制電荷果Μ 是否應增加麵讀出電荷至迴猶妓16。鱗濾波器Μ可將 電荷泵14輸出之電荷轉換為 %卩控制輕控制延遲電路μ 產生之延遲相位Fd她於參考相位㈣延遲量。也就是說，電 麗控制延遲電路I8巾的每—賴單元Μ分縣參考她价延遲 一固定量以由電壓控制延遲電路18的最後一級延遲單元U輸出. 延，相位Fd至相位偵測器12。相位侧器12會根據所需要的延 遲量（例如一個週期）比較參考相位Fr與延遲相位別的相位差。 舉例來說，如果參考相位&與延遲相位Fd的相位差超過所需的 一個週期（360。）’則相位偵測器12驅動電荷泵14增加輸出電荷 至迴路濾波器16;迴路濾波器16將較大的電荷轉換為較大的電壓 Vc並輸入至電壓控制延遲電路18的每一延遲單元22 ;延遲單元 22受到較大的電壓vc驅動對應地產生較小的延遲量以減少延遲 相位Fd與參考相位Fr的相位差。相反的，如果參考相位Fr與延 遲相位Fd的相位差小於所需的一個週期，則相位偵測器12驅動 1234933 電荷泵14減少輸出韻至迴路濾波^ 16以產生騎小的電壓％ 及對應地每-輯單元22較小岐，她^目㈣與參考 相位Fr的相位差得以增加。因此，延遲鎖定迴路裝置⑺可藉一 閉迴=4(如第1計所示）由電壓控制延遲電路18的最後L級 延遲早tg22輸ii{敎岐遲她船现彳，朗步之用。 然而，習知延遲鎖定迴職置1〇會受到同譜鎖定（Ha_ic Lock)及阻塞鎖定（StuckL〇ck)的影響限制。請參考第2圖，第 2圖為延賴定迴路裝置ω _定翻之波科序示意圖。第2 圖中’週期Tr用以表示第！圖之參考相位產生器2〇產生之 她於的-週期，時段T贿及Tmin分別表示延遲相位柯最大 及取小延遲細，·波形絲參考相仙之波形，波形 Wd，max及Wd，mm表示延遲相位Μ最大及最小延遲時的波形。 =貞定是由於習知延遲鎖定迴路裝置1〇之相位偵測器η僅能 她目仙_錢，邮_的相位為 5相位抑與參考相位&間相位差的整數倍時，相位偵測哭12 日舍生_錯誤。舉絲說，纽魏定迴路 ^的延遲相㈣時，相位_〗2就會設細相位= 出電荷至迴路濾、波器16。然而，當延遲相位Fd與表考 r的相位差為1440。時(延遲相位抑延遲叫，相位細 1234933 器12會誤判延遲鎖定迴路裝£ 1〇已正確鎖定（因為144〇。=2測 )。為了避免上述同谐鎖定的問題，習知延遲鎖定迴路裝置1〇必 須將最大延遲範圍設定為Tmax。除此之外，達到鎖定的過程也會 限制了延遲鎖定迴路裝置10的最小延遲範圍為Tmin。簡而言之， 由於同譜鎖定及阻塞鎖定，習知延遲鎖定迴路裝置1〇必須將鎖定 範圍限制在Tr<Tmax<1.5Tr及0.5Tr<Tmin<Ti·。然而，上述的 鎖定範圍關無法滿足許多的需求，況且可能產生錯誤的延 遲鎖定。 為了解決上述的問題，習知技術可外加一鎖定狀態備測器。 請參考第3圖，第3圖為另一習知延遲鎖定迴路裝置3〇之示意圖。 延遲鎖定迴路裝置30包含有一相位偵測器32、一電荷泵^、一 迴路濾波器36、一電壓控制延遲電路38、一參考相位產生器仞 以及一鎖定狀態偵測器46。參考相位產生器4〇可產生一參考相位 Fref至電壓控制延遲電路38及相位_器％ ,·電愿控制延遲電路 38包3有複數個延遲單元42 ’每一延遲單& 42可受迴路濾波器 36輸出之賴Vct控制其延遲參考相位Fref的大小。電塵控制延 遲電路38根據迴路濾波器36輸出之電壓Vct將參考相位&f延 遲後由電壓控制延遲電路38中最後一級延遲單元42輸出為一延 遲相位Fdl至相位偵測器％。鎖定狀態偵測器46可根據參考相位 加f及電壓控制延遲電路对每一級延遲單元42輪出之相位輸 1234933 出一鎖定指示訊號Sp至相位偵測器η。鎖定指示訊號Sp包含有 過早正確或太晚指示訊號以指示相位彳貞測器％延遲時間是否太 f、正確或過長。相位_器32接收到鎖定指示訊號Sp後即判 斷延遲相位Fdl是否正破延遲於一特定範圍之内（以避免同譜鎖定 及阻塞鎖定）’並根據延遲相位Μ及參考相位Μ間的相位差以 閉迴路控制電壓控制延遲電路38輸出之延遲她M。關於鎖定 狀態偵測器46的配置，請繼續參考第4圖。第4圖為習知延遲鎖 定迴路裝置3G中鎖定狀縫靡46之示賴。鎖定狀態偵測器 46包含有-狀態機（StateMachine) 48及一串進式移位暫存器組 50。串進式移位暫存器組5〇包含有複數個〇型正反器（d Flip-Fl〇p>52。電壓控制延遲電路38中每一級延遲單元42各對應 至一 D型正反器52。每一 D型正反器π藉參考相位祕正緣觸 發以對電馳舰遲電路％每—級延遲單元a輸㈣訊號(㈤ 〜CKN)取樣以輸出一序列訊號⑺、Q2 .Qn至狀態機佔。而狀 態機料可根據該細罐Q1、Q2...Qn鼓—真絲以輸出鎖 定指示訊f虎SP至相位_器32。舉例來說，若電屢控制延遲電路 38包含四個延遲單元42 ’則鎖定狀態摘測器私亦包含對應的四 個D型正反n 52，因此可根祕定的輯量（如㈣1週期）得 如第5圖的真值表。第5圖中，第一列L1表示參考相位Fref 遲1週期）之正緣取樣每—延遲私42之輸出所得的結果皆為〇， 也就是說，此時參考她Fref之正緣取樣_訊號皆為低位準亦 1234933 即由最後-級延遲單元42輸出之延遲相位μ與參考相位祕之 延遲1小於該特定的延遲量（1週期）。因此，鎖定指示訊號Sp p可將2巾的過早如奴為i，絲延遲她Fd丨她於該特定 的延遲1 (1棚）為過早以提示相位細器32避免鎖定到錯誤 的相位並具_整電細働之電荷_應控觀遲電路 38之延遲相位Fdi。同理，第5圖令，第二列L2至第四列L4表 喊遲相位Fdl與參考相位Fref之延遲量約等於該特定的延遲量 (1週期）’卿定指示婦υ Sp即可將其巾的正確指示設定為卜 而相位_|| 32難_定麵峨Sp中正確細】之訊號後 即判斷延遲相位Fdl已正確延遲於一特定範圍之内，並根據延遲相 位Μ及參考她Fref間的相位差以閉迴路控制電壓控制延遲電 路38輸出之延遲相位Μ以維持閉迴路44之延遲鎖定。除此之 外’第5圖中，第五列L5至第七列L7表示延遲相位灿與參考 相位Fref之延遲量遠大於該特糾延遲量（ι週期），則鎖定指示 fl戒Sp將其中的太晚指不設定為卜表示延遲相位拙相較於該 特定的延遲量（1週期）為太晚以提示相位偵測器32避免鎖定到 錯誤的她並具以調整電荷泵34輸出之電荷以控制電壓控制延遲 電路38之延遲相位Fdl。 口此’延_定迴路裝置3〇藉鎖定狀態偵測器46彳貞測電壓 控制延遲電路38巾每-延遲單元42之輸出以得到—真值表，並 1234933 根據該真值表提示她偵· π聽敏到錯她以改善同 »白鎖疋及阻基鎖疋的問題。然而’在許多要求高精密度的應用中， 需要精確的延遲相位Fdl，如此—來，必需增加電壓控制延遲電路 =中延遲單元42的數目。而增加的延遲單元42對應地需增加鎖 疋狀悲债測器46中串進式移位暫存器組％的〇型正反器^個 數’因此’勢必造成狀態機你產生一龐大的真值表。此獻的真 絲需要好⑽、統f源，m不同區塊触置皆需延遲鎖 定迴路敍30轉射統整體關步。_言之，為了增加延遲 鎖定迴路裝置30輸出的延遲相位Fdl的精確度，勢必需耗費相當 的系先資源除此之外，當參考相位產生器受到雜訊影塑使炎考 相位Fref中包含劇_訊（施0，或使參考她F咐工作週期 不對稱的情形時（即工作週财較娜）’延遲較迴路褒置 30料生錯誤較。舉例來說，請參考第6圖（及第5圖）。第6 圖為第4圖中·控制延遲電路38僅包含四個延遲單元42且爽 考相位Fr如麵_ 7科每—延· &之輸出爾 先及茶考她Ffef之波獅賴。第6时，訊號㈣表示參考 相位Fref的波形。_，訊號_〜鹽表示第—級至第四級 延遲單元42之輸出訊號的波形。若欲得之延遲相細與參考相 位Fref之延遲量為i週期，職據第$ _魏表可知，當參 相位Fref延遲1週期之丨不绘兩扭办 口 田〆 結果符合第5圖中料元42之糾赠所得之 弟一歹JL2至苐四列L4時’則相位偵測器％可 1234933 W _ ’ t_㈣f的工作週期為 "桃級延遲單元42的輸出訊號明顯不符合所求的延遲】 5 ^ ’但由於參考相位耐的工作週_ 7鞭得參考相位时 L遲1週期之正緣取樣訊號佩4之結果為高位準，因此根據第 ，中^二列U可得此時延遲鎖定迴路裝置％為正確鎖定的狀 =也歧說，當參考她Frcf工作狀於啊時，習知 鎖疋迴路裝置3〇會發生誤判。_，考第7圖 績第6圖的例子但參考相位时之工作 圖软 列L1r^"r_3G%，使得第7圖之情形符合第5圖第— 夕JL1的狀悲，亦即過早 置3〇應為正常鎖定。 一只際上柄習知延遲鎖定迴路裝 ，而言之’習知延遲鎖定迴路裳置1〇無法查知同言皆鎖定及阻 Γ _知㈣敎迴雜置3()__彳上_門 在第 == 單元42的數目又會增加真值表'^加延遲迴路精準度而增加延遲 當參考她之料祕祕資源。再者， 、延遲鎖定迴路装置30會發 1234933 生鎖定錯誤。0此習知延遲鎖定迴路裝置耗㈣統資源但仍無法 正確達到延遲鎖定的要求，更有可㈣為雜訊或其它因素造成系 統同步上的錯誤，嚴重的影響系統的穩定。 【發明内容】 、因此’本發明之主要目的即在於提供-種可防止假鎖 定的延遲鎖定迴路裝置以改善習知技術的缺點。 _ 本發_露-種可防止假鎖定的輯鎖定迴路裝置，其包含 2一電壓控制延遲電路、一相位偵測器、一電荷泵及-鎖定福測 為。该電麗控制延遲電路包含有複數個延遲單元串聯於一序列， 用以根據-參考相位及一控制麵產生一延遲相位。該相位制 器’並聯於該控制延遲電路，用以根據—鎖定指示訊號、該 參考相位及該延遲相位產生一控制訊號。該電荷果，串聯於該相參 位侦測器，用以根據該控制訊號產生該控制健以輸出至該電壓 控制延遲電路。該鎖定偵測器，並聯於該錢控制延遲電路，用 報據該電麵細《路每單元輸出之她輪細歧 * 指不訊號至該她侧n，該鎖定侧器包含有—除二裝置、—、 第—移位暫存器組一第二移位暫存器組及—邏輯模組。、該第;; 移位暫存益組’包含有複數個移位暫存器各對應於該電屡控制延 13 1234933 、£电路中每—延遲單70 ’用以根據—第—除二相位及該電屢控制 延遲電路之每—延遲單元輸出之她以產生—第—序列比較訊 =该第二移位暫存器組，包含有複數個移位暫存器各對應於該 第二位暫存器組中每-移位暫存器，用以根據—第二除二相位 ”序列比較訊號以產生—第二序列比較訊號。該邏_ 組’電連於該第二移位暫存驗，用啸據該第二相比較蘭 產生該鎖定指示訊號。 〜 【實施方式】 #月$考第8圖’第8®為本發明可防止假鎖定的延遲鎖定迴 6〇之轉圖。延綱定迴賴置的包含有—相位偵測器 、—電荷泵64、一迴路滤波器66、一電壓控制延遲電路68、一 ^考相位產生器7G以及—鎖定制器76。電壓控制延遲電路68 匕含有複數個延遲單元則以由最後—級延遲單元η輸出一延 ^相位Fde至相位偵測器62’而延遲鎖定迴路裝置6〇可根據鎖定 輸出之鎖定指示訊號Spl形成軟迴路74;鎖定指示訊 ==有過早訊號SU、正確訊號&及太晚訊號％。_定 ^:的配置，請繼續參考第9圖。如第9圖所示，鎖定债測 ⑽包,有-除頻電路78、—第—移位暫存驗⑽、—第二移 位暫存⑽82及—邏輯模組84。第—餘料驗⑽及第二移 14 1234933 =存器各包含有N個及型正反器86、8 路78可根據參考相位產生器 、 輪出-第一除二相位时2及==7相位Fr叙正緣觸發 一 弟—除二相位Fref_2B ;苴中，第 目位_及第二除二相位Fr❹係為反相。如前所述， 二1目ΓΓ的工作週期不等於5G料，會造成相位鎖定時的 同崎，而本發明利用簡易的除步 Μ & η㈣賴478即可偷參考相位Fref =作週期不對稱的問題。請繼續參考第1G圖，第 =:中除㈣路78的輸人物峨形_;波形财 她祕之波形，_财—2及财—2β分別表示 /于、—相位Fref—2及第二除二相位Fref—2Β的波形。第㈣中， 假設輸入至除頻電路78的參考相位时的工作週期為，由 於除頻電路根據參考相位Fref的正緣觸發以輸出第一除二相 位Fref—2々及第二除二相位Fr(2β，因此可以維持第—除二相位 =f_2及第二除二相位Fref—扭的工作週射為㈣。第9圖中， 弟-移位暫存器組80的第—級〇型正反器防以電塵控制延遲電 路68的第-級延遲單元72輸出的訊號（如第9圖中㈤所示） 對第-除二相位Fref_2進行取樣以輸出一比較訊號队至第一移 純存器組_第：級0型正反器％。而第—移位暫存器組8〇 的弟—級D型正反器86以賴控制延遲電路68的第二級延遲單 元72輪出的訊號（如第9圖中阳所示）對比較訊號QQ進行 取樣以輸出-比較訊號QC2至第—移位暫存器組80的第三級〇 15 1234933 =反•以此類推’第一移位暫存器組80可根據第一除二相 浐及f壓控制延遲電路邰的每-級延遲單元72輸出的訊 :(如弟9圖f CK1〜CK_)所示）輸出一序列比較訊娜1 D型N+1 ^二移位暫存^組82。第二移位暫存11組82之每一級 口口正反器86分別對應於第一移位暫存器組8〇的每一級d型正 二:用M將第二除二相條f—況對每一比較訊號⑹〜心 相輪出—序列比較訊號U〜L_)。舉例來說，第二移 子讀82的第一級D型正反器％以第二除二她㈣邡 =觀號QCl進行取觀輸歧較訊號u。以此娜，第二移 〇Γ存_2可藉第二除二相位时—沈對相比較訊號QCl〜 ^進仃取樣以輸料列比較峨u〜l_至邏輯模組糾。 ㈣歧84根據比較訊號L1〜L_)以輸出鎖定指示訊卿。 、、關=_黯％觸延遲做稱裝置的衫正確鎖定的 枝，請見以下朗。如前所述，#發生阻塞鎖定（驗關 :表丁L遲相位Fde與參考相位祕之延遲量小於W週期。 因此’在第-移位暫存驗8Q中，電壓控制延遲電路68的每一 級延遲早兀72輪出的訊號（如第9圖中αα〜CK(N+1)所示）皆 =取樣第-除二相位Fref_2的正半周（即第一除二相位μ 2的 问位季區段）。在此情形下，於第二移位暫存器組⑽中，第一移 位暫存輪_較訊號qq〜彻第二除二相位 12349331234933 IX. Description of the invention: [Technical field to which the invention belongs] The present invention refers to a delay lock loop device, especially a delay by a lock detector to prompt a correct lock to avoid blocking locks and homophonic locks' and to extend the working range. Lock-in loop device. [Previous technology] The rapid development of digital integrated circuits, such as personal computers, mobile phones, even watches, computers, etc., are all examples of digital integrated circuit applications #. However, with the development of high-speed, miniaturization, and multiple I of digital integrated circuit, —diffused digital integrated circuit usually includes many different components, and each component will have different delays for the same reference clock. . Therefore, a Delay-Locked Loop is required to maintain the synchronization of the components. Figure 1 of the heart test. The first figure is a schematic diagram of the conventional delay lock loop device 10. ^ The late-locking loop device 1G includes-a phase side device 12, a charge pump, a core plus filtering, a voltage control delay circuit 18, and a reference phase generator. The reference phase generator 20 can generate a reference Phase & to voltage-controlled delay circuit 18 and phase detector 12, voltage-controlled delay circuit 18 includes a plurality of delays 1234933 single ^ 22 'each-delay unit 22 can be controlled by the loop _ __㈣ control phase delay Fr . Lai Ve, who controls the delay circuit, and the output of Lai Yu, will refer to her & delay relay system, delay power last, and delay unit 22 rounds out as a delay phase to phase side detector 12 and phase detection to 12 may Compare the phase difference between the reference phase Dan and the delayed phase suppression to determine whether the light-control view delay electricity is positively referenced to her called Chi Yi fixed, and according to the reference her delay the phase difference of her Fd to control whether the charge fruit M should increase the surface Read the charge back to Jewish prostitute 16. The scale filter M can convert the charge output from the charge pump 14 into%, the delay phase Fd generated by the control light control delay circuit μ, and the reference phase by the delay amount. That is to say, each unit of the Lai control delay circuit I8 is divided by the county by referring to her price to delay a fixed amount to be output by the last delay unit U of the voltage control delay circuit 18. Delay, phase Fd to the phase detector 12. The phaser 12 compares the phase difference between the reference phase Fr and the delay phase according to the required delay amount (for example, one cycle). For example, if the phase difference between the reference phase & and the delay phase Fd exceeds a required period (360 °) ', the phase detector 12 drives the charge pump 14 to increase the output charge to the loop filter 16; the loop filter 16 The larger charge is converted into a larger voltage Vc and input to each delay unit 22 of the voltage-controlled delay circuit 18; the delay unit 22 is driven by a larger voltage vc and accordingly generates a smaller delay amount to reduce the delay phase Fd Phase difference from the reference phase Fr. Conversely, if the phase difference between the reference phase Fr and the delay phase Fd is less than a required period, the phase detector 12 drives the 1234933 charge pump 14 to reduce the output rhyme to the loop filter ^ 16 to generate a small voltage% and correspondingly Each unit 22 is smaller, and the phase difference from the reference phase Fr is increased. Therefore, the delay-locked loop device can use a closed loop = 4 (as shown in the first count) to control the final L-level delay of the delay circuit 18 as early as tg22 and lose ii. . However, the conventional delayed lock return to position 10 will be limited by the influence of Ha_ic Lock and Stuck Lock. Please refer to Figure 2. Figure 2 is a schematic diagram of the wave sequence of the fixed loop device ω _ fixed turn. In the second figure, the period Tr is used to indicate the first! The reference phase generator 20 generates the -cycle, the time periods Tb and Tmin represent the maximum delay phase and the minimum delay, respectively, and the waveform wire refers to the phase phase waveform, the waveforms Wd, max, and Wd, mm. Waveforms showing maximum and minimum delay phase M. = The determination is because the phase detector η of the conventional delay-locked loop device 10 can only be used for phase detection. The phase detection is an integer multiple of the phase difference between 5 phase and the reference phase & Test crying on the 12th was born _ wrong. For example, when the delay phase of the Newell-Weining circuit ^ is equal, the phase _ 2 will set the fine phase = the charge to the loop filter and the wave filter 16. However, when the retardation phase Fd and the phase difference r are 1440. Time (delayed phase suppression delay call, phase fine 1234933 device 12 will misjudge that the delay lock loop device is properly locked (because 1440. = 2 test). In order to avoid the problem of homophonic lock mentioned above, the delay lock loop device is known 10. The maximum delay range must be set to Tmax. In addition, the process of reaching the lock will also limit the minimum delay range of the delay lock loop device 10 to Tmin. In short, due to the same spectrum lock and blocking lock, Xi It is known that the delay lock loop device 10 must limit the lock range to Tr < Tmax < 1.5Tr and 0.5Tr < Tmin < Ti ·. However, the above-mentioned lock range cannot satisfy many requirements, and erroneous delay lock may occur. To solve the above problems, the conventional technology can be added with a lock state tester. Please refer to FIG. 3, which is a schematic diagram of another conventional delay lock loop device 30. The delay lock loop device 30 includes a phase detection 32, a charge pump, a loop filter 36, a voltage controlled delay circuit 38, a reference phase generator 仞, and a lock state detector 46. Reference phase The bit generator 40 can generate a reference phase Fref to the voltage control delay circuit 38 and the phase generator%. The electric control delay circuit 38 includes three delay units 42 'each delay unit & 42 can be subject to loop filtering The output of the controller 36 depends on Vct to control the magnitude of its delay reference phase Fref. The electric dust control delay circuit 38 delays the reference phase & f according to the voltage Vct output by the loop filter 36 and is delayed by the last-stage delay unit 42 in the voltage control delay circuit 38. The output is a delay phase Fdl to the phase detector%. The lock state detector 46 can control the delay circuit to output 1234933 for each phase of the 42 units of the delay unit according to the reference phase plus f and the voltage, and output a lock indication signal Sp to the phase. Detector η. The lock indication signal Sp contains a premature or too late indication signal to indicate whether the phase delay% delay time is too f, correct, or too long. The phase detector 32 receives the lock indication signal Sp immediately after Determine whether the delay phase Fdl is breaking within a specific range (to avoid co-spectrum locking and blocking locking) 'and use the phase difference between the delay phase M and the reference phase M to determine The delay of the output of the closed-loop control voltage control delay circuit 38 is M. For the configuration of the lock state detector 46, please continue to refer to FIG. 4. FIG. 4 is a view showing the lock shape 46 in the conventional delay lock loop device 3G. Lai. The lock state detector 46 includes a state machine 48 and a serial shift register group 50. The serial shift register group 50 includes a plurality of 0-type flip-flops. (D Flip-FlOp > 52. Each stage of the delay unit 42 in the voltage-controlled delay circuit 38 corresponds to a D-type flip-flop 52. Each D-type flip-flop π is triggered by the reference phase secret positive edge to power the circuit. The galvanic delay circuit% samples the signal (㈤ ~ CKN) at each stage delay unit a to output a sequence of signals ⑺, Q2, Qn to the state machine. And the state machine can output the lock indication signal to the phaser 32 according to the drums Q1, Q2 ... Qn drum-real silk. For example, if the electrical control delay circuit 38 includes four delay units 42 ′, the locked state detector also includes four corresponding D-type positive and negative n 52, so it can be determined by a fixed amount (such as 1 cycle ) Get the truth table as shown in Figure 5. In Fig. 5, the first column L1 indicates that the reference phase Fref is 1 cycle later). The result obtained by each delay of the positive edge 42 output is 0, that is, at this time, reference to the positive edge of her Fref sample_Signal Both are low levels and 1234933, that is, the delay phase μ and the reference phase secret 1 output by the last-stage delay unit 42 are smaller than the specific delay amount (1 cycle). Therefore, the lock indication signal Sp p can make the two towels too early as a slave i, delaying her Fd 丨 she is too early for this particular delay 1 (1 shed) to prompt the phase finer 32 to avoid locking to the wrong phase It also has _ the charge of the entire electric circuit _ to control the delay phase Fdi of the delay circuit 38. Similarly, in Figure 5, the second column L2 to the fourth column L4 indicate that the delay amount between the delay phase Fdl and the reference phase Fref is approximately equal to the specific delay amount (1 cycle). The correct instruction of the towel is set to bu phase_ || 32 difficult_fixed face E Sp.] Signal, it is judged that the delay phase Fdl has been correctly delayed within a specific range, and according to the delay phase M and reference to her The phase difference between Fref controls the delay phase M output from the delay circuit 38 with the closed-loop control voltage to maintain the delay lock of the closed-loop 44. In addition, in the fifth figure, the fifth column L5 to the seventh column L7 indicate that the delay amount between the delay phase Can and the reference phase Fref is far greater than the special correction delay amount (ι period), and the lock instruction fl or Sp will be included therein. Too late is not set to indicate that the retardation phase is too late compared to the specific delay amount (1 cycle) is too late to prompt the phase detector 32 to avoid locking to the wrong one and to adjust the charge output by the charge pump 34 The delay phase Fdl of the delay circuit 38 is controlled by the control voltage. The delay-determining circuit device 30 obtains a truth table by measuring the output of the delay control circuit 38 by the lock state detector 46 and the voltage control delay circuit 38, and 1234933 prompts her to detect the truth value according to the truth table. · Π heard that she was wrong to improve her problems with the white lock and the base lock. However, in many applications that require high precision, an accurate delay phase Fdl is required, and so-it is necessary to increase the number of voltage-controlled delay circuits = the middle delay unit 42. The added delay unit 42 correspondingly needs to increase the number of type 0 flip-flops of the serial shift register group in the lock-up sad debt detector 46. Therefore, the state machine is bound to cause you to generate a huge Truth table. The silk required for this purpose needs to be good and the source f, and the different blocks of m need to be delayed to lock the entire loop of the 30-transmission system. _In other words, in order to increase the accuracy of the delay phase Fdl output from the delay-locked loop device 30, considerable prior resources must be consumed. In addition, when the reference phase generator is affected by noise, the phase of the test phase Fref is included. Drama_News (Shi 0, or make reference to the situation in which her order of work cycle is asymmetric (that is, work week Choi Na)) 'delay comparison loop setting 30 errors occur. For example, please refer to Figure 6 ( And Figure 5). Figure 6 is Figure 4. The control delay circuit 38 includes only four delay units 42 and the test phase Fr is as shown in the figure. Ffef wave wave. At the 6th time, the signal ㈣ indicates the waveform of the reference phase Fref. _, Signal _ ~ salt indicates the waveform of the output signal of the first to fourth delay units 42. If the delay is desired, The delay amount of the reference phase Fref is the i period. According to the work table $ _Wei, we can see that when the reference phase Fref is delayed by 1 cycle, I will not draw two twists. The result is in line with the younger brother of the material element 42 in Figure 5. One 歹 JL2 to 苐 four columns L4 'then the phase detector% can be 1234933 W _' t_㈣f The output signal of the "Peach-level delay unit 42 obviously does not meet the required delay" 5 ^ 'But due to the working period of the reference phase resistance _ 7 when the reference phase is obtained, the positive-edge sampling signal of L is 1 cycle later 4 The result is a high level. Therefore, according to the second and third columns U, the delay locked loop device% is correctly locked at this time = it is also ambiguous that when referring to her Frcf work status, the lock loop device 3 is known. Misjudgment will occur._, Consider the example in Figure 7 and Figure 6, but refer to the working chart soft line L1r ^ " r_3G% when referring to the phase, so that the situation in Figure 7 is in line with the situation in Figure 5—Even JL1, That is, premature setting of 30 should be a normal lock. One intermediary handle is known for the delay lock circuit device, in terms of 'knowledge delay lock circuit dress 1', it is impossible to check that the same language is locked and blocked Γ _ 知 ㈣敎 回 杂 杂 3 () __ 彳 上 _ 门 在 第 == The number of units 42 will increase the truth table '^ plus the delay loop accuracy and increase the delay when referring to her secret resources. Furthermore,,, Delay-locked loop device 30 will issue a 1234933 lock error. Resources, but still cannot correctly meet the requirements of the delay lock, and it can cause errors in system synchronization due to noise or other factors, which seriously affects the stability of the system. [Summary of the Invention] Therefore, the main purpose of the present invention is to provide -A delay-locked loop device that can prevent false locks to improve the shortcomings of the conventional technology. _ 本 发 _ 露-a latched loop device that can prevent false locks, which includes 2 voltage-controlled delay circuits and a phase detector , A charge pump and -locking fortune measurement. The electric control delay circuit includes a plurality of delay units connected in series in a sequence for generating a delay phase according to the -reference phase and a control plane. The phase controller 'is connected in parallel to the control delay circuit, and is used for generating a control signal according to the -locking indication signal, the reference phase and the delay phase. The charge result is connected in series with the coherent position detector to generate the control key according to the control signal for output to the voltage control delay circuit. The lock detector is connected in parallel to the money control delay circuit, and the electric circuit is used to report the difference between the output and output of each unit of the unit *, which means that no signal is sent to the other side n. The lock side device includes-except two The device, the first shift register group, the second shift register group, and the logic module. 、 第 第 ;; Shift temporary benefit group 'contains a plurality of shift registers each corresponding to the electrical control delay 13 1234933, £ 70 per-delay single in the circuit to be used according to-the first-except two phases And each of the electrical delay control circuit outputs the delay unit output to generate the first serial comparison message = the second shift register group, including a plurality of shift registers each corresponding to the second bit A per-shift register in the register group is used to generate a second sequence comparison signal according to the "second divide by two phase" sequence comparison signal. The logic group is electrically connected to the second shift register. According to the second comparison, the lock indication signal is generated using the second comparison blueprint. ~ [Embodiment] # 月 $ 考 第 8 图 '第 8® This is a rotation diagram of the present invention that can prevent false lock delay lock back to 60. The extensions include: a phase detector, a charge pump 64, a loop filter 66, a voltage control delay circuit 68, a test phase generator 7G, and a lock controller 76. Voltage control delay The circuit 68 includes a plurality of delay units, and a delay is output by the last-stage delay unit η. Bit Fde to the phase detector 62 'and delay the locked loop device 60. A soft loop 74 can be formed according to the lock output signal Spl of the lock output; the lock instruction signal == premature signal SU, correct signal & too late signal% _ 定 ^: For the configuration, please continue to refer to Figure 9. As shown in Figure 9, lock the debt test packet, there are-frequency division circuit 78,-the first shift temporary storage check,-the second shift Temporary memory 82 and-logic module 84. The first-residual material inspection and second shift 14 1234933 = The memory each contains N and type flip-flops 86, 8-way 78 can be based on the reference phase generator, out- In the first division of two phases, the positive edge of 2 and == 7 phases Fr triggers a younger brother—division of two phases Fref_2B; in the above, the first position _ and the second division of two phases Fr❹ are opposite phases. As mentioned earlier, two The working period of 1 mesh ΓΓ is not equal to 5G materials, which will cause Tongzaki when phase locked. However, the present invention can simply steal the reference phase Fref = using the simple removal step M & η㈣lai 478 for the issue of periodic asymmetry. Please continue Referring to Figure 1G, No. =: The character of the loser in the middle of Kushiro 78 is E-shaped; the waveform of her secret treasure, _Cai-2 and Cai-2β represent / The waveforms of the phase Fref-2 and the second division two phase Fref-2B. In the first one, it is assumed that the duty cycle when the reference phase is input to the frequency division circuit 78 is that the frequency division circuit is triggered based on the positive edge of the reference phase Fref. With the output of the first two-phase Fref-2々 and the second two-phase Fr (2β, it is possible to maintain the working cycle of the second-two phase = f_2 and the second two-phase Fref_twist as ㈣. Figure 9 The signal output by the first-stage delay unit 72 of the first-stage 0-type flip-flop of the shift register group 80 to prevent dust control (as shown by ㈤ in FIG. 9) -Divide the two phases Fref_2 and sample to output a comparison signal to the first shifted register group_ #: level 0 flip-flop%. And the first-stage D-type flip-flop 86 of the first-stage shift register group 80 depends on the signal (shown as yang in FIG. 9) from the second-stage delay unit 72 of the control delay circuit 68 for comparison. The signal QQ is sampled to output-compare the signal QC2 to the first-the third stage of the shift register group 80 015 1234933 = inverse • and so on 'The first shift register group 80 can be divided according to the first two phases浐 and f-voltage control delay circuit 邰 The output signal of each-stage delay unit 72: (as shown in Figure 9 f CK1 ~ CK_) output a sequence of comparisons Na 1 D type N + 1 ^ two shift temporary storage ^ Group 82. Each stage of the second shift register group 82 of each stage of the mouth flip-flop 86 corresponds to each stage of the first shift register group 80 of the d-type positive two: use M to divide the second phase bar f-condition For each comparison signal ⑹ ~ Phase phase rotation-sequence comparison signal U ~ L_). For example, the first stage D-type flip-flop% of the second shifter read 82 is divided by the second and the second is equal to the observation number QCl to perform the comparison input signal u. In this way, the second shift 〇Γstore _2 can be used for the second division of the second phase-Shen to the comparison signal QCl ~ ^ into the sampling to compare the feed line to u ~ l_ to the logic module correction. The ambiguity 84 outputs a lock instruction signal according to the comparison signals L1 to L_). 、、 关 = _ 暗 ％ Touch delay is the branch of the shirt which is called the device to lock properly, please see below. As mentioned before, #blocking lock occurs (check off: the delay amount between the delayed phase Fde and the reference phase of the watch L is less than W cycles. Therefore, in the first shift temporary check 8Q, each stage of the voltage control delay circuit 68 The signals delayed by the early 72 rounds (as indicated by αα ~ CK (N + 1) in Fig. 9) are all equal to the positive half cycle of the sampling second division phase Fref_2 (that is, the first quarter division phase μ 2 interrogation season) Section). In this case, in the second shift register group ⑽, the first shift register wheel
Fref—2B的正緣進行取樣。由於延遲晉 崦里過小，因此第二移位暫存哭 組82輸出的比較訊號L1〜L_)皆為高位準。簡言之，當峨 鎖定時，假設參考相位Fref的週期為丁， 二土 且屯壓控制延遲電路68Sampling is performed at the positive edge of Fref-2B. Because the delay time is too small, the comparison signals L1 ~ L_) output by the second shift temporary buffer group 82 are all high. In short, when E is locked, it is assumed that the period of the reference phase Fref is D, Ertu and the voltage control delay circuit 68.
的每一級延遲單元72之延遲時間a TH 才间马Td，可得下列關係式： 當阻塞鎖定時（即Sr=0，Su=l， 5 (NxTd)<0.5T,N>\ 哪(㈣ （式〇 (式2) (式3) QCM(t) = NxTd Q^n+i(0 = +1) x Td 將(Λ^η〇<〇·5Γ的條件代入式卜式2、式 ^ QCX (t) = (-—) χ τ ΝThe delay time a TH of each stage of the delay unit 72 is Td, and the following relationship can be obtained: When the block is locked (that is, Sr = 0, Su = 1, 5 (NxTd) < 0.5T, N > \ which ( ㈣ (Equation 0 (Equation 2) (Equation 3) QCM (t) = NxTd Q ^ n + i (0 = +1) x Td Substituting the condition of (Λ ^ η〇 < 〇 · 5Γ) into Equation 2, ^ QCX (t) = (-—) χ τ Ν
QCN(t) = 〇,5T Q^n+i (Ο = χΤ + 0,5Γ 由於第一除二相位Fref-2之相位為參考相位Fref之二分之 口此參考相位Fref的奇數週期對應的第一除二相位 皆為高位準，而偶數週期對應的第—除二相位卩政2 為低位準。所以： ρς (’)〜(，)==Γ3Γ5Γ，… ⑻丨(’)〜W = 0, / == 2,，4Γ，6Γ 因此，當發生阻塞鎖定時（即Sr=〇，Su=1，s〇=〇)，u 〜L(M+1)皆為高位準。 +例來況右欲求的延遲相位Fde與參考相位肝“之延遲量為 17 1234933 為ί考相位Fref的週期），亦即本發明延遲鎖定迴路裝 置60發生阻塞鎖定時的情形，請參考第u圖。第I!圖為本發明 ^遲鎖疋稱織將參考相位Fref延遲四分之—週期的波形 時序示意圖。由第n圖可知，電壓控制延遲電路68的每一級延 遲單元72輪出的訊號CK1〜CK⑽）取樣第一除二她F欢2的 正半周並輸出比較訊號QkQC，後，第二除二相位㈣―沈再 野比較減QCl〜QC㈣進行取樣所得到的比較訊號u）皆 為高位準（即1) 〇 同理，當正確鎖定時（即Sry，ς 加=0，So=〇)，可得 下列之關係式： 當正確鎖定時（即Sr=l，Su=0，QCN (t) = 〇, 5T Q ^ n + i (0 = χΤ + 0,5Γ Because the phase of the first divided two phase Fref-2 is two-half of the reference phase Fref, the first phase corresponding to the odd period of the reference phase Fref The first and second phases are all high levels, and the first-divided second phase corresponding to the even period is the low level. So: ρς (') ~ (,) == Γ3Γ5Γ, ... ⑻ 丨 (') ~ W = 0 , / == 2 ,, 4Γ, 6Γ Therefore, when blocking lock occurs (that is, Sr = 〇, Su = 1, s〇 = 〇), u ~ L (M + 1) are all high levels. The delay amount of the right desired delay phase Fde and the reference phase liver is 17 (1234933 is the period of the phase Fref), that is, the situation when the blocking and locking of the delay lock loop device 60 of the present invention occurs, please refer to FIG. U. The picture shows the waveform timing diagram of the present invention ^ Delay lock 织 delays the reference phase Fref by a quarter-period. From the nth figure, it can be seen that the signals CK1 ~ CK of each stage of the delay unit 72 of the voltage-controlled delay circuit 68 are round. ) Sample the first half of the second half of her Fen 2 and output the comparison signal QkQC. After that, the second half of the second phase ㈣—Shen Zaiye compares and subtracts QCl ~ QC㈣. The comparison signals u obtained above are all high level (ie 1). Similarly, when locked properly (ie, Sry, ς plus = 0, So = 〇), the following relationship can be obtained: When locked properly ( That is, Sr = l, Su = 0,
°〇-U)^ (NxTd)^T 將(7Vxrc/) = ；r代入式1、式2、式3° 〇-U) ^ (NxTd) ^ T Substitute (7Vxrc /) =; r is substituted into Equation 1, Equation 2, Equation 3
QcN(t) = T Q^n^x (Ο ^ (~) χΤ + τ 瓦 QCN_ 人t) = τ， Q^n+\ (Ο = γ+(—)χ τ ·.·队(r)〜0Q+1(〇 = 1，卜 Γ，3Γ，5Γ，·… 且 26(0 〜2Q+1(〇 = 〇，/ = 2Γ，4Γ，67ν.·· ··· L1 二1，L2=l，···，L(M-1)=1，UH，L_)=〇 18 1234933 考慮時脈抖動（Jitter) 效應 令Tj: £ QCN^"T^(j^)xT±e QcN、t) = τ ± s Q^N^\{t) = (—-) XT Λ-Τ±£ ·· LI一1，L2=l，···，l(M—1):i TM 】 ^ ^ LM-1 〇r 〇5 l(M+1)=〇 因此，當正確鎖定時，Ll〜u 準 UM〜D為南位準，L(M+1)為低位 其次，同諳鎖定（即Si-〇，Su=〇 、 姑—「β〜 〇—1)表示非上述兩種 鎖疋（阻基鎖定及正確鎖定），田 TNOR^ 、 口此只要將訊號Sr與Su做反 或閘（N0R)運鼻即可得So的輪出。 由以上說明可知，本發明延遲 铛定及nn , ㈣贼置60除可避免阻塞 鎖疋外，並可將鎖定範圍擴大為^經，N表示電壓控 制延遲電路68巾延遲單元72 _。因此，當_求-蚊 延遲罝的延遲相位Fde時，電壓控制延遲電路防中每—延遲單元 72會將參考相位Fref延遲,量，並輸出至鎖定姻器μ。 鎖定_器76中的除頻電路78可根據參考相位㈣以輪出第一 除二相位Fref—2至第-移位暫存器組8〇及輸出第二除二相位QcN (t) = TQ ^ n ^ x (0 ^ (~) χΤ + τ watt QCN_ person t) = τ, Q ^ n + \ (0 = γ + (—) χ τ ·. · Team (r) ~ 0Q +1 (〇 = 1, BUΓ, 3Γ, 5Γ, ..., and 26 (0 ~ 2Q + 1 (〇 = 〇, / = 2Γ, 4Γ, 67ν ..... L1 = 2, L2 = 1, ···, L (M-1) = 1, UH, L _) = 〇18 1234933 Considering the clock jitter effect, let Tj: £ QCN ^ " T ^ (j ^) xT ± e QcN, t) = τ ± s Q ^ N ^ \ {t) = (—-) XT Λ-Τ ± £ · · LI-1, L2 = 1, ···, l (M-1): i TM] ^ ^ LM -1 〇r 〇5 l (M + 1) = 〇 Therefore, when properly locked, Ll ~ u quasi UM ~ D is the south level, L (M + 1) is the second low level, and the isochronous lock (that is, Si- 〇, Su = 〇, "-β ~ 〇-1) means the above two kinds of locks (resistance base lock and correct lock), Tian TNOR ^, the only need to reverse the signal Sr and Su brake (N0R) From the above description, we can get the turn out of So. From the above description, it can be seen that in the present invention, in addition to delaying the setting and nn, the thief set 60 can avoid blocking the lock, and can expand the locking range to ^ jing, N means voltage control delay Circuit 68 towel delay unit 72 _. Therefore, when _ seeking-mosquito delay 罝 delay phase F When de, the voltage-controlled delay circuit anti-delay unit 72 delays the reference phase Fref by an amount, and outputs it to the lock device μ. The frequency divider circuit 78 in the lock device 76 may rotate the first phase according to the reference phase. One division two phase Fref-2 to -shift register group 80 and output second division two phase
Fref_2B至弟二移位暫存器組82。由於除頻電路78係根據參考相 位Fref之正緣觸發，因此可以確保第一除二相位制」及第二 19 1234933 工物皆娜。此外，第-移位暫存器 遲單-72於屮/正反$86以電麵制延遲電路68的第一級延 遲早兀72輸出的訊號取樣第一 QG至第-移位暫存器__二n f—2以輸出比較訊號 .σσ 8〇的4二級D型正反器86及第二移位暫 ,S2^ D δ8 〇 ? =的母-級D型正反器88可將第二除二相位π❹對第一移位 86 模組84。戦模組84可根觀較訊號心 L_)㈣早的數學關係式得出訊號、一值 侦測器62進行相位偵測時之依據。相較於習知技術，本發明阳 免阻塞鎖定及赠敎、獻歡翻為(f〜W，並可將工二 圍擴大。除此之外，本發明可避免因參考相位_之工作週期不 對稱，造成鎖定判斷錯誤的問題。其次，當要求精確鎖定而增加 的級數時’本㈣不但*會有儲存真縣所需耗費的 貝"、而’ ^ ’更可因為增加的延遲單元72級數使得鎖定範圍更為 擴大，大大地改善了 f知技術的問題。舉例來說，當電壓控 遲電路68包含啸的延遲單元了2時，本㈣延遲敎迴路裝置 60可提供的鎖絲圍狀25T〜4T ’她於習知延遲敎迴路裝 置3〇的鎖定範圍僅為〇· 5T〜1. 5T。 鎖 再者’由於模組84僅綠倾述的數學_式以輪出 20 1234933 定指示訊號Spl，因此邏輯模組84可藉一簡易的電路實現。請參 考第12圖，第12圖為本發明延遲鎖定迴路裝置6〇中電壓控制延 遲電路68包含六級的延遲單元72時，鎖定偵測器中一較佳實施 例％輯模組90的功能方塊示意圖。邏輯模組9〇包含有一阻塞鎖 疋判斷模阻92、一正確鎖定判斷模阻94及一同諧鎖定邏輯模組 96。阻塞鎖定判斷模阻92包含有三個及閘（and gate) 98、100、 102用以判斷當比較訊號L1〜L6全為1時過早訊號^為丨，反之 則為0。正確鎖定判斷模阻94包含有一及閘1〇4及一反相間（ gate) 106，用以根據比較訊號li〜L4及L6的反相判斷當比較訊 唬L1〜L4皆為1而L6為0 (L5是1或〇不影響結果）時正確訊 號Sr為1 ;反之，若比較訊號L1〜u有一不為i或以不為〇， 則訊號Sr為G。同諧縱邏輯模組96包含有—反或閘⑽_) ’用以根據過早訊號Su及正確訊號Sr以決定當訊號如及訊 號S二全為0時，訊號s。為i ;反之當訊號Su及訊餘不全為〇 時’訊號So為〇。因此，只要依循前述的判斷關係式，亦即當阻 塞鎖定時’比較訊號L1〜卿）全為〇 ;當正確鎖定時，比較訊 號L1〜L(M-丨）全為丨，而比較訊號_ )為q，其中比較訊賴 為1或0並砂響結果（_免時脈抖_影響）；當同諧鎖定時， =非阻塞鎖定且非正確鎖定。如此可類推至當電壓控制延遲電 路68包含有不同級數的延遲單元72的情形。 21 1234933 簡言之，本發明藉鎖定偵測器76中的除頻電路78以參考相 位Fref正緣觸發輸出第-、第二除二相位Fref—2、f晚沈以解 決因雜訊等因素影響而造成參考相位Fref工作週期不對稱的門 題。再者’鎖定偵測器76中第-移位暫存器組8〇的第一㈣型 正反器86以賴控制延遲電路68的第—級延遲單元72之輪出訊 號對第-除二相位Fref—2進行取樣以輸出比較訊號如；第—移 位暫存器組80的第-級D型正反器86後的每一級D型正反器肋 分別以對應的延遲單元72輸出的訊號對前—級D型正反哭卵產 生的比較訊號進行取樣並將比較訊號qg〜QG+i輸入至第°二移位 暫存器組82。第二移位暫存器組82的每—級D型正反器紹再以 第二除二相位Fref—2B分別對比較訊號QG〜QC_進行取樣以輪 出比較訊號L1〜L(M+1)至邏輯模組84。邏輯模組84以簡易的及 閘、反相閘、反或騎組成，並鋪__式而設計以輪出鎖 定指示訊號SP1至相位偵測器62。相位偵測器犯根據鎖定指示訊 號Spl即可維持鎖定迴路之運作。因此，相較於習知技術 明可加大鎖定範圍至〜句，並可避免阻塞鎖定及同·定^ 此之外，可避免因參考相位Fref工作週期不對稱所造成誤判的問 題’亚可防止劇跳雜訊（jitter)所造成的錯誤鎖定。 總而言之’隨著積體電路的高度發展，高速、高精確、多工 的使用已成為基本需求。本發由歡侧騎提供之鎖定提 22 1234933 電路、中各組件達到同步。本發明中鎖定偵測器的除頻 二此項技㈣乐二移位暫存器組皆可由D型正反11所組成。如熟 、了麵齡，D奴反旨並無狀魏祕，只要能以輪 ㈣脈端（GK)找簡輸人D型正反11的D端之 組:採用:輪出結果即可。同理，本發明中侧測器的邏輯模 γ木及閉、反向間、反或閘亦無固定之電路規格，舉凡能 同之數位運算即可。因此，相較於習知技術，本發明可防 止阻基鎖^、同譜鎖定’並提供較大的鎖定範圍；除此之外，對 2訊或電路贼所造成參考她的工俩__的問題亦可 凡王改善。更重要的是，本發明中無需計算真值表，當然也不需 要用來儲存真值表的裝置；即使增加縣控觀遲電路中延遲: 摘個數’也不會造成如習知抆術中過大的資源浪費。因此，本 發明除了改善了習知麟幅塞鎖定、襲b較_題外，亦解 决了鎖絲圍過小關題及參考她之工作週财對稱的問題； 更重要的是，本發明之鎖定制器僅使用簡易之數位電路即可解 決習知技術中之問題，大大地降低電路複雜度並節省系統資源。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明專利之涵 蓋範圍。 【圖式簡單說明】 23 1234933 第1圖為習知延遲鎖物路裝置之示 第2圖為第丨圖之延遲鎖定迴路_ 第3圖為另-習知延_…⑽_疋滅波树序示意圖 卜 延遲鎖疋迴路錢之示意圖。 第4圖為第3圖之延遲鎖定迴路 圖。 Ο中—鎖疋狀㈣測器之示意 第5圖為第4圖中鎖定狀態偵測器的真值表。 巧為第4财每—延料元之触域波 .波形示意圖。 ^矛邳伹之 =8圖為本發财防止假較的延遲較迴喊置之示意圖。 第9圖為第8圖之鎖定摘測器的配置示意圖。 " 第10圖為第9圖之鎖定偵測器中除頻電路的輸人/輪出 意圖。 第11圖為第8圖之延遲鎖定迴路裝置將參考相位延遲四分之一週 期的波形時序示意圖。 刀 σ 第12圖為第8圖之延遲鎖定迴路裝置中邏輯模組—較佳實施例的 功能方塊示意圖。 、 【主要元件符號說明】 10、30、60延遲鎖定迴路裝置 12、32、62 相位偵測器 24 1234933 14、34、64電荷泵 16、36、66迴路濾波器 24、44、74 迴路 48狀態機 92阻塞鎖定判斷模阻 96同諧鎖定邏輯模組 106反相閘 · 18、38、68電壓控制延遲電路 20、40、70參考相位產生器 22、42、72延遲單元 46、76 鎖定狀態偵測器 90邏輯模組 94正確鎖定判斷模阻 98、100、102、104 及閘 108 ·反或閘Fref_2B to the second shift register group 82. Since the frequency division circuit 78 is triggered based on the positive edge of the reference phase Fref, it can ensure the first division by two phase system and the second 19 1234933. In addition, the -th shift register is delayed by -72 at $ / positive and negative $ 86, and the first-stage delay signal of the first stage delay 72 is output from the electrical system delay circuit 68 to sample the first QG to the -shift register_ _Two nf-2 to output a comparison signal. 4 2nd stage D-type flip-flop 86 with σσ 8〇 and the second shift temporarily, S2 ^ D δ8 〇 = = mother-level D-type flip-flop 88 can Divide two phases π❹ to the first shift 86 module 84. The 戦 module 84 can obtain the signal and the basis of the phase detection by the value detector 62 based on the earlier mathematical relationship formula. Compared with the conventional technology, the present invention is free from blocking and locking, giving gifts and offerings to (f ~ W, and can expand the work area. In addition, the present invention can avoid the working cycle due to the reference phase_ Asymmetry, causing the problem of incorrect lock judgment. Secondly, when an exact number of levels is required to increase the lock, not only will the "*" have the cost of storing the true cost of the county, but the "^" may also be due to the increased delay The number of units in 72 makes the locking range wider, which greatly improves the technical problems. For example, when the voltage-controlled delay circuit 68 includes a delay unit of two, the delay delay circuit device 60 can provide Lock wire enclosure 25T ~ 4T 'She ’s lock range of the conventional delay loop circuit device 30 is only 0.5T ~ 1.5T. Lock again' because the module 84 only has the green mathematical formula described in green. 20 1234933 The fixed indication signal Spl, so the logic module 84 can be implemented by a simple circuit. Please refer to FIG. 12, which is a voltage-controlled delay circuit 68 in the delay locked loop device 60 of the present invention, which includes six stages of delay units. A good implementation of the lock detector at 72 For example, the functional block diagram of the% module 90. The logic module 90 includes a blocking lock judgment mode resistor 92, a correct lock judgment mode resistor 94, and a harmonic lock logic module 96. The blocking lock judgment mode resistor 92 includes three And gates 98, 100, and 102 are used to determine that the premature signal ^ is 丨 when the comparison signals L1 to L6 are all 1, otherwise, it is 0. The correct lock judgment mode resistor 94 includes an AND gate 104. And an inverse phase (gate) 106, which is used to judge based on the inversion of the comparison signals li ~ L4 and L6 when the comparison signals L1 ~ L4 are 1 and L6 is 0 (L5 is 1 or 0 does not affect the result) The signal Sr is 1; conversely, if the comparison signal L1 ~ u has a value other than i or a value other than 0, the signal Sr is G. The homo-harmonic longitudinal logic module 96 includes -inverted or gated _) ' The signal Su and the correct signal Sr are used to determine the signal s when the signal such as and the signal S are all 0. Is i; conversely, when the signal Su and the remaining signal are not all 0, the signal So is 0. Therefore, as long as the foregoing judgment relationship is followed, that is, when the block is locked, the 'comparison signals L1 ~ Q) are all 0; when the lock is properly locked, the comparison signals L1 ~ L (M- 丨) are all 丨, and the comparison signal _ ) Is q, where the comparison signal is 1 or 0 and sands the result (_ free from clock jitter _ effect); when the homology locks, = non-blocking lock and incorrect lock. This can be analogized to the case where the voltage-controlled delay circuit 68 includes delay units 72 of different stages. 21 1234933 In short, the present invention uses the frequency divider circuit 78 in the lock detector 76 to trigger the positive edge of the reference phase Fref to output the first and second divided phases Fref-2 and f late sinking to resolve factors such as noise. Influence caused by the asymmetry of the reference phase Fref duty cycle. Furthermore, the first 正 -type flip-flop 86 of the -shift register group 80 in the lock detector 76 depends on the output signal of the first-stage delay unit 72 of the first-stage delay unit 72 to the second-divide two Phase Fref-2 is sampled to output a comparison signal such as; each stage of the D-type flip-flop ribs after the first-stage D-type flip-flop 86 of the first-shift register group 80 is output by the corresponding delay unit 72. The signal samples the comparison signal generated by the front-grade D-type positive and negative crying eggs and inputs the comparison signals qg ~ QG + i to the second shift register group 82. Each D-type flip-flop of the second shift register group 82 then samples the comparison signals QG ~ QC_ with the second division two phase Fref-2B to rotate the comparison signals L1 ~ L (M + 1) Go to logic module 84. The logic module 84 is composed of a simple AND brake, reverse brake, reverse or ride, and is arranged in a __ style to turn out the lock indication signal SP1 to the phase detector 62. The phase detector can maintain the operation of the lock loop according to the lock indication signal Spl. Therefore, compared with the conventional technology, it can increase the lock range to ~ sentence, and can avoid blocking and locking. Besides, it can avoid the problem of misjudgment caused by the asymmetry of the reference phase Fref duty cycle. Prevent false locks caused by jitter. All in all, with the rapid development of integrated circuits, the use of high speed, high accuracy, and multiplexing has become a basic requirement. The locks provided by Huan side riding 22 1234933 The circuit and the components in the lock are synchronized. In the present invention, the frequency-resolving unit 2 of the lock detector can be composed of a D-type positive and negative 11 register. If you are mature and mature, D slaves will not have any secrets, as long as you can find the D end of the D-type positive and negative 11 by using the GK pulse: use: turn out the results. In the same way, there is no fixed circuit specification for the logic module γ of the side tester in the present invention, and the closed, reversed, reversed or gated circuits, and any digital operation can be used. Therefore, compared with the conventional technology, the present invention can prevent the base lock, the same spectrum lock, and provide a larger lock range; in addition, the reference to her by the two news or circuit thieves __ The problem can also be improved by the king. More importantly, the present invention does not need to calculate the truth table, and of course, it does not need a device for storing the truth table; even if the delay in the county-controlled watch circuit is increased: the number of picks will not cause the problem Excessive waste of resources. Therefore, the present invention not only improves the problem of the lock of the known lintel plug, but also solves the problems of the lock wire around the small problem and the symmetry of her work weekly wealth; more importantly, the lock controller of the present invention Using only simple digital circuits can solve the problems in the conventional technology, greatly reducing the complexity of the circuit and saving system resources. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the invention patent. [Schematic description] 23 1234933 Figure 1 shows the conventional delay lock device. Figure 2 is the delay lock loop of Figure 丨 Figure _3 is another-conventional extension _... ⑽_ 疋 extinguish wave tree The sequence diagram is a schematic diagram of the delay lock circuit. Figure 4 is the delay lock loop diagram of Figure 3. 〇 中 —Schematic diagram of the lock-shaped detector Figure 5 is the truth table of the locked state detector in Figure 4. Coincidentally, it is the 4th wave of each element—extended element touch wave waveform. ^ Mao Zhizhi = 8 This is a schematic diagram of the delay in making a fortune to prevent fake comparisons. FIG. 9 is a configuration diagram of the lock picker of FIG. 8. " Figure 10 is the input / output intention of the frequency divider circuit in the lock detector of Figure 9. Fig. 11 is a waveform timing diagram of the delay locked loop device of Fig. 8 delaying the reference phase by a quarter of a cycle. Knife σ Figure 12 is a functional block diagram of the logic module in the delay locked loop device of Figure 8-the preferred embodiment. [Description of main component symbols] 10, 30, 60 Delay-locked loop devices 12, 32, 62 Phase detector 24 1234933 14, 34, 64 Charge pump 16, 36, 66 Loop filters 24, 44, 74 Loop 48 status Machine 92 blocking lock judgment mode resistance 96 homo-locking logic module 106 reverse gate 18, 38, 68 voltage control delay circuit 20, 40, 70 reference phase generator 22, 42, 72 delay unit 46, 76 lock state detection Detector 90 logic module 94 is correctly locked to determine the mode resistance 98, 100, 102, 104 and gate 108.
Fd、Fr、Fref、Fd卜 Fde相位 Vc、Vet電壓 Sp、Sp卜Su、So、Sr指示訊號 CK1 〜CK(N+1)、Q1 〜QN、QCcQQsm、LI〜L(M+1)訊號 Wr、Wd，max、Wd，min、Wref、Wckl 〜Wck4、Wref—2、Wref—2B 波形Fd, Fr, Fref, Fd and Fde phase Vc, Vet voltage Sp, Sp and Su, So, and Sr indicate signals CK1 to CK (N + 1), Q1 to QN, QCcQQsm, and LI to L (M + 1) signals Wr , Wd, max, Wd, min, Wref, Wckl ~ Wck4, Wref-2, Wref-2B waveforms
Tr、Tmax、Tmin 時段 QC2至第一移位暫存器組80的第三級D型正反器86。以此類推， 第一移位暫存器組80可根據第一除二相位Fref_2及電壓控制延遲 電路68的每一級延遲單元72輸出的訊號（如第9圖中CK1〜 CK(N+1)所示）輸出一序列比較訊號QCl〜QC顧至第二移位暫存 器組82。第二移位暫存器組82之每一級D型正反器86分別對應 25 1234933 於第一移位暫Tr, Tmax, Tmin periods QC2 to the third-stage D-type flip-flop 86 of the first shift register group 80. By analogy, the first shift register group 80 can output signals according to the first divide-by-two phase Fref_2 and each stage of the delay unit 72 of the voltage control delay circuit 68 (such as CK1 ~ CK (N + 1) in FIG. 9 (Shown) outputs a sequence of comparison signals QCl ~ QC to the second shift register group 82. Each stage D-type flip-flop 86 of the second shift register group 82 corresponds to 25 1234933 respectively in the first shift register
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