TWI234852B - Inspection method of flip-chip bonding surface by applying atomic force microscope (AFM) - Google Patents

Inspection method of flip-chip bonding surface by applying atomic force microscope (AFM) Download PDF

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TWI234852B
TWI234852B TW093111029A TW93111029A TWI234852B TW I234852 B TWI234852 B TW I234852B TW 093111029 A TW093111029 A TW 093111029A TW 93111029 A TW93111029 A TW 93111029A TW I234852 B TWI234852 B TW I234852B
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Taiwan
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flip
chip
afm
atomic force
force microscope
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TW093111029A
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Chinese (zh)
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TW200536064A (en
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Jeng-Gung Du
Hung-Kai Chen
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Univ Tsinghua
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Sampling And Sample Adjustment (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)

Abstract

The present invention relates to one kind of inspection method of flip-chip bonding surface by applying atomic force microscope (AFM), which mainly obtains observation results of atomic force microscope with higher image contrast ratio. The present invention utilizes the technique of ion-beam etch to prepare the flip chip (FC) specimen, wherein while adjusting etch time and ion beam energy, incorporated with a tilting angle, the deformed portion between the solder ball and the pad caused by grinding and polishing can be removed to obtain better morphology in the specimen for the Ni-layer and Cu-layer of the pad, which in turn optimizes analyses of the atomic force microscope (AFM).

Description

1234852 五、發明說明(1) " 【發明所屬之技術領域】 人本發明係有關一種應用於原子力顯微鏡(AFM)之覆晶接 口面檢測方法,特別是一種應用於製備覆晶試片使獲得更 佳之觀察效果。 【先前技術】 傳統的封裝是單顆1C進行封裝,需要導線架(Lead rame)或是基板(Substrate),黏晶(Die Attach)、打線 (Wire Bond)、灌膜(M〇lding)、成型(Τγ^ and 等製 ,封裝後的1 C大小是晶片(Ch i p )的好幾倍。覆晶是在j c 曰曰片上叹有銅(cu)或銲錫之凸塊(Bump),以做為與焊接j 之用。覆晶在裝配於PCB基板時,為將晶片的電路面朝下, 因此稱為覆晶。 覆晶接合(FC)又稱為C4接合(C〇ntr〇lled c〇Uapse hip Connection),其係由美國ibm公司所開發,它屬於平 技姓Array)的接合,而非如打線接合(wire bond)及 捲帶式晶粒接合技術(TAB)僅能提供周列式(peripherai 的接合,因此覆晶接合能應用於極高密度的構裝連 $製程,在未來的構裝連線與接合技術中,覆晶接合的技 術預期將有極高比例的應用。 日覆晶接合的基本原理,是先在1(:晶片的金屬墊上生成〇 塊(Solder Bump),將κ晶片置放到構裝基板上並完 成鋅錫凸塊與基板之焊墊(pad)對位之後,利用迴流( 熱曰處1里配合鲜錫㈣時之表面張力效應使銲錫成球 並元成I C晶片與構裝基板之接合。 12348521234852 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for detecting a flip-chip interface surface applied to an atomic force microscope (AFM), and particularly to a method for preparing a flip-chip test piece. Better observation. [Previous technology] Traditional packaging is a single 1C package, which requires a lead frame or substrate, die attach, wire bonding, molding, and molding. (Tγ ^ and other systems, the size of 1 C after packaging is several times the chip (Ch ip). The flip chip is sighed with copper (cu) or solder bumps (Bump) on the jc chip. It is used for soldering j. The flip-chip is called flip-chip when it is mounted on the PCB substrate so that the circuit side of the wafer faces downward. The flip-chip bonding (FC) is also called C4 bonding (C〇ntr〇lled c〇Uapse hip) Connection), which was developed by the American IBM Corporation, and belongs to the Pingji Array) bonding, instead of such as wire bonding and tape-and-die bonding technology (TAB) can only provide peripheral type (peripherai Therefore, flip-chip bonding can be applied to extremely high-density fabrication and fabrication processes, and in the future construction wiring and bonding technology, flip-chip bonding technology is expected to have a very high proportion of applications. The basic principle is to first generate 0 (Solder Bump) on 1 (: metal pad of the wafer, After the κ wafer is placed on the structured substrate and the zinc-tin bumps are aligned with the pads of the substrate, the surface tension effect when reflowing (1 mile with fresh tin tin) is used to make the solder balls merge. Form the joint of IC chip and the structure substrate.

一銲錫的種類很多,常見的種類為高熔點的95%鉛-5%錫 合金,或低熔點的51%銦-32. 5%鉍-16.5%錫、63%鉛-37%錫 、50%鉛-50%銦合金。銲錫凸塊的製作方法為,先在ic晶片 表面鍍上玻璃保護層以提供密封保護並防止銲錫的任咅潤 溼,在金屬墊位置上開出導孔後再濺鍍上如鉻—銅—金^之 多層金屬薄膜(通稱為Under Bump Metallurgy ; UBM),以 提供黏著、擴散障礙、增進銲錫潤濕與防止氧化等功能, 後再以蒸鍍(Evaporation)、沉浸(Dipping)或超音波點 銲(Ultrasonic Soldering)的技術將1〇〇至125 "爪厚的鉍一 錫合金(Pb-Sn)鍍上,在後續的接合熱處理過程中,銲°錫 熔融時之表面張力效應將使銲錫層轉變成球形的銲錫凸塊 。使用覆晶接合的構裝基板接墊上相對地也需鍍上多層 屬薄層(稱為Top Surface Metallurgy ; TSM),以利錄總几 塊接合時的潤濕。 錫凸 在電子構裝的可靠度分析當中,有絕大部分便是 在焊接點的部分。因為,當錫球與基板結合之後,由 同物質間化學勢(Chemical potential )的差別,造虑= 質原子的移動,也就是所謂的擴散行為,因此,藉著= 反應的關係形成了介金屬化合物(Intermetal丨ic 予 compound ; IMC )。此一介金屬化合物的生成,會因埶 的關係,有著厚度、種類、組成及性質上的變化,而、、^ ^理 在電子構裝的過程中,常常會有焊接點破壞、斷裂的=成 。因此,如何建立一個有效的試片準備方式來獲得主=為 原子力顯微鏡(AFM)照片,便是此類分析工作中頗為θ斤的 垔要的There are many types of solder. The common types are 95% lead-5% tin alloy with high melting point, or 51% indium-32.5% bismuth-16.5% tin, 63% lead-37% tin, 50% with low melting point. Lead -50% indium alloy. The method of manufacturing solder bumps is to first coat a glass protective layer on the surface of the IC chip to provide sealing protection and prevent any solder wetting. After opening a pilot hole on the metal pad position, then sputter plating such as chromium-copper-gold ^ Multi-layer metal film (commonly known as Under Bump Metallurgy; UBM) to provide adhesion, diffusion barriers, enhance solder wetting and prevent oxidation, etc., followed by evaporation, immersion (dipping) or ultrasonic spot welding ( (Ultrasonic Soldering) technology is used to plate the bismuth-tin alloy (Pb-Sn) with a thickness of 100 to 125. In the subsequent bonding heat treatment process, the surface tension effect when the solder melts will change the solder layer. Spherical solder bumps. The flip-chip-bonded structural substrate pads also need to be plated with multiple layers of thin metal (referred to as Top Surface Metallurgy; TSM), in order to record the wettability of several pieces during bonding. Tin bumps In the reliability analysis of electronic components, most of them are at the solder joints. Because, after the solder ball is combined with the substrate, the difference between the chemical potentials of the same substance is caused by the movement of the mass atoms, which is the so-called diffusion behavior. Therefore, the intermetallic metal is formed by the relationship of the reaction. Compound (Intermetal 丨 ic compound); The formation of this intermetallic compound will vary in thickness, kind, composition, and properties due to the relationship between 埶 and ^. In the process of electronic assembly, solder joints often break and break. . Therefore, how to establish an effective way to prepare test strips to obtain the main = for atomic force microscope (AFM) photos is the most important thing in this kind of analysis work.

12348521234852

第7頁 1234852 、發明說明(4) ^ 可增加照片的清晰度。傳統的方 片進行蝕刻除去試片上的變形層’為利用化學溶液來對試 來蝕刻特定的試片,由於化學蝕刻,=用特定的化學溶液 法,故必須依材質的種類和所欲二=二,選擇性的餘刻方 化學溶液蝕刻,亦即是特定的 ==、、、。構而使用不同的 組成才具有蝕刻的效用。因此利用舳=^疋的材料或 種元素或相的試片時,合造成开 子 x來處理含有多 題。除此之外,化學溶;: = 勻的問 的傷害與污染均是其他應受重視的課題。【及其對於環境 又在中華民國專利公告第329020號的「薄腺带辦 電子顯微鏡試片製備技術…,則提出了—種: (Grading)與拋光(Polishing)技術製備電子顯微鏡二 方法,但是一般的試片在經過切割與研磨拋光之後合 形層的產生而影響原子力顯微鏡(AFM)的觀察。 曰 【發明内容】 本發明的主要目的在提供一種應用於原子力顯微鏡( A F Μ)之覆晶接合面檢測方法。 另一目的係在解決傳統利用化學餘刻方式製備原子力 顯微鏡(AFM)試片的問題。 再一目的係在解決一般的試片在經過切割與研磨抛光 之後產生的變形層對原子力顯微鏡(AFM)觀察之影響。 本發明所揭露的方法是使用離子束钱刻之方法,對覆 晶試片進行表面處理,其主要係利用離子束能量與钱刻時 間這兩個條件的交互配合,再加上一特定的試片與離子束Page 7 1234852, Description of Invention (4) ^ It can increase the sharpness of photos. The traditional square piece is etched to remove the deformed layer on the test piece. To use a chemical solution to etch a specific test piece, since chemical etching = uses a specific chemical solution method, it must be determined according to the type of material and desired. Second, the selective chemical solution etching of the engraved square, that is, specific == ,,,. The structure has the effect of etching only when different compositions are used. Therefore, when using 舳 = ^ 疋 material or a kind of element or phase of the test piece, the result of the opening x is used to deal with multiple problems. In addition, chemical dissolution :: = uniform problems of injury and pollution are other issues that should be paid attention to. [It is also related to the environment in the "Glass gland strip office electron microscope test strip preparation technology ...", which proposes a kind of: (Grading) and polishing (Polishing) two methods to prepare an electron microscope, but The generation of conformal layers after cutting, grinding and polishing of general test pieces affects the observation of atomic force microscope (AFM). [Summary of the Invention] The main object of the present invention is to provide a flip chip for atomic force microscope (AF Μ). The method of detecting the joint surface. Another purpose is to solve the problem of preparing atomic force microscope (AFM) test strips by traditional chemical method. Another purpose is to solve the deformation layer pair produced by cutting, grinding and polishing of general test strips. Effect of Atomic Force Microscopy (AFM) Observation. The method disclosed in the present invention is to use ion beam money engraving to surface-treat a flip-chip test piece, which mainly uses the interaction between the ion beam energy and money engraving time. Fit, plus a specific test strip and ion beam

第8頁 1234852 五、發明說明(5) 的炎角,以便對試片的表面進行處理。其具 點: 〜成項優 丨.離子束蝕刻屬於非選擇性蝕刻,故適 或多相的試片。 夕7Μ才料 2. 由於可以調整離子束的能量、電流大小的 類,因此適用於低蝕刻率的精密蝕刻,這樣對試t的種 傷害亦會減低。 乂成的 3. 製程參數的控制較為準確與便利,而試片的 現性亦高。如是,亦可作小面積的蝕刻,故可針對 特定區域進行蝕刻。 ^片的 【實施方式】 有關本發明的詳細技術内容及其較佳實施例, 圖式說明如次。 曰 :先請參閱「第1圖」所示,在這裡僅以覆晶接合技術 中的單一錫球(solder bump,或稱銲料凸塊)及其相接之金 屬墊和銲墊的接合構造為例。由圖中的構造可以瞭解,一 般在晶片(Si chip)10之金屬墊(如銅墊,Cu pad)2〇的表面 具有一層氮化物(Nitride)的介電保護層3〇,並留有一 與金屬㈣相通的接觸窗開·ntaefHQle),留在有這個用: 觸窗開口處將鍍上多層金屬薄層(稱為T〇p Surface Metal lurgy,TSM),以利銲錫凸塊接合時的潤濕,此一多 層金屬薄層包括:利用物理氣相沈積(physical Vap〇r Deposition)法依次生成鈦(Ti)4〇和銅((:11)5〇的金屬層,接 著鑛上錄(Ni)層60 ’然後生成一錫球(s〇ider ball)70,Page 8 1234852 V. Inflammation angle of description (5) in order to treat the surface of the test piece. It has the following advantages: ~ Excellent item. Ion beam etching belongs to non-selective etching, so it is suitable for multi-phase test pieces. Even at 7M 2. Since the energy and current of the ion beam can be adjusted, it is suitable for precision etching with low etching rate, so that the damage to the test t will also be reduced. The completed 3. Control of process parameters is more accurate and convenient, and the test piece has high reproducibility. If so, it can also be etched in a small area, so it can be etched for a specific area. [Embodiments] The detailed technical content of the present invention and its preferred embodiments are illustrated in the drawings below. Said: Please refer to the "Figure 1" first, here only the single solder ball (solder bump, or solder bump) in the flip-chip bonding technology and the bonding structure of the metal pad and solder pad connected to it example. It can be understood from the structure in the figure that, generally, a surface of a metal pad (such as a copper pad, Cu pad) 2 of a silicon chip 10 has a layer of nitride (Nitride) dielectric protection layer 30, and one with The contact window of the metal ㈣ communicates with ntaefHQle), which is used for this purpose: The opening of the contact window will be plated with a multi-layer metal thin layer (called Top Surface Metal Lurgy, TSM) to facilitate the solder bump bonding process. Wet, this multi-layer metal thin layer includes: using a physical vapor deposition (physical vapor deposition) method to sequentially generate a metal layer of titanium (Ti) 4o and copper ((: 11) 50), followed by recording (Ni ) Layer 60 'then generates a solder ball 70,

第9頁 1234852 五、發明說明(6) 至此即完成所謂的銲料凸塊。 在基板(PCB chip)80的表面則生成盥 對應可供銲料潤溼附著的銲墊(如銅墊,^料凸塊相 位於銲墊90之表面的另一銻(Ni)層91。而覆ΒΓ接以及 係將翻轉之晶片10的銲料.凸塊對準基板8〇上的曰:::方式 迴銲(Ref low)的方法使其接合, $90,以 。 I疋所明的覆晶接合技術 由於材料的焊點往往會因迴焊(Refl〇w)時 介金屬化合物(lnter託tallic c〇mp〇und ; IMcf) j 的 破壞的所在,因此如何精確的觀察此一部份的顯微結構,,'、 以瞭解此介金屬化合物的生成機制’進而分析其組成、 態及結構,對I C晶片的電性表現及構裝可靠度的影響。因 此,如何建立一個有效的試片準備方式來獲得清晰的原子 力顯微鏡(AFM)照片’便是此類分析工作中頗為重要的的課 題。 本發明的技術基本上包括兩個階段的步驟,分別為: 1 ·切割取得如「第1圖」之覆晶接合結構之試片丨〇 0, 並經過粗略的研磨以及拋光,其厚度介於1〜2mm的覆晶試 片。 ( 2·利用離子束14刻(ion beam etch)之方式,對經過前 一步驟研磨拋光的覆晶試片1 〇 0,控制離子數的能量與蝕刻 的時間,配合入射離子束1 0 1與試片1 0 0的之入射角度0 (如 「第2圖」所示),其中該入射角度係為25度至35度,但最 佳角度為3 0度,來去除錫球及相接金屬墊間,因研磨拋光Page 9 1234852 V. Description of the invention (6) This completes the so-called solder bump. On the surface of the PCB chip 80, a solder pad (such as a copper pad, which has a bump phase on the surface of the solder pad 90) corresponding to a solder pad (such as a copper pad) is formed. ΒΓ bonding and the soldering of the flipped wafer 10. The bumps are aligned on the substrate 8: ::: Reflow (Ref low) method to bond them, $ 90. Technology Because the solder joints of materials are often damaged by intermetallic compounds (lnter tray metalcmpund; IMcf) j during reflow (Refl0w), how to accurately observe the micrograph of this part Structure, ', to understand the formation mechanism of this intermetallic compound', and then analyze its composition, state and structure, the impact on the electrical performance and reliability of the IC chip. Therefore, how to establish an effective way to prepare the test piece Obtaining clear AFM photos' is a very important subject in this kind of analysis. The technology of the present invention basically includes two steps, which are: 1 Test piece of flip-chip bonding structure 丨 〇 0 , And after rough grinding and polishing, the thickness of the chip-on-chip test piece is between 1 ~ 2mm. (2 · Using the ion beam 14 etch (ion beam etch) way, the chip-on-chip test piece that has been ground and polished in the previous step 1 〇0, control the energy of the number of ions and the etching time, and cooperate with the incident angle 0 of the incident ion beam 1 0 and the test piece 1 0 0 (as shown in the "Figure 2"), where the incident angle is 25 Degrees to 35 degrees, but the optimal angle is 30 degrees to remove the solder balls and the adjacent metal pads, due to grinding and polishing

第10頁 1234852 五、發明說明(7) 所產生的變形部分,使得其所生成的介金屬化合物,及各 金屬層的變化情形進行表面處理,以獲得所需之原子力顯 微鏡的試片。 本發明利用離子束餘刻(i〇n beam etch)之方式,其主 要係控制離子數的能量與蝕刻的時間,配合入射離子束丨〇 i (例如採用氬(Ar )為離子源的反應氣體)與試片丨〇 〇的之 入射角度Θ的模式’對試片的表面進行處理;以除去錫球( solder ball)及其相接之金屬墊(pad)間因為研磨拋光所產 生的變形部份’特別是對於錫球(s 〇 1 d e r b a 1 1 )及其相接之 金屬墊(pad)間所生成的介金屬化合物可以獲得較利於原子《 力顯微鏡分析的試片形態。茲以下面的實例作為說明。 首先叫先參閱「第3圖」所示,係為試片經過一般的 研磨、拋光製成後所的AFM影像。圖中各層的成分由上而下 分別為錫球70、介金屬化合物1〇2,鎳層91,銲墊9〇之銅層 ,由圖可看出,雖然可以大略分別各層之間的差異,但由 2 =磨所造成的變形卻讓鎳層9丨與銲墊9〇之影像變的較不 >月楚,無法很明顯的看出鎳層91與銲墊9〇之鋼層有何差 。因此,便需要將試片做更進一步的處理。 、 為2。0本/Λ例所設定的條件為,固定離子束的入射電流量I =〇微女培(uA),對研磨拋光後的覆晶試片i〇 ^ 為30度的模式,分別以4、5、6、7 :射角度Θ 量來森擊試片3分鐘,然後經由原子力顯::=):能 FM影像。其各別所得的ΑρΜ影像分別為「第45其Page 10 1234852 V. Description of the invention (7) The deformed part caused surface treatment of the intermetallic compound and the change of each metal layer to obtain the required test piece of atomic force microscope. The present invention uses an ion beam etch method, which mainly controls the energy of the number of ions and the etching time, and cooperates with the incident ion beam. 〇i (for example, using argon (Ar) as the reaction gas of the ion source) ) The pattern of the incident angle Θ with the test piece 丨 〇〇 'is to treat the surface of the test piece; to remove the deformed part caused by grinding and polishing between the solder ball and its adjoining metal pad Part 'especially for intermetallic compounds generated between solder balls (s 〇1 derba 1 1) and their adjoining metal pads (pads) can obtain the shape of the test piece that is more favorable for atomic force microscope analysis. The following example is given as an illustration. First of all, please refer to "Figure 3", which is the AFM image of the test piece after general grinding and polishing. The composition of each layer in the figure is the copper layer of the tin ball 70, the intermetallic compound 102, the nickel layer 91, and the pad 90, from the top to the bottom. As can be seen from the figure, although the differences between the layers can be roughly compared However, the deformation caused by 2 = grinding makes the image of the nickel layer 9 丨 and the pad 9〇 less> Yue Chu, it is not obvious what the nickel layer 91 and the steel layer of the pad 90 are. difference. Therefore, the test piece needs to be further processed. , Is set to 2.0. The conditions set in this example are: a mode in which the incident current of the fixed ion beam is I = 0 micro-female (uA), and the mode for polishing the flip-chip test piece i0 ^ is 30 degrees, Use 4, 5, 6, 7 respectively to hit the test piece for 3 minutes with the shooting angle Θ, and then show via atomic force :: =): can FM image. The respective AρM images obtained are "45th

1234852 五、發明說明(8) 〜 7A、8A圖」,「第6B、7B、8B圖」分別為「第μ、7A、8A 圖」鎳層與銲墊之銅層的AFM放大影像。 經由上述的触刻過程處理試片之後,可以清楚的觀察 到錄層9 1與銲墊90之銅層的晶粒形狀及排列的方式。對鎳 層9 1來說,可以明顯的分辨出其柱狀晶的成長型態,另外 更可發現,分別在靠近銲墊90之銅層及介金屬化合物1〇2層 的錄’具有不同的晶粒大小,靠近銲墊9 〇的鎳,其晶粒較 小,而靠近介金屬化合物102層的鎳則具有較大的晶粒尺寸 ,另外,對於銲墊9 0之銅層來說,也可以清楚的看出其晶 粒的形狀。因此,對於藉由觀察介金屬化合物1〇2生成機㈤ 的來做為電子構裝可靠度分析的依據將有極大的助益。 總結來說,由上述不同蝕刻條件所獲得的AFM影像可得 知,其最佳的AFM掃描影像,條件的設定可為離子束的入 應選擇7keV ’入射電流為2〇〇微安培,且將試片傾 度角。 一當然以上的例子’ €用以說明本發明的較佳實施例之 :時^於::2 =條件參數,包⑨:離子束能量,蚀 j覆晶接合所使用之鲜料凸塊及其相接之金屬塾“::: 上述僅為本發明之較佳實施例而已 Γ實施之範®,即凡依本發明申請專利範圍 變化與修飾,本發明專利範圍所涵蓋。圍所做的均專1234852 V. Description of the invention (8) ~ 7A, 8A picture "," Figures 6B, 7B, 8B "are AFM enlarged images of the nickel layer and copper layer of the solder pad of" pictures µ, 7A, 8A ", respectively. After processing the test piece through the above-mentioned engraving process, the grain shape and arrangement of the copper layer of the recording layer 91 and the bonding pad 90 can be clearly observed. For the nickel layer 91, the growth pattern of the columnar crystals can be clearly distinguished. In addition, it can be found that the recording of the copper layer near the pad 90 and the 102 layer of the intermetallic compound have different characteristics. The grain size, nickel near the pad 90, has smaller grains, and nickel near the intermetallic compound 102 layer has a larger grain size. In addition, for the copper layer of the pad 90, The shape of the grains can be clearly seen. Therefore, the observation of the formation mechanism 介 of the intermetallic compound 102 as a basis for the reliability analysis of the electronic assembly will be of great help. In summary, the AFM images obtained from the above different etching conditions can be known, the best AFM scanning images, the conditions can be set to the ion beam should be selected 7keV 'incidence current is 200 microamperes, and Test piece inclination angle. -Of course, the above example is used to illustrate the preferred embodiment of the present invention: ^^ :: 2 = conditional parameters, including: ion beam energy, etch j, and fresh material bumps used for flip-chip bonding and their The connected metal 塾 "::: The above is only a preferred embodiment of the present invention and it has been implemented. That is, all changes and modifications in accordance with the scope of the patent application for the present invention are covered by the scope of the patent for the present invention. Special

^234852 圖式簡單說明 ^圖式簡單說明】 第1圖,炎φ 銲球與及其相接之金屬墊和銲墊 的接合 構造圖 為覆晶技術中單一 第2圖,炎丄^ 234852 Simple illustration of the diagram ^ Simple illustration of the diagram] Figure 1, the joint of the Yan φ solder ball and the metal pads and solder pads connected to it.

Q0 ^ \ P 圖。 射離子束與試片的入射角度0之示意 第3圖,為試月崦、品— 像。 、、义—般的研磨、拋光製成後所的AFM影 $ 4圖’為經過4 + a aQ0 ^ \ P figure. Schematic diagram of the incident angle 0 between the ion beam and the test piece. Figure 3 shows the test moon and image. AFM image after grinding, polishing—like grinding and polishing $ 4Picture ’shows 4 + a a

影像。 、 千伙特(keV )的能量轟擊過之試片的AFM 第5圖,為經過5 影像。 大特(keV)的能量轟擊過之試片的afm 第6 A圖’為經過image. Figure 5 of the AFM of the test piece bombarded by the energy of thousands of keV (keV) is shown in 5 images. Afm of the test piece bombarded by energy of keV (picture 6A)

影像。 伏特(keV)的能量轟擊過之試片的afM 第圖,為第image. The afM of the test piece bombarded by the energy of volts (keV)

第7Α圖,為0、圖錄層與銲塾之銅層的AFM放大影像。 影像。 、、呈過7千伏特(keV )的能量轟擊過之試片的afM 第7B圖,為第8A ®Figure 7A is an enlarged AFM image of the 0, catalogue layer, and copper layer of the solder pad. image. The afM of the test piece that had been bombarded with energy of 7 kilovolts (keV). Figure 7B is 8A ®

第8A圖,為、θ、。圆錦層與詳塾之銅層的AFM放大影像。 影像。.、Λ^8千伏特(keV)的能量轟擊過之試片的afM 第8β圖,為第8A圖# 【圖式>4» 鱗層與銲墊之銅層的AFM放大影像。 1 0 · 链號說明】 20 30 晶片 金屬墊 介電保護層Fig. 8A is, θ ,. AFM image of the round brocade layer and the detailed copper layer. image. ., AfM Figure 8β of the test piece bombarded by energy of ^^ 8 kilovolts (keV), which is Figure 8A # [Schematic> 4 »AFM enlarged image of scale layer and copper layer of pad. 1 0 · Description of chain number] 20 30 Chip Metal pad Dielectric protection layer

第13頁 1234852 圖式簡單說明 40 :鈦(Ti) 5 0 :銅(Cu) 6 0、9 1 ··鎳(N i)層 7 0 :锡球 80 :基板 9 0 :銲墊 1 0 0 :試片 101 :離子束 1 0 2 :介金屬化合物 0 :入射角度 ΦPage 131234852 Brief description of drawings 40: Titanium (Ti) 5 0: Copper (Cu) 6 0, 9 1 · Ni (N i) layer 7 0: Tin ball 80: Substrate 9 0: Pad 1 0 0 : Test piece 101: Ion beam 1 0 2: Intermetallic compound 0: Incident angle Φ

第14頁Page 14

Claims (1)

12348521234852 1· 一種應用於原子力顯微鏡(AFM)之覆晶接合面檢測方 法,用以對覆晶接合(fl ip chip ,· FC)結構進行試片^備的 處理,包括: 切割以取得該覆晶接合結構,並研磨拋光為一覆晶試 片;以及 以離子束餘刻(ion beam etch)之方式,對經過前一步 驟研磨拋光的覆晶試片在入射離子束與試片於一入射角度 的態樣下進行表面處理,以獲得所需之原子力顯微鏡(A F Μ) 的試片。 2 ·如申請專利範圍第1項所述之應用於原子力顯微鏡(罐^ AFΜ)之覆晶接合面檢測方法,其中該覆晶試片的厚度介於1 至2mm之間。 3.如申請專利範圍第1項所述之應用於原子力顯微鏡( AFM)之覆晶接合面檢測方法 ',其中該離子束姓刻之離子束 能量為4keV至8keV,蝕刻時間為3分紅。 4 ·如申請專利範圍第1項所述之應用於原子力顯微鏡( AFM)之覆晶接合面檢測方法 ',其中該入射角度係為25度至 35度,最佳角度為30度。1. A method for detecting a flip-chip joint surface applied to an atomic force microscope (AFM), which is used to process a test piece of a flip-chip bond (FC chip structure), including: cutting to obtain the flip-chip bond Structure, and grinding and polishing into a flip-chip test piece; and in the manner of ion beam etch, the flip-chip test piece which has been polished and polished in the previous step is incident on the ion beam and the test piece at an incident angle. Surface treatment is performed to obtain the required test piece of the atomic force microscope (AF M). 2. The method for detecting a flip-chip joint surface applied to an atomic force microscope (can ^ AFM) as described in item 1 of the scope of patent application, wherein the thickness of the flip-chip test piece is between 1 and 2 mm. 3. The method for detecting a flip chip joint surface applied to an atomic force microscope (AFM) according to item 1 of the scope of the patent application, wherein the ion beam engraved ion beam energy is 4 keV to 8 keV, and the etching time is 3 cents. 4 · The method for detecting a flip-chip joint surface applied to an atomic force microscope (AFM) as described in item 1 of the scope of the patent application, wherein the incident angle is 25 degrees to 35 degrees, and the optimal angle is 30 degrees.
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