TWI234845B - Structure and manufacturing process of gate containing diffusion barrier layer - Google Patents

Abstract

The present invention relates to one kind of structure and manufacturing process of gate containing diffusion barrier, which utilizes the ion implantation method on silicon to form one diffusion barrier layer between a polysilicon layer and a tungsten silicide metal layer to avoid, during gate re-oxidation process, the occurrence of the silicon-atom diffusion phenomenon derived from the chemical potential difference between the polysilicon layer and the tungsten silicide metal layer, as well as the stress difference resulted from the lattice distortion phenomenon, which in turn reduces operational failure of the gate.

Description

The technical field to which the invention belongs] The present invention relates to a gate structure and process, in particular to a gate structure and process with a diffusion barrier layer, which is characterized by being capable of effective sand ionization and reoxidation processes. Lattice stress caused by sub-diffusion and stress difference between polycrystalline silicon layer and tungsten silicide layer. [First: Technology] The more integrated circuit technology enters the era of deep sub-microns, the more the component size becomes, the more the gate 1 'process becomes more and more complicated. For example, in the MOSFET device, the thickness of the layer is reduced from a few hundred angstroms to about forty angstroms. In this trend, the level of trace defects in the build-up layer is lower, so the thin film process rate, and Circuit technology is highly valued, and its reliability is directly related to the product's good competitiveness. It directly affects the entire production cost and affects the entire product. Therefore, the quality of ultra-thin gate layers has become the focus of many major manufacturers today. question. Hualu takes most MoS devices now as an example. It is defined by a gate oxide oxide gate oxide and a polycrystalline silicon layer and a tungsten silicide metal layer through the lithography process. However, this process will expose the gate oxygen layer to a money-carved environment such as plasma (piasma), which will cause the product f of the gate oxide layer to be damaged ', which will affect the hot carriers of the Mos device. "Sinality", a Gate woxidation recipe is often added to the process to repair this type of damage. However, under this process, Shi Xihua cranes that have a gap between the original chemical potential and the film stress will be induced. Diffusion of silicon atoms between the metal layer and the polycrystalline silicon layer causes the formation of holes and causes structural distortion, leading to the failure of the abnormal gate oxide layer.

Page 5 1234845 V. Description of the invention (2) ○ Therefore, the present invention proposes a gate structure with a diffusion barrier layer to solve the above problems. [Summary of the Invention] The main object of the present invention is to provide a gate structure and process with a diffusion barrier layer, which can prevent the diffusion of silicon atoms due to the difference in chemical potential between the polycrystalline silicon layer and the metal tungsten silicide layer. Another object of the present invention is to provide a gate structure and process with a diffusion barrier layer, which can avoid lattice distortion between the polycrystalline silicon layer and the metal silicide layer due to the gate reoxidation process. Yet another object of the present invention is to provide a gate structure and process with a diffusion barrier layer, which can be applied to the deep sub-micron era that is extremely sensitive to film defects and reduces the occurrence of defects. Another object of the present invention is to provide a gate structure and process with a diffusion barrier layer, which can reduce the thin film stress gap between a polycrystalline silicon layer and a metal silicide layer. One embodiment of the present invention is a gate structure with a diffusion barrier layer, which includes: a semiconductor substrate having a plurality of isolation regions therein; a gate oxide layer on the semiconductor substrate; and a gate electrode on the semiconductor substrate. A polycrystalline silicon layer on an oxide layer; a tungsten silicide metal layer formed on the surface of the polycrystalline silicon layer; and a diffusion barrier layer which ion implants the semiconductor substrate with silicon ions to place the polycrystalline silicon layer and the tungsten silicide metal The diffusion barrier layer is formed between the layers. Another embodiment of the present invention is a system having a diffusion barrier layer.

Page 6 1234845 _Case No. 92131192_Year Month__ V. Description of the invention (4) The body substrate is ion implanted to form a diffusion barrier layer 2 between the polycrystalline silicon layer 16 and the tungsten silicide metal layer 18 0, and the material of the diffusion blocking layer 20 is a broken amorphous material. The manufacturing method of the present invention will be described with reference to the structure shown in the first figure above. Please refer to Figures 2 (a) to 2 (d), which is a preferred embodiment of the present invention. The cross-sectional structure of each step of the gate structure of the layer is shown. As shown in the figure, the manufacturing method of the present invention includes the following steps: First, referring to the second (a) diagram, an isolation region 12 is formed on a semiconductor substrate 10. Subsequently, a gate structure process is started, and a silicon oxide as a gate oxide layer 14, a polycrystalline silicon layer 16, and a tungsten silicide metal layer 18 are sequentially formed on the semiconductor substrate 10 to form a second (b ) The structure shown in the figure, wherein the gate oxide layer 14 can be made in an oxidation furnace tube using a dry oxidation method, and before the process, a cleaning action can be performed on the semiconductor substrate 10 to make The exposed silicon surface is kept clean to ensure its quality. The polycrystalline silicon layer 16 is manufactured by a chemical deposition method, and the resistance value can be adjusted by diffusion method or ion implantation method. Tungsten silicide metal Layer 18 is made by chemical vapor deposition, and in order to make it have lower resistance, an annealing process may be performed after this process. Then, an ion implantation method is used to implant silicon ions with a concentration of 10 13-1 10 15 cm _2 between the tungsten silicide metal layer 18 and the polycrystalline silicon layer 16 to form a diffusion barrier layer 2 made of amorphous silicon. 0, forming a thin film stack structure as shown in the second (c) diagram. Next, a gate lithography etching process is performed on the semiconductor substrate 10 to form

1234845 _Case No. 92131192_Year Month Date__ V. Description of the invention (5) The gate structure 22 having a diffusion barrier layer 20 is formed as shown in one of the second (d) drawings. At this time, the lithography is repaired The damage caused by the etching process to the gate oxide layer 14 is often followed by a gate reoxidation process after the gate structure 22 is completed. In the present invention, due to the temperature effect, a higher energy (H i gh E ntropy) implanted silicon ions move to achieve a more stable energy (L 〇w E ntr 〇py), thereby eliminating the polycrystalline silicon layer 16 and tungsten silicide metal layer 18 caused by the conventional process. The resulting stress difference. The present invention provides another manufacturing method, in which an isolation region 12 is formed on a semiconductor substrate 10, as shown in the third (a) structure. Next, a gate structure process is performed to form a gate structure having a gate oxide layer 14, a polycrystalline silicon layer 16, and a tungsten silicide metal layer 18 on a semiconductor substrate, as shown in FIG. 3 (b). Then, using ion implantation, silicon ions with a concentration of 10 10 15 cm_2 were implanted between the tungsten silicide metal layer 18 and the polycrystalline silicon layer 16 to form a diffusion barrier layer 20 made of amorphous silicon. A gate structure with a diffusion barrier layer as shown in three (c) diagrams. In summary, the present invention is a gate structure and process with a diffusion barrier layer, which uses silicon ion implantation to form a diffusion barrier layer between a silicide metal layer and a polycrystalline silicon layer to suppress silicon. The diffusion of atoms due to the difference in chemical potential between the metal silicide and the polycrystalline silicon layer, and the use of silicon with higher energy to implant atoms in the gate reoxidation process, and appropriate atom movement and lattice reorganization to alleviate this The stress gap between the thin films caused by the manufacturing process can avoid the failure of the gate operation.

1234845 _ Case number 92131192_ 年月 日 __ V. Description of the invention (6) The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The equal changes and modifications of the shape, structure, characteristics and spirit described in the scope of the patent application shall be included in the scope of the patent application of the present invention. [Illustration of drawing number] 10 semiconductor substrate 1 2 isolation area 1 4 gate oxide layer 1 6 polycrystalline silicon layer

1 8 Tungsten silicide metal layer 2 0 Diffusion barrier layer 2 2 Gate structure

Page 10 1234845 Amendment No. 92131192 Brief Description of Drawings The first drawing is a sectional view of a structure of a preferred embodiment of the present invention, which is used to illustrate the structure of the present invention. The second (a) to the second (d) diagram are schematic diagrams of an embodiment of the present invention, and are used to explain the process steps of this embodiment. The third (a) to third (c) diagrams are schematic diagrams of another embodiment of the present invention, which are used to explain the process steps of this embodiment.

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Claims (1)

1234845 _Case No. 92131192_Year_Month__ VI. Application for patent scope 8 · As described in item 7 of the scope of application for a gate process with a diffusion barrier layer, the gate oxide layer of the silicon oxide uses dry oxidation It is prepared by oxidation furnace tube. 9 · The gate process with a diffusion barrier layer as described in item 8 of the scope of the patent application, wherein before the dry oxidation process is performed, a cleaning operation may be performed on the semiconductor substrate to keep the exposed stone surface clean. 10 · The gate process with a diffusion barrier layer as described in item 1 of the scope of the patent application, wherein the silicon ion implantation concentration is 1 0 13-1 0 15cnr2. 1 1 · The gate process with a diffusion barrier layer as described in item 1 of the scope of the patent application, wherein the material of the diffusion barrier layer is amorphous silicon. 1 2 · A gate process with a diffusion barrier layer, comprising: providing a semiconductor substrate having isolation regions formed therein; sequentially forming a gate oxide layer, a polycrystalline silicon layer on the semiconductor substrate, and A tungsten silicide metal layer; performing a gate lithography process to define a gate structure; and ion implanting the Shixi chemical crane metal layer with Shi Xi ions to form a diffusion resistance between the tungsten silicide metal layer and the polycrystalline silicon layer Barrier. 1 3 · The gate process with a diffusion barrier layer as described in item 12 of the scope of the patent application, wherein after the tungsten silicide metal layer is formed, an annealing process is performed to reduce the resistance of the metal lithoxide. 14. The gate process with a diffusion barrier layer as described in item 12 of the scope of the patent application, wherein the tungsten silicide metal layer is prepared by a chemical vapor deposition method. 1 5 · Gate with diffusion barrier as described in item 12 of the patent application Page 13 1234845 _Case No. 92131192_ Year Month__ VI. Patent Application Process, where the polycrystalline silicon layer is made by chemical deposition method. 16. The gate process with a diffusion barrier layer as described in item 12 of the scope of the patent application, wherein the resistance value of the polycrystalline silicon layer can be reduced by a thermal diffusion method or an ion implantation method. 17 · The gate process with a diffusion barrier layer as described in item 12 of the scope of the patent application, wherein the gate oxide layer is made of silicon oxide. 18 · The gate process with a diffusion barrier layer as described in item 17 of the scope of the patent application, wherein the gate oxide layer is prepared in an oxidation furnace tube by a dry oxidation method. 19 · According to the gate process with a diffusion barrier layer described in item 18 of the scope of the patent application, before the dry oxidation process is performed, a cleaning operation may be performed on the semiconductor substrate to keep the exposed silicon surface clean. . 2 〇 · The gate process with a diffusion barrier layer as described in item 12 of the scope of the patent application, wherein after the diffusion barrier layer is completed, a gate reoxidation process can be performed to repair the gate due to the etching process. Damage caused by oxide layer. 2 1 · The gate process with a diffusion barrier layer as described in item 12 of the scope of the patent application, wherein the silicon ion implantation concentration is 10 13-1 0 15 cm _2. 2 2 · The gate process with a diffusion barrier layer as described in item 12 of the scope of the patent application, wherein the material of the diffusion barrier layer is amorphous silicon. 2 3 · A gate structure with a diffusion barrier layer includes: a semiconductor substrate having a plurality of isolation regions therein; a gate oxide layer on the semiconductor substrate; a polycrystalline silicon layer on the semiconductor substrate Gate oxide Page 14 1234845 _Case No. 92131192_Year_Month__ Sixth, the scope of the patent application: a tungsten silicide metal layer formed on the surface of the polycrystalline silicon layer; and a diffusion barrier layer, which uses silicon ions to ionize the semiconductor substrate Implanted to form the diffusion barrier layer between the polycrystalline silicon layer and the tungsten silicide metal layer. 24. The gate structure with a diffusion barrier layer as described in item 23 of the scope of patent application, wherein the material of the gate oxide layer is silicon oxide. 25. The gate structure with a diffusion barrier layer as described in item 24 of the scope of patent application, wherein the gate oxide layer is formed by a dry oxidation method. 26. The gate structure with a diffusion barrier layer according to item 23 of the scope of the patent application, wherein the tungsten silicide metal layer is formed by a chemical vapor deposition method. 27. The gate structure with a diffusion barrier layer as described in item 23 of the scope of the patent application, wherein the polycrystalline silicon layer is formed by a chemical deposition method. 28. The gate structure with a diffusion barrier layer as described in item 23 of the scope of the patent application, wherein the silicon ion implantation concentration is 10 13-10 15 cm-2. 29. The gate structure with a diffusion barrier layer as described in item 23 of the scope of the patent application, wherein the material of the diffusion barrier layer is amorphous silicon. Page 15