TWI234260B - An interconnect structure of a chip and a configuring method thereof - Google Patents

Abstract

A chip has a power bus, a first metal layer and a plurality of internal electric circuits. The first metal layer includes a plurality of power lines which are connected to the power bus and running in parallel for delivering electrical power to the internal electric circuits. A plurality of metal lines on a second metal layer of the chip are configured by an automatic place and route (APR) step according to the internal electric circuits, and at least one sparse area is formed on the second metal layer. Later, at least one supply-power area is configured in the sparse area, and is connected electrically to the power bus.

Description

1234260 V. Description of the invention [Technical field to which the invention belongs] The present invention relates to an integrated circuit, and more particularly to a chip interconnect structure. [Previous technology] Integrated circuit is to reduce the size of various electronic circuits and circuits required to be fabricated on a tiny chip, and use a power bus to provide the power required for the above electronic circuits. FIG. 1 is a schematic diagram showing a power transmission structure of a conventional chip. As shown in Figure 1, the power rings 104a and 104b surrounding the chip 100 are used as chip power buses, which are connected to the connection points (pacj) 102a and 102b, respectively. Power sources of different potentials, where connection point 〇2a is high potential (VDD), and connection point 〇2b is low potential (VSS). Furthermore, a plurality of power rails 106a and 106b are arranged parallel to each other at the core portion of the chip 100, and are connected to the power ring 104a and 104b, respectively. These power lines are metal interconnects in the chip, which are used to evenly transfer power to the electronic circuit (not shown in the figure) located at the core of the chip. However, this type of power transmission structure has the following disadvantages: 1. The size of the power ring is too large, which wastes the precious limited space in the chip. It is known that the typical width of the power ring is between 20 micrometers and 4 ς = If the width of the power ring is reduced, this size is reduced. The voltage drop (Voltage hop) will cause the operating voltage to be insufficient and / or Electronic circuits can be operated at insufficient voltage. Area knife size of integrated circuit

V. Description of the invention (2) Approximately 3000 micrometers X 30000 micrometers, # 30 micrometers # current loop is combined to surround this integrated circuit, and the area is a width of%, which is for the chip ^ power supply The ring occupies about 7 of the integrated circuit. In terms of the effective use of the area, it is very wasteful. Benefit method: ft Τ, the power rotation is limited to the pre-planned path T ′. It cannot provide mines flexibly. Some of the electronic circuits of 1 worker are particularly power-consuming. The second is the insufficient power supply of the electronic circuits located in other areas in the f power supply path. "This causes a voltage drop, which causes the force transmission structure to use a long and narrow electric circuit. Figure 1 As shown, due to this circuit, when the size of this wafer is very large, the spring is responsible for the problem of uneven distribution of electric power to the electronic electricity, which is particularly easy to occur as described above. efficacy. [Summary of the Invention] The power transmission structure in the chip is conventionally used to provide power buses for the electronic circuits inside the chip, and in the power structure, the power bus is surrounded by the chip's force. The conventional power transmission junctions are arranged parallel to each other at the center of the chip's Xiao center = week 15, and the power path connecting a plurality of phase structures is planned to be narrow = minus line. Because the size of such a power bus is too large and the power f line inside the chip, it will have a power source. In view of this, the object of the present invention is to provide a problem of uneven supply. The structure is used to reduce the size of the wafer and to improve the interconnectability of a wafer. Uniform power distribution inside the chip Another object of the present invention is to provide additional power supply area around the metal wire: J photomask combination, in the metal layer to effectively use the internal wiring 1234260 Description of the invention (3) Structure blank area. Another object of the present invention is the clock-up θ method. In the automatic arrangement of the month = k for a configuration of a chip interconnect structure = = metal wire, the other side branch path remaining in the same-metal layer . As a method for supplying power to an electronic circuit according to the above object of the present invention. The chip has a power distribution line with a wiring structure inside the chip. The electric power source basin is composed of a power line, a first metal layer, and a plurality of wires. The metal layer has a plurality of power lines. Some power strips. ; Aunt flatly arranged in parallel and electrically connected to the power supply bus: Bit 2: = some electronic circuits are arranged automatically with windings to arrange a plurality of metal wires of the chip to one of the metal layers, so that the One > into at least one blank area. After that, at least an electric area 'is arranged in the blank area, and the power supply area is electrically connected to the power bus. According to a preferred embodiment of the present invention, there is a gap (sPacing) between the power supply area and the metal wires. The minimum value of this gap is equal to or greater than the minimum dimension, and the minimum wire spacing conforms to the unrelated Design rule of unrelated metal-to-metal. In addition, the power supply region may be a solid metal region 'or a non-solid metal layer region in the formation of the second metal layer, such as a mesh (mesh-1 ikee) metal region. In order to achieve electrical connection between the power supply area and the power lines, the number of layers of the dielectric plugs may be plural, and the dielectric plugs in each layer may be directly stacked vertically or not vertically. In addition, according to another preferred embodiment of the present invention, when the number of the second metal layers is two,

1234260 V. Description of the invention (4) The location of the power supply area on the same floor is a detailed structure. The babes correspond to each other to form a power supply area of the present invention, which is connected to a power bus for m selection. According to an embodiment of the present invention, the power supply area is indirectly electrically connected to the power source bus via at least one intermediary plug and the power source bus. The power supply line and the power bus can be directly and electrically connected to this power supply area and the power bus is merged as an electrical connection. This power supply area can also be directly connected to the power supply. [Embodiment] In general, the chip in the chip is used to transmit electricity. The power wheel 1 = 2 is used to connect other metal interconnects as shown in Figure 1. . When the product design is used to transmit signals, it gradually becomes a lot of lines. 'Multilayer metal layers and metal layers are interposed between the interlayers (a method that must be used for integrated circuits). The layers of each layer must be-a complete "back: : Iug) to achieve the purpose of being connected to each other: the short circuited $ :: 5: structure other than the plug has contacted each other and sent a contact window plug (c0rvr) to isolate it. Furthermore, it is connected to the electronic circuit with a number 。 Source and non-polar 'w power or electronic news Figure 2 U schematic diagram of multilayer metal interconnect structure in the chip. As shown in Figure 2

Page 9 1234260

=: The power lines 106 & and 106 "in the figure 22 are located in the multi-layer metal I,: ,, and the first metal layer (M1), parallel to each other along the direction 1 22 1 w 2 to supply the electronic circuit 108a in the chip , 108b, 108c, and θ 1 = electric power. The metal wires 116 used to transmit electronic signals of the electronic circuits 108a, 108b, and 108c = 1 are located in the multilayer metal interconnects, and the second metal layer in the structure. (M2), and arranged in parallel with each other along the direction 124. As mentioned above, the metal interconnects used to transmit electronic signals may not be the same. In the embodiment of FIG. 2, when there are more metal layers, The metal wires on the second metal layer (M3) are arranged parallel to each other along direction 122, and the metal wires on the fourth metal layer (M4) are aligned along the direction] 24 They are arranged parallel to each other. That is, the arrangement direction of the metal lines on two adjacent metal layers is perpendicular to each other, and each layer follows this rule to achieve the effect of optimizing the layout winding. In integrated circuits, automatic Layout winding (Automomatic Place & R0ute, APR) , Such as Avanti Ap〇n〇 or Cadence

Silicon Ensemble or other automatic layout winding tools are used to plan multi-layer metal interconnects, making the configuration of metal interconnects more efficient and optimized. In general, the density of metal lines decreases as the number of metal layers increases. That is, the higher the number of metal lines in a metal layer, the fewer blank areas remain. The present invention uses these remaining empty areas as additional power supply areas. As mentioned above, the more the blank space in the metal layer, the more suitable the Vietnamese metal layer is to configure the power supply region of the present invention. Such as

II IIMII circle page 10 1234260, description of the invention (6) Therefore, the use of extra power supply area to provide the use of excess area in the chip, not = branch "electric path can effectively jw product + but can reduce the conventional power ring It can be p-inch, and can be supplemented with the flexibility of the high-power-consumption electronics 2 power supply structure due to the situation and prevent the performance of the region: 2 & surface electricity execution. The 3D image shows the second metal layer (the area between the power supply area of Ming and the plurality of metal lines 116) in the second image.

Ln: = shows a schematic diagram of a preferred embodiment of the present invention. Light r] m (p0sitive) light sheet, used for photosensitive material after the IC shirt, the obtained pattern is the same as the pattern on the photomask η prime disc μ material exposure after development, the obtained

Uegatlve) photomask. For good complementation, the second metal layer (2) in the negative picture must be used. This photomask includes a plurality of trough-shaped regions 302, and in this trough-shaped region 3 UZ there are a plurality of phoenixes 1 1 β t & The second picture on this reticle 30 0a includes a power supply region 304a, which is modeled after 咚 μ, +, and 从, and is located from ΛΑ 广 丄 糸 in a region other than the above-mentioned plurality of slot-shaped regions 3 0 2 'i This power supply area 304a is a solid metal (soiid metal area). This power supply area 304a is connected to the electrical material from φα soil and connected to the electrical material, so == the transmission impedance of the connection or directly connected to the power loop circuit, and : The power ring is internal to the chip. Also, the width of the power ring can be reduced by 5 to 15. According to another embodiment of the present invention, the power supply area 302 & is intended to pass through the intermediary plug and the power line 106 & or 1010 in the figure 1234260. 5. Description of the invention ) Sexual connection, this connection method will be explained in detail below. It is worth noting that in the present invention, there must be an interval L between the grooved region 302 and the metal wire 116, and this interval L is equal to or greater than the minimum line distance that complies with the design rules between the unrelated metal wire and the metal wire. In this way, the power supply area 304a of the present invention will not affect the transmission of electronic signals on the metal wires 116 in the same metal layer (M2). In addition, if the distance between two metal wires is quite close, for example, when the distance between the two is approximately the minimum line distance of the design rule plus the two minimum line distances, the slot-shaped area of the present invention may include this Two metal wires that are relatively close together are shown in the slot-shaped area 3 丨 2 in FIG. 3A. That is, the number of metal lines contained in the groove-shaped region 312 in the present invention may be plural. Figures 3B to 3D are schematic diagrams illustrating other preferred embodiments of the present invention to illustrate that the power supply region of the present invention may be non-solid (n〇n-s〇1 id) other changes of the metal region . The difference between the mask 300b in FIG. 3B and the mask 300a in FIG. 3A lies in that the power supply area in FIG. 38 is not a mesh-like metal area. Furthermore, the present invention can also provide two or more different types of power supply areas on the same metal layer. For example, the photomask 300c in the figure (3) provides a solid metal power supply area 304c and the mesh metal power supply area 314c. The photomask 3D in FIG. 3D provides two different The grid density of the grid-shaped metal power supply areas 3 0 4 d and 3 1 4 d. The grid density of the power supply area 304 d is greater than the grid bifurcation of the power supply area 31 4 d, so it can be used in a unit area. Provides higher current loads. On the other hand, low-density power supply areas

Page 12 1234260 V. Description of the invention (8) Subtraction> Interconnect capacitance, so it is more suitable to be placed around the critical path circuit. It can be known from the above embodiments that the present invention can adjust the position of the power supply area and the grid density according to the distribution of electronic circuits in the chip and the power requirements to improve the efficiency of power supply and reduce the generation of interference. FIG. 4A is a schematic diagram illustrating a preferred embodiment of the present invention. The power ring 10 and "104b" surrounding the chip 400 are used as chip power buses, which are respectively connected to the connection points 102a and 102b to provide power at different potentials. The connection point 102a is a high potential ( VDD), and the connection point 102b is a low potential (vss). In addition, a plurality of power lines 1063 and 1061) are arranged parallel to each other at the core portion of the chip 1000, and are respectively connected to the power ring 104a. It is connected to 104b. Moreover, as mentioned above, these power lines 〇06a and 106b are the first metal layer (Ml) in the multilayer metal interconnection structure of the wafer 400. " 本The invention is on the higher metal layer of the multilayer metal interconnect structure of the wafer 400, such as the fourth metal layer (M4) 402a, to provide at least one power supply region 404a. The fourth metal layer 402a also has a plurality of metals Line, and a distance L from the power supply area 404a (as shown in FIG. 3A). The power supply area 402a of the present invention may be selected to be a high potential or a low potential as required. X The power supply area 404a of the present invention is connected to the power The method of loop 104 or 10 The need to make different choices. In this embodiment, the power supply region 404a is directly and electrically connected to the power ring 104b with a connection line 408a, for supplying a low-potential (VSS) power source.

Page 13! 234260 V. Description of the invention (9) And ‘this power supply area 404a can be directly combined with the power ring 104a or 104b as an electrical connection. In addition, this power supply area 404a can even be electrically connected to one of the power cords 106a or 1061 via an interposer (not shown in the figure) through the power cord 106a or 10. 61) Indirect electrical connection with the power ring 104a or 1041) 'This connection method will be described in the embodiment of Fig. 5C. In addition, 'as the area of the power supply area 4O4 & of the present invention is sufficient to withstand a large current load, the present invention can reduce the width and size of the conventional power supply ring 4a or 4b to reduce the area on the waste wafer. . According to a preferred embodiment of the present invention, the power supply area can also be used to reduce the number of sides of the power supply ring (104a or 1041), and even the structure of the power supply ring is completely unnecessary in the chip, and the power supply area is directly connected To the single-point chip power bus, the conventional power supply loops (104a and 1041) are directly replaced by the power supply area. FIG. 4B is a schematic diagram of another preferred embodiment of the present invention, which is used to illustrate that the power supply area of the present invention may occupy only a part of the blank area 某一 of a certain metal layer. As shown in FIG. 4B, the third metal layer (M3) 40 2b in the multilayer metal interconnect structure of the wafer 400 is different from the fourth metal layer 4002 in FIG. 4A in that The power supply region 404b occupies only a part of the third metal layer, and does not completely fill the entire third metal layer 402b. In addition, the electrical region 404b is electrically connected to the power supply loop 104a with a connection line 408b, for supplying a high-potential (VDD) power. It is worth noting that when the power supply structure 404a in FIG. 4A and the power supply structure 404b in FIG. 4β are formed in the chip together, at this time, the interconnection can increase the high and low potentials of the power bus Inter-layer capacitance. High internal capacitance value helps to suppress

1234260 V. Description of the invention (10) The noise of the supply-line, so the stability of the circuit of the present invention can be realized. 'Figures 5A to 5C use the wafer 400 in Figure 4A as an example to illustrate the relationship between the power supply area of the invention and other metal layers. The first diagram is a schematic cross-sectional view taken along the section line A_A 'in FIG. 4A. The wafer 400 has a multi-layer metal interconnection structure, including four metal layers: a fourth acoustic layer 40 2a, a third metal layer 402b, and a second metal layer 402 (: ^ first ^ metal layer 402d. The power bus of this chip 400 is a power ring 104. For the convenience of illustration, in the following figures, only a single power ring 104 is used to supply the pseudo potential (VDD) and low potential (VSS). As shown in FIG. 5A, the metal wire 416 located on the fourth metal layer 40 仏 of the wafer 400 is a metal plug 602 and a third metal layer ㈣ "Metal = 6 Electrical connection. On the other hand, the power supply area of the present invention is "the connection ring 408 (the connection line 408 is not located on this section line, so it is represented by a dashed line) and the fourth metal layer 4002a 104 is electrically connected. Section 5] 8 is a schematic cross-sectional view taken along section line BB in FIG. 4A. Because the section line is perpendicular to the power lines 106a and 106b of the chip 400, so The first redundant picture can see the cross section of the power lines 106a and 106b. Figure 5C shows the section along the section line c-c in the figure. Schematic diagram, this section line C-C 'coincides with one of the power lines 106b, and is used to explain how the power supply area 404a of the present invention is electrically connected to the power line 106a or 10 through the interposer plug, and Indirectly and electrically connected to the power bus 1 0 6 a or 10 6 b with the power line 〇 0 a or 10 6 b. In the embodiment of FIG. 5C, three types of power supply area and power line are shown. Connection class

1234260 V. Description of the invention (11) Crack. The first connection type 622 is a single-layer interposer plug 612 and a buffer power supply region 618 of each metal layer to connect the metal layer and the wire 106b, and the interposer plugs 612 are directly stacked.彳, The second connection type 624 is also a single-layer intermediary plug 612, and is equipped with a buffer power supply area 6 i 8 of each layer to connect the metal layer and the power cord 丨 〇6 b, but the plug 612 series Not directly stacked. Among the second connection types 624: the arrangement of the inserts is not straight. The buffer power supply area 618 of each metal layer is used to provide a tortuous arrangement, so it is more flexible and flexible in circuit design. Each metal layer can be adjusted as needed. Intermediate plugs 6 丨 8 between. The third connection type 626 of the Fox uses a single-layer interposer 612 and a multi-layer metal interposer 614, and cooperates with the buffer power supply area 618 'of some metal layers to connect the metal layer and the power line mb. This type of connection 626 shows that the interposer plugs here are not limited to only interlayer plugs 612 between layers, and interposer plugs 614 across multiple metal layers are also suitable for use in the present invention. It can be known from the foregoing that these three connection types may be used in combination with each other alternately depending on the situation, to improve the flexibility of the present invention during implementation. Fig. 6 is a schematic cross-sectional view taken along the line A-A in Fig. 4A when the power supply structure 40A in Fig. 4A is formed in the wafer together with the power supply structure 404b in Fig. 4β. As shown in Fig. 6, the power supply area 40 "is connected to the low potential in the power bus, and the power supply area 40b is connected to the high potential of the power bus. At this time, the upper and lower positions correspond to the power supply area 40. "AND = 4b forms a capacitor structure, which is equivalent to capacitor 632. This internal wiring structure equivalent to electricity and valleys can suppress the noise of the power line (s u P P 1 y _ 1 i n e), because

Page 16 1234260 V. Description of the invention (12) This can improve the stability of the integrated circuit. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

Page 17 1234260 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings, The detailed description is as follows: FIG. 1 is a schematic diagram showing a conventional power transmission structure of a wafer; FIG. 2 is a schematic diagram showing a multilayer metal interconnection structure in a wafer; and FIG. 3A is a photomask of the present invention. Figure 3B is a schematic diagram of another preferred embodiment of the photomask combination of the present invention; Figure 3B is a schematic diagram of another preferred embodiment of the photomask combination of the present invention; 3D is a schematic diagram of another preferred embodiment of the photomask combination of the present invention, and FIG. 4A is a schematic diagram of a preferred embodiment of the present invention; FIG. 4B is a schematic diagram of the present invention. A schematic diagram of another preferred embodiment of the invention; FIG. 5A is a schematic sectional view taken along section line AA ′ in FIG. 4A; FIG. 5B is a schematic sectional view taken along section line B-B in FIG. 4A. 'Cross-section schematic diagram; Figure 5C shows the section along Figure 4A A schematic cross-sectional view of C-C '; and FIG. 6 is a schematic cross-sectional view showing another embodiment of the present invention along the cross-sectional line A-A' in FIG. 4A.

Page 18 1234260 Simple illustration of the drawing [Simple description of component representative symbols] 1 0 0 · Chip 1 0 2 a, 1 0 2 b: Connection point 104, 104a, 104b: Power bus 1 0 6 a, 1 0 6 b : Power line 108a, 108b, 108c, 108d: Electronic circuit 1 16: Metal wire 122, 124: Direction 3 0 0a, 3 0 0b, 30 0c, 3 0 0d: Photomask 3 0 2, 3 1 2: Slot Shaped areas 304a, 304b, 304d, 304d, 314c, 314d: Power supply area 400. Wafer 402a: Fourth metal layer 402b. Third metal layer 402c. Second metal layer 402d. First metal layer. 404a, 404b: Power supply area 408a, 408b: Connection line 4 1 6, 6 1 6: Metal wire 6 0 2, 6 1 2, 6 1 4: Intermediate plug 6 1 8: Buffer power supply area 6 2 2, 6 2 4, 6 2 6: Connection type 6 3 2: Capacitance

Page 19

Claims (1)

1234260 6. Scope of patent application 1. A method for arranging interconnect structure of a chip, the chip has a power bus, a first metal layer and a plurality of electronic circuits, wherein the first metal layer has a plurality of power lines, the The power lines are substantially parallel to each other and are electrically connected to the power bus in parallel. The configuration method at least includes: arranging a plurality of wafers located on a second metal layer by an automatic layout winding according to the electronic circuits. Metal wires, wherein under the automatic layout winding configuration, at least one blank area is formed on the second metal layer; and at least one power supply area is arranged in the blank area, and the power supply area is electrically connected to the power bus Row, the power supply region includes a plurality of slot-shaped regions, and each of the slot-shaped regions includes at least one of the metal wires. 2. The configuration method described in item 1 of the scope of patent application, wherein the power supply area is electrically connected to one of the power lines via at least one intermediary plug, and the power line is indirectly electrically connected to the power bus through the power line. connection. 3. The configuration method described in item 1 of the scope of patent application, wherein the power supply area is directly electrically connected to the power bus. 4. The configuration method described in item 1 of the scope of patent application, wherein the power supply area is directly merged with the power bus. 5. The configuration method according to item 1 of the scope of patent application, wherein there is at least a gap between the power supply area and the metal lines. Page 20 1234260 _Case No. 92132183_ Year Month Amendment_ VI. Patent Application Range 6. The configuration method described in item 5 of the patent application range, wherein the distance is not less than the minimum line distance, and the minimum line distance is Meet the design rules between unrelated metal wires and metal wires. 7. The configuration method described in item 1 of the scope of patent application, wherein the power supply area is a solid metal area. 8. The configuration method described in item 1 of the scope of patent application, wherein the power supply area is a non-solid metal area. 9. The configuration method described in item 1 of the scope of patent application, wherein the power supply area is a mesh metal area. 10. The configuration method as described in item 1 of the scope of patent application, wherein when the number of the interposer plugs is plural in a direction perpendicular to the first metal layer, the interposer plugs are directly stacked and electrically charged. Connect the power supply area to one of the power lines. 1 1. The configuration method as described in item 1 of the scope of patent application, wherein when the number of the interposer plugs is plural in a direction perpendicular to the first metal layer, the interposer plugs are not directly stacked to Electrically connect the power supply area with one of the power lines. Page 21, 1234260 6. Application scope of patent 12. The arrangement method described in item 1 of the scope of application for patent, wherein when the number of the second metal layer is two, it is located in the two power supply areas of the second metal layer. The positions are substantially corresponding to each other to form a capacitor structure. 13. An interconnect structure of a chip, the chip having a power bus and a plurality of electronic circuits, the interconnect structure includes at least: a first metal layer having a plurality of power lines, the power lines are substantially mutually Are arranged in parallel and electrically connected to the power bus in parallel; and at least a second metal layer having a plurality of metal wires and at least one power supply area, wherein the metal wires are arranged according to an automatic layout winding, and At least one blank area is formed on the second metal layer, and the power supply area is disposed in the blank area and is electrically connected to the power bus. The power supply area includes a plurality of slot-shaped areas. Each includes at least one such metal wire. 14. The interconnection structure as described in item 13 of the scope of patent application, wherein the power supply area is electrically connected to one of the power lines via at least one intermediary plug, and the power line is indirectly connected to the power bus through the power line. Ground electrical connection. 15. The interconnection structure as described in item 13 of the scope of the patent application, wherein the power supply area is directly and electrically connected to the power bus. 16. The interconnection structure described in item 13 of the scope of patent application, wherein the power supply area is directly merged with the power bus. Page 22 1234260 VI. Scope of patent application 17. The interconnect structure described in item 13 of the scope of patent application, wherein there is at least one gap between the power supply area and the metal wires. 18. The interconnect structure described in item 17 of the scope of patent application, wherein the distance is not less than the minimum line distance, and the minimum line distance is in accordance with the design rules between non-relevant metal wires and metal wires. 19. The interconnect structure described in item 13 of the scope of patent application, wherein the power supply area is a solid metal area. 20. The interconnect structure described in item 13 of the scope of patent application, wherein the power supply area is a non-solid metal area. 21. The interconnect structure described in item 13 of the scope of patent application, wherein the power supply area is a mesh metal area. 22. The interconnect structure described in item 13 of the scope of the patent application, wherein when the number of the interposer plugs is plural in a direction perpendicular to the first metal layer, the interposer plugs are directly stacked, Electrically connect the power supply area with one of the power lines. 23. The interconnect structure described in item 13 of the scope of patent application, wherein when the number of the interposer plugs is plural in a direction perpendicular to the first metal layer Page 23 1234260 6. When applying for a patent, the intermediary plugs are not directly stacked to electrically connect the power supply area with one of the power cords. 24. The interconnect structure described in item 13 of the scope of the patent application, wherein when the number of the second metal layer is two, the positions of the two power supply regions located in the second metal layer substantially correspond to each other. To form a capacitor structure. 25. The interconnect structure described in item 13 of the scope of the patent application, wherein the automatic layout winding is to plan the configuration of the metal wires according to the electronic circuits. 26. A photomask combination for defining a metal layer of a wafer, the photomask combination includes at least: a first pattern to define a plurality of metal lines on the metal layer; a second pattern on the metal At least one power supply area is defined on the layer, wherein the power supply area includes a plurality of trough-shaped areas, each of the trough-shaped areas contains at least one of the metal wires, and the edges of the trough-shaped areas are each associated with the at least one metal contained therein. There is at least one space between them. 27. The photomask combination described in item 26 of the scope of the patent application, wherein the distance is not less than the minimum line distance, and the minimum line distance complies with the design rules between non-relevant metal wires and metal wires. 28. The photomask assembly described in item 26 of the scope of patent application, wherein the power supply area is a solid metal area. Page 24 1234260 6. Scope of patent application 29. The photomask combination described in item 26 of the scope of patent application, wherein the power supply area is a non-solid metal area. 30. The photomask combination according to item 26 of the scope of the patent application, wherein the power supply area is a mesh metal area. 31. The photomask combination described in item 26 of the scope of patent application, wherein at least one of the groove-shaped areas is used to define a plurality of metal wires. Page 25