TWI234242B - Manufacturing method of integrated flash memory and high voltage device - Google Patents

Abstract

A manufacturing method for integrated flash memory and high voltage (HV) device is disclosed, which combine the oxidation of flash memory with the oxidation of HV device in one process. First, the oxide between a floating gate and a control gate of a flash memory is formed with a first thickness. Then, the gate oxide of HV device is formed; meanwhile, the oxide of the flash memory is thickened to a second thickness. It avoids additional thermal cycles, which would affect the flash memory quality.

Description

1234242 _ Case No. 92122925_ Japanese amendment __ V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to semiconductor integrated circuit components, and particularly to the integration of flash memory and high voltage components Manufacturing method of integrated circuit. [Prior art]

Flash memory is a semiconductor technology developed based on the computer's random access memory (RAM). It is a solid-state storage system that requires only very little power to efficiently store memory. The block method can change the internal data instantly, and does not require any power to retain the data after storage. Other solid-state memories such as Read Only Memory (ROM), Static / Dynamic Random Access Memory (SRAM / DRAM), and Electronically-Erasable Read-Only Memory (Electricaiiy

Erasable Programmable Read Only Memory (EEPROM) ^ Both flash memory and flash memory are widely used. Among these solid-state memories, flash memory has the characteristics of non-volatile, repeatable read and write, high density and durability, etc., becoming the best quality remaining media. According to the different memory transistor design architecture, it can be divided into two types: cell type (Cel i Type) and operation type (〇per ti 〇n Type). The cell type can be divided into self-aligned gate (Seif — A1 igned Gate (ie, Stack Gate) and Split Gate (Spiit Gate). In contrast, discrete gate flash memory components are more power efficient than stacked gate flash memory components, and the size of the integrated circuit is even smaller. Therefore, currently split flash memory has become a very popular memory element. In addition, as everything shrinks, the channel length (Channel

$ 6Page 1234242 Case No. 92122925 V. Description of Invention (2)

Length) will make the operating speed of the transistor faster, but the problems caused by the shortening of the channel will become increasingly serious. This is the so-called Short Channel Effect. If the applied voltage does not change and the channel length of the transistor is shortened, it can be known from the equation (E · F-V / L) that the electric field (E. F) is equal to the voltage (V) divided by the length (L). The energy of the internal electrons will be increased by the enhancement of the electric field, which will increase the situation of electrical freakdow ^. On the other hand, if the channel length of the transistor is not changed 'and the voltage is increased', the strength of the electric field will also increase, so that the increase in the energy of the electrons in the channel will also cause an electrical breakdown. For example, 'high-density digital video disc (DVD) and LiqUid Crystal Display (LCD) drives' need to withstand high voltages from 12 volts to 30 volts, generally using an isolation layer and an isolation layer The uneven drift region (Drif t RegiOn) increases the distance between the source / inverter region and the gate, so that the device can still work normally under high voltage conditions. This is a high voltage device. Because the process of separating 7-pin flash memory and high-voltage components has its own needs and characteristics, the separation of ultra-flash memory and high-voltage components is usually produced on different chips by using different lines and wires. . It is a great challenge to integrate these two processes, and it takes more time and cost to design integrated circuits. '

Page 7 1234242 Case No. 92122925 Amended 5. Description of the invention (3) Manufacturing of oxide layer on floating gate and control is integrated. According to the purpose described above, the manufacturing method of this article includes: first, flash A substrate of the memory area; and a layer; then, the first definition step of the flash memory location is performed; a partial definition step of the first domain in the flash memory area is performed, and the operation of removing high voltage components to produce high voltage components Region; using the second oxidized region on the high-voltage element and at the same time making the above-mentioned first definition step of the first oxidized region in the process of manufacturing the oxide layer covered between the gate electrodes and the high-voltage element in the same integrated circuit process. Ming Ming integrates flash memory and high-voltage elements to provide a region of high-voltage elements and a first polycrystalline silicon step on the substrate. The first polycrystalline silicon is deposited in a flash oxidation step, and, The first layer is used to deposit the above-mentioned resistance and micro-layer. Therefore, the thick oxide layer of the first layer covers the first oxidation region covered by the high-covered dew film. Carved at least one oxide domain in a complex crystal. The shape voltage element region is a voltage element to define the second oxidation step. The oxidized region is formed into a step piece region in the 0 degree region. The middle part of the shape region is not struck by light. The thickness of this step region is greater than that of silicon. The layer is partially formed before the layer opening is formed to thicken the operation region. In the best implementation, and then exposed to the opening, you can flash the oxidized memory to form a layer; the first oxidized region is defined in the base material region of the multi-crystal crushed dioxide to perform a second layer to define the steps to form On the surface, the portion covered by the surface resistance of the substrate due to the original thickness increase may include: lithographically etching the polycrystalline silicon layer first. And the middle 0 is, for example, the sink memory area of the sedimentary layer, so there are regions. The steps can be protected by using light. The edge containing the oxidized material will be smaller than the second oxidized area

1234242 Case No. 92122925 Λ_ Name Amendment V. Description of the Invention (4) In a preferred embodiment of the present invention, a plurality of insulating layers are formed in the substrate. In addition, it is possible to keep only the layer in the polycrystalline silicon layer as the control gate of the flash memory voltage element region and the second polycrystalline silicon layer of the flash memory, which is faster than the first oxidized region. Both sides; Dioxide regions, as the high power source and the drain are located in the second general high voltage element, which is an important factor for the thermal quality of the 1 〇 〇 Α oxide layer. The number of thermal cycles using the memory is in the process. And, at the same time, make the high-voltage element and fast. In addition, it also has a holding element. In the first complex region, this insulation is the second oxidation step. The floating gate in the first oxidation region. The thickness of the two oxide layers of the gate complex crystal second layer of the second piezo element that overlaps the source of the first oxygen flash memory and forms part of the second body is about the thickness of the other elements. For the manufacture of the present invention, the integration of high voltage requires a new design The meta-flash memory can be made of a structure formed of a superior-quality silicon layer, which can be, for example, after removing the upper and lower portions of the substrate first, and can also be used in the second polycrystalline silicon layer. The region is changed into a pole and a drain, and the complex crystal layer is heavy, and the high voltage side. For about 1 0 0 0 i, it will be the shadow method. The first compound silicon that is oxidized in the field is at the high level before the shadow process is performed on the express structure or the photomask is made at the same integration point. Do not form a flash circuit that overlaps the first element, but the shape of the element sounds like a flashing memory circuit. [Embodiment] In order to make the description of the present invention more detailed and complete, reference may be made to the description of the following embodiments and the illustrations of Figs. 1 to 8. Among them, FIG. 1 to FIG. 8 are cross-sectional structural diagrams of the manufacturing process of integrating and separating the gate flash memory and the high-voltage device according to a preferred embodiment of the present invention. Although the invention

1234242

Case No. 92122 ^ V. Description of the invention (5) Flash memory and high-voltage components are used as a preferred embodiment of the present invention; integration with high-electricity migration components can also be structured: base / 10 ', whose material can be, for example, dream Material, the production region of the body region u, and a P-well (PW) region and a 1-well (NW) region located in the p-well region are determined in the high-voltage element region 12. Next, a plurality of dielectric layers for isolation, such as a field oxide layer (F i 1 ed Oxi de; FOX) 16, are formed in the substrate 10, which can be separated from the high-voltage element region 12 and the separation gate. The flash memory area 4 is used to prevent the short circuit of the element 2A. After that, a separate gate flash memory H is deposited on the substrate 10: The gate electrode layer 18 'is generally composed of a polycrystalline silicon material. In this floating gate, the layer 18 is covered by the separate gate flash memory. Area ", and at the same time cover the yt pressure element area 12. Or, generally, several pieces of separated gate memory will have a through oxide layer between the floating idler layer 18 and the substrate 10 (not shown) Therefore, before the floating gate layer i 8 is formed, the separate gate flash memory can be formed on all the A materials in the high voltage element region 12 and the split gate flash memory region 丨 4. The tunnel oxide layer is not limited to this. Generally, there are countless high-voltage elements and separated gate flash memory elements in the substrate 10. However, in Figure 1, only two representative parts are shown. Surface structure diagram 'and the height and width of the two parts of the high-voltage element area 12 and the separated gate flash memory area 14 and their relative heights and widths are not shown in proportion. Figure 1 represents only a schematic diagram of the structure. In other words, the

Page 10

1234242 Case No. 92122925 A_ Revision V. Description of the invention (6) The floating gate layer 18 in the separate flash memory area 14 is actually the same as the floating gate layer in the high voltage element area 12 18 has the same height. However, in order to make the structure in the split-gate flash memory region 14 clearer, the present invention only shows the structure on a larger scale. Referring to FIG. 2, a mask layer 20 is formed by a chemical vapor deposition process, and covers the surface of the floating gate layer 18 of the high-voltage element region 12 and the separated gate flash memory region 14. A preferred material of the mask layer 20 may be, for example, a nitride material in which nitride stones are deposited. Please refer to FIG. 3 again. First, the substrate 10 is covered with a layer of photoresist 22, and the photolithography and etching process is used to form an opening 23 in the mask layer 20 to define the separation gate flash. Component locations in memory area 14. In the lithography etching process, the photoresist 22 is covered on the high-voltage element region 12 to protect the structure in the high-voltage element region 12. Referring to FIG. 4, the photoresist 2 2 in the high-voltage device region 12 and the split gate flash memory region 14 are removed. Then, a cleaning step may be selectively performed to remove residues or cleaning agents on the surfaces of the polycrystalline silicon layer 18 in the mask layer 20 and the openings 23 and 3. After that, an oxidation step is performed to form an oxide layer 24 having a thickness of about 100 μA on the surface of the floating gate layer 18 in the opening 2 3 of the gate flash memory region 14. Among them, the oxide layer 24 is a gate dielectric layer between the floating gate and the control gate in the separated gate flash memory. Please refer to FIG. 5. The lithography and etching processes are used to define the position of the operating area (0 perati ο n D 〇mai η; 0 D) in the high voltage element area 12. This operating area is where the high voltage component is located. . First, cover a layer of photoresist 26 on part of the high-voltage element area 12 and the split gate flash memory area 14 so that

Page 11 1234242 Case No. 92122925 _f »Zheng V. Description of the invention (7)

The structure under the photoresist 26 can be protected. Then, the dry gate etching or wet surface etching is used to remove the part of the high voltage element region 12 that does not cover the photoresist 26 and the mask layer 20 and the floating gate layer 18 below it. 77 If a tunneling oxide layer is first formed between the substrate 10 and the floating gate layer 丨 8, when the floating gate layer 18 is removed, a part of the tunneling oxide layer will also be etched, so at this time A slight amount of tunneling oxide may be exposed. In summary, the thickness of the tunneling oxide layer is only about 100 Å, and since this tunneling oxide layer is not the focus of the present invention, the present invention will not specifically describe it here. VIII. Please refer to Figure 6 to remove the photoresist 2 6 in the high-voltage element area 2 and the split-gate flash memory area 14. Next, another oxidation step is performed. An oxide layer 28 is formed on the exposed surface of the substrate 0 in the operating region of the high voltage element region 12. At the same time as this oxidation part, the oxide layer 24 originally shown in the opening 23 of the separation gate flash & body region 14 as shown in Fig. 5 will also be thickened by this to form an oxide layer 24a. Among them, the oxide layer 28 is a gate oxide layer of a high-voltage element. ^ In this preferred embodiment of the present invention, it is expected that the oxide layer 2 8 ′ is formed to a thickness of about 1,000. However, under the same conditions, the increased thickness of the oxide layer 2 4 to the oxide layer 2 4 a will not equal 1 〇〇〇A. This is due to the presence of the oxidized layer 24 in the opening 23, which will cause the oxidation rate to be inferior to that of the oxidized layer. Come fast. Therefore, under the same process conditions and time, the oxide layer 24a in the opening 23 includes the previously formed total thickness', which is only about 1700 Å. Please refer to Figure 7 again, flash the high-voltage component area 丨 2 and the separate gate flash memory

No. 1234242 Case No. 92122925 Revision V. Description of the invention (8) All the deposited layers on the surface of the body region 14 are removed. This step can use a wet etching process such as a phosphoric acid tank. Next, in the high-voltage element region 12 and the separated gate flash memory region 14, all the floating gate layers 18 are removed, and only the oxide layer 24 a in the separated gate flash memory region 14 remains. Under the floating gate layer 18. The floating gate layer 18 retained in this part is the floating gate used as the flash memory of the separation gate. And in the step of removing the floating gate layer 18, in order to protect the oxide layer 2 8 of the high-voltage element region 12, a photoresist 30 can be selectively covered thereon to avoid the etchant and the oxide layer 2 8 surface contact, so as to obtain better quality of the oxide layer 2 8. Since the steps of FIG. 7 are completed, the features of the present invention have been completed. However, a subsequent process may be further performed to complete the production of the high-voltage device and the separate gate flash memory, as shown in FIG. 8. For example, referring to FIG. 8, a deposition and lithography process can be performed to form a gate layer 32 in the high-voltage element region 14 and the separated gate flash memory region 14, which is generally made of a polycrystalline silicon material. Made up. Among them, a part of the gate layer 32 is partially overlapped with the oxide layer 28 of the operating region of the high-voltage element region 12 and serves as a gate of the high-voltage element. In addition, a part of the gate layer 32 is superposed on the oxide layer 24a of the divided gate flash memory region 14 to serve as a control gate of the separated gate flash memory.

In addition, an ion implantation step may be performed to form a source and a drain of the high-voltage element and the split-gate flash memory in the high-voltage element region 12 and the split-gate flash memory region 14 respectively. Among them, for example, in the high-voltage element region 12, the N1E domain, which is located below the right end of the oxide layer 28 and is located in the N-well region, is the drain portion of the local voltage element, and the NH located below the left end of the oxide layer 28

Page 13 1234242 Case No. 92122925 Amended 5. Description of the invention (9) The domain is the source part of the high-voltage component, and the polycrystalline silicon layer 32 is located between the source and the drain. A portion having several field oxide layers 16 and several P II domains on the left side of the high-voltage element region 12 is another circuit structure. Since this portion is not the focus of the present invention, the present invention is not described here and will not be described in detail here. Limited to this. In addition, the present invention does not show the source and drain portions of the split-gate flash memory in the split-gate flash memory region 14 of FIG. 8. Generally, the source and the drain are separated. The two sides of the gate flash memory, that is, the positions of the first oxide layer 24a, the polycrystalline silicon layer 18, and the polycrystalline silicon layer 32 are between the source and the end. Since the floating gate layer is generally composed of a polycrystalline silicon material, when the above method of the present invention is used for manufacturing, in the manufacturing steps of FIG. 6, the exposed sides of the floating gate layer 18 may also be simultaneously Oxidative thickening. To solve this problem, the present invention also proposes a manufacturing method here. First, before the mask layer 20 is formed in the high-voltage device region 12 and the gate flash memory region 14 (before the step in FIG. 2), the lithography and etching process is used to define the high-voltage device region. In the middle of the operation area, the cover layer 20 is formed on the structure. At this time, there is only the cover layer 20 in the operation area. Then, when the lithography and etching processes are used again to define the operating area in the high-voltage element area 12 (step in FIG. 5), the position of the photoresist 26 can be controlled to slightly protrude from the floating gate layer 18 In the operating area. Therefore, by reuse. In the structure shown in FIG. 6, the side of the floating gate layer 18 can be protected by the cover layer 20 without being exposed to the oxidizing environment. During the manufacturing process of the split gate flash memory device, a thicker oxide layer needs to be formed.

Page 14 1234242 Case No. 92122925 _η Revision V. Description of the invention (10) The production of high-voltage components will affect the quality. Due to the gate oxide layer located on the floating gate and the control gate, the flash memory is oxidized in the middle process step. In this way, in countless cases, it is worth noting that in the embodiment, the other is due to high structural changes and other electricity is small, the present invention is not limited to, and the above-mentioned floating removal step, the layer deposition step, cleaning The steps are all familiar to the artist. The oxide layer 2 4. The oxide layer can be added to the same integrated circuit performance as one of the advantages of the invention depending on the product. Another advantage of the invention is to improve the product integration and high voltage. The quality does not affect the memory due to the high temperature and the thermal process required for the manufacture of its oxide layer. Therefore, the present invention integrates the manufacture of the oxide layer between the gates of the flash memory system and the high voltage components in the same process. The feature is that the separation gate layer is formed in two process steps, and the gate oxidation of the high-voltage element is also formed at the same time. The separation gate flash memory undergoes a thermal process, and the separation gate flash memory is maintained. Quality. Figures 1 to 8 above show the processes required for a better voltage device and separate gate flash memory device circuit according to the present invention, which can be increased or decreased as needed. The gate layer or gate layer deposition, lithography etching and de-deposition, lithography etching and removal steps, photoresist removal, oxide layer formation steps, ion implantation steps, etc. are known, so the present invention will not repeat them here. The above-mentioned formation thicknesses of 24a and the oxide layer 28 are merely examples, and the present invention is not limited thereto. In order to make the separated gate flash memory and high voltage element, this can make an integrated circuit have more power application technology. In order to make use of the existing manufacturing technology of the split gate flash memory, and to make the extra thermal process of the split gate flash memory pressure element decay, so it can be guaranteed.

Page 15 1234242 _Case No. 92122925_ Year Month__ V. Description of the invention (11) Maintain the quality of the original split gate flash memory. In addition, in the above embodiments, the manufacturing process of the high-voltage element and the split gate flash memory element was originally manufactured separately in two production lines. When the two processes are integrated in the present invention, there is no need to redesign the high-voltage element or the split gate. The structure of the flash memory and the pattern position of its photomask need not be changed, without additional cost or time redesign. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

Page 16 1234242 Case No. 92122925 Modified Simple Description [Schematic Description] In order to make the above and other objects, features, advantages and preferred embodiments of the present invention more comprehensible, please supplement it The drawings are as follows: FIG. 1 to FIG. 8 are cross-sectional structural diagrams of a process for integrating and separating a gate flash memory and a high-voltage element according to a preferred embodiment of the present invention. [Simple description of component representative symbols]

10 Substrate 12 South voltage element area 14 Split gate flash memory area 16 Field oxide layer 18 Floating gate layer 20 Cover layer 22, 26 ~ 30: Photoresist 23: Opening 24, 24a, 2 8: Oxide layer 32: gate layer

Page 17

Claims (1)

1234242 Case No. 92122925 A_3 Amendment VI. Patent application scope 1 · A manufacturing method for integrating flash memory and high-voltage components, the manufacturing method includes at least: a substrate including at least a high-voltage component region and at least A flash memory region; forming a floating gate layer on the substrate; defining a position of at least one gate flash memory in the flash memory region; performing a first oxidation step to form a A first oxidized region on a portion of the floating gate layer in the flash memory region; removing a portion of the floating gate layer in the high voltage element region to define an operating region of at least one high voltage element; And performing a second oxidation step to form a second oxidation region in the operation region of the high-voltage element region and to be located on the surface of the substrate, and at the same time, the thickness of the first oxidation region is increased. 2. The manufacturing method described in item 1 of the scope of patent application, further comprising: after the floating gate is formed, forming a cover layer to cover the floating gate layer; and performing a lithographic etching process on the At least one opening is formed in the mask layer to expose the floating gate layer, and the first oxidized region is formed in the opening. 3. The manufacturing method according to item 1 of the scope of patent application, further including : After the floating gate layer is formed, the high voltage element region is removed from the operating region Page 18 1234242 _ Case No. 92122925 _ month and year __ VI. Part of the floating gate layer in the scope of patent application; forming a cover layer to cover the floating gate layer; and performing a lithographic etching process, At least one opening is formed in the mask layer to expose the floating gate layer, and the first oxidized region is formed in the opening. The description of the mask is made by the method described in the law. The first material of the office, the Fanhua, Nitrogen and Nitrogen, please apply by the department of the fourth floor. Fan, the degree of medium and thick special step, please step into the Shenhua area, such as the oxidation of 5 dioxin, the above-mentioned method made by the French side of the above-mentioned items should be increased in the system of the region, the oxygen should be increased, The encirclement of the former Fan Zhicheng's special form, please apply the layer as described in the description of the method made by the law of the 6 gates. The above-mentioned items should be re-formed on the edge of the area, including the base material. The system ο 成 成 所 ί Item Η The 6-story enveloping Fan-Fu Li-Yi field is specially requested by Shen Yuru District 7 Yuan 8-story pole. The gate layer should be placed on the floating gate, the floating gate should be removed, and the profit-receiving department should go down to the Shenhua domain, such as the oxygen zone, and the oxygen level should be included in the above-mentioned method. The in-situ retention guarantee only floats the removal of the item made by its legal party in the removal. Item 8 Fan Li specially requested to apply for amendment on page 19 1232442 Case No. 92122925 Sixth, in the step of applying a patent for the gate layer, A photoresist is used to protect the second oxidized region in the high-voltage element region. 10 · The manufacturing method as described in item 1 of the scope of patent application, further comprising forming a gate layer on the high-voltage element region and the flash memory region, wherein part of the gate layer overlaps the first oxidation Region, and part of the gate layer is overlaid on the second oxidized region. 11. The manufacturing method as described in item 10 of the scope of patent application, further comprising forming at least one source and at least one drain in the high voltage element region, wherein the gate layer in the high voltage element region is located in the high voltage element region. Between the source and the drain. 1 2. The manufacturing method according to item 1 of the scope of patent application, further comprising forming at least one source and at least one drain in the flash memory region, wherein the first oxidation region is located between the source and the source. Between the drains. 1 3. A method for manufacturing a flash memory and a high-voltage device, the manufacturing method at least includes: providing a substrate having at least one high-voltage device region and at least one flash memory region; forming A floating gate layer covers the base material of the high-voltage element region and the flash memory region to form a cover layer covering the floating gate layer; the floating gate layer covers the floating gate layer; An opening is formed in the mask layer to expose Page 20 1234242 _ Case No. 92122925 _ month and month _ 6. The scope of the patent application for the floating gate layer; a first oxidation step is performed to form a first oxide layer in the opening on the floating gate layer ; Removing part of the cover layer in the high-voltage element region and the floating gate layer below, and defining at least one operating region in the high-voltage element region; performing a second oxidation step to form a second An oxide layer is in the operating region in the high-voltage element region, and at the same time, the thickness of the first oxidation region is increased; removing all the mask layers in the high-voltage element region and the flash memory region; removing All of the floating gate layer in the high-voltage element region and the flash memory region, but retaining a portion of the floating gate layer layer under the first oxide layer in the flash memory region; and forming A gate layer is located in the high-voltage element region and the flash memory region, part of the gate layer is overlapped on the first oxide layer, and part of the gate layer is overlapped on the second oxide layer. . Special application is required to apply the same power to the Arc Arc cart | This pole is used to set the gate of the ancient puppet layer. The step of the step of this step is 1 under 15 and the manufacturing method described in item 13 of the scope of patent application is formed before the cover layer. Before, the step of removing the floating gate layer in the high voltage element region required for the step of defining the operating region of the high voltage element region is performed. Page 21 No. 1234242 Case No. 92122925 Amendment VI. Patent application process, and after the first oxidation step, the step of removing the cover layer in the middle of the high-voltage element area is performed. 16. The manufacturing method as described in item 13 of the scope of patent application, wherein the above-mentioned mask layer is made of a nitride material. 1 7. The manufacturing method according to item 13 of the scope of patent application, wherein in the above-mentioned second oxidation step, the increased thickness of the first oxide layer is smaller than the thickness of the second oxide layer. 18. The manufacturing method as described in item 13 of the scope of patent application, further comprising forming a plurality of insulating regions in the substrate before the floating gate layer is formed. 19. The manufacturing method according to item 18 of the scope of patent application, wherein the above-mentioned insulating region is composed of a field oxide layer. 20. The manufacturing method as described in item 13 of the scope of the patent application, wherein in the step of removing all the floating gate layers, a photoresist is used to protect the second oxidized region in the high-voltage element region. 2 1. The manufacturing method as described in item 13 of the scope of patent application, further comprising forming at least one source and at least one drain in the high voltage element region, wherein the gate layer in the high voltage element region is located at Between the source and the drain. _"logic M | Page 221233242 _Case No. 92122925_Year Month Date__ VI. Application for Patent Scope 2 2. The manufacturing method described in Item 13 of Patent Application Scope, further includes forming at least in the flash memory area A source and at least one drain, wherein the first oxidized region is located between the source and the drain. 2 3. A method for manufacturing a flash memory and a high-voltage device, the manufacturing method at least includes: providing a substrate, the substrate including at least a high-voltage device region and at least one flash memory region; forming a A floating gate layer on the substrate; Define the position of at least one separate gate flash memory in the flash memory region; form a gate dielectric layer on the floating gate layer in the flash memory region; remove the height A gate layer is partially floated in the voltage element region to define an operation region of at least one high voltage element; and a gate oxide layer is formed in the operation region of the high voltage element region. 24. The manufacturing method as described in item 23 of the scope of patent application, wherein the step of forming a gate oxide layer in the operating region of the high voltage element region is to simultaneously increase the thickness of the gate dielectric layer. 25. The manufacturing method as described in item 23 of the scope of patent application, further comprising: after the floating gate is formed, a cover layer is formed to cover the floating gate layer 1234242 Case No. 92122925 2.The scope of the patent application is a lithographic etching process, at least one opening is formed in the mask layer to expose the floating gate layer, and the first oxidation region is formed in the opening. The manufacturing method described in the item 23 of the scope further includes: after the floating gate layer is formed, removing a part of the floating gate layer in the operating region of the high-voltage element region; forming a cover layer to cover the floating gate layer; On the floating gate layer; and performing a lithographic etching process, forming at least one opening in the mask layer to expose the floating gate layer, and the first oxidation region is formed in the opening. 2 7 The manufacturing method as described in item 25 of the scope of patent application, wherein the above-mentioned mask layer is made of a hafnium nitride material. 28. The manufacturing method as described in item 23 of the scope of patent application, further comprising forming a plurality of insulating regions in the substrate before the floating gate layer is formed. 29. The manufacturing method according to item 28 of the scope of patent application, wherein the above-mentioned insulating region is composed of a field oxide layer. 30. The manufacturing method described in item 28 of the scope of patent application, further comprising removing the floating gate layer after the second oxidation step, leaving only a portion of the floating gate below the first oxidation region. Floor. Page 24 1232442 1 厶 J 厶 厶 appeal 厶 Case No. 92122925_Year Date_ Sixth, the scope of the patent application Fan Li specifically requested to apply for the step of the oxygen layer two-pole gate of the mid-level step zone < 3 An item used in the float-made French method W ο refers to the high-voltage piezoelectric element that is removed from its area, the protection and light-blocking forming, including the item made in the French method, 3 2 Zhongru 2 3 points R—The area in the entrance is self-explanatory 0 flashing and the element voltage is high in the layer gate Unul system layer gate In this section and the zone is oxygenated 1 ο The upper field The gate is superimposed on the second layer of the heavy oxygen system in the area. The fan is in the stack. Fan Li specially invited the 2 pole system 3 as described in the 3 method to make it. A piece of less 3S.1 forming includes a higher value. In the middle, the pole area draws the element and the voltage source power is high. This place should be in place. Fan Li specially requested to apply as described in the 4 method made by the law, such as less pole 2 to the source into the shape in the middle area. In the memory area of the system, the scintillation oxygen is 3 times faster and shorter, and the source of the pole is the same as that of the pole. Page 25