A7 B7 A 9 /1 〇 2 5691twf.doc/008 五、發明説明（I ) 本發明是有M於一種快閃記憶體（Flash memory)的製造 方法，且特別是有關於一種改善分離閘極式快閃記憶體氧 化層品質的方法。 非揮發性記憶體（Nonvolatile memory)現係應用在各種 電子元件的使用上，如儲存結構資料、程式資料及其它 可以重複存取的資料。而在可程式非揮發記憶體上，最 近更是強調如快閃記憶體結構之可抹除且可程式唯讀記 憶體（Erasable Programmable Read-Only Memory, EPROM) 或是可電除且可程式唯讀記憶體（Electrically Erased Programmable ROM)的應用。通常快閃記憶體具有兩個閘 極，其中分爲以複晶矽所製作用來儲存電荷的浮置閘 (Floating Gate)，以及用來控制資料存取的控制閘（Control Gate)。浮置閘位於控制閘下方，且通常處於”浮置”的狀 態，沒有和任何線路相連接，而控制閘通常與字元線（Word Line)相接。而由於快閃記憶體中的資料，可以進行多次 存入、讀取與淸除等的動作，因此成爲半導體市場上， 成長頗爲快速的產品。 近來，半導體元件爲了達到降低成本，簡化製程步驟的 需求上，將記憶體區（Mem〇ryce11)與週邊電路區（Periphery circuit)的元件整合在同一晶片上已逐漸成爲一種趨勢，例 如將動態隨機存取記憶體（D R A M)與週邊電路元件之製程 架構在同一晶片上’稱之爲嵌入式動態隨機存取記憶體 (Embedded DRAM)，而將快閃記憶體與週邊電路元件整合 在同一晶片上，則稱之爲嵌入式快閃記憶體（Embedded 請 先 閱 讀 背 意 再; ύ 寫 本 頁 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ2.97公釐） 4 3 ?- 6 2 5691twf.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（1) flash memory)。 而在記憶體區元件追求可靠度（Reliability) ’週邊電路 區追求高效能（High performance)的優先順序下，以及在考 量到元件施加電壓的高低下，使得在將記憶體區與周邊電 路區之元件整合在同一晶片的製程中，需製造具有不同厚 度的閘極氧化層，以使元件在操作上可以達到要求。 第1A圖至第1E圖所繪示的是習知一種分離閘極式快 閃記憶體的製造流程剖面示意圖。請參照第1A圖，提供 一矽基底100，接著利用熱氧化法在矽基底100上形成一 層穿隨氧化層（Tunneling oxide)102。然後，依序在穿險氧 化層102上形成一層第一複晶矽層104和一層氮化矽層 106 〇 請參照第1B圖，定義氮化矽層106，以形成一暴露出 預定形成浮置閘之第一複晶矽層104的罩幕層l〇6a。接 著’利用熱氧化法在所暴露出的第一複晶矽層104上形成 一複晶矽氧化層108。由於氮化矽材質所形成之罩幕層l〇6a 在高溫下對水分子與氧氣的擴散具有良好的阻擋能力，因 此，在罩幕層106a所覆蓋的矽基底100表面並不會生成 氧化矽，而未被罩幕層l〇6a所覆蓋的表面，則被氧化而 形成由氧化矽所構成的複晶矽氧化層108。另外，由於水 分子與氧氣對罩幕層l〇6a角落的部份依然有能力進行水 平方向的擴散，因此位於罩幕層l〇6a角落的矽基底1〇〇， 仍會產生不同程度的氧化，而使所形成之複晶矽氧化層108 的部份呈現鳥嘴(Bird’s beak)的外観。 先 閲 讀 背 意 事 i 訂 本紙垠尺度適用中國國家標準（CNS } Μ规格（210X297公釐） 4324b2 A7 5691twf,doc/008 五、發明説明（3 ) 請參照第1C圖，剝除罩幕層106a，以暴露出部分第一 複晶矽層104。接著，利用複晶矽氧化層108爲罩幕，穿 隧氧化層102爲蝕刻終止層，去除所暴露出的第一複晶矽 層104,以在穿隧氧化層102上形成一浮置閘（Floatmg gate)104a。繼之，再次進行熱氧化法以在浮置閘104a的 側壁形成氧化間隙壁110。然而，在形成氧化間隙壁110 的步驟中，裸露之複晶矽氧化層108與穿隧氧化層102上 依舊會與氧氣和水分子反應而生成氧化矽層，故裸露之複 晶矽氧化層108會些微變厚成爲複晶矽氧化層108a，而穿 隧氧化層102亦會些微變厚成爲厚氧化層（Thick 〇xide)103。其中，厚氧化層103的厚度爲穿隧氧化層102 與在氧化間隙壁110形成步驟中穿隧氧化層102上所生成 的氧化層厚度之總和，故厚氧化層103的厚度大於穿隧氧 化層102的厚度。由於複晶矽氧化層108a與氧化間隙壁110 包覆著浮置閘l〇4a，故使得浮置閘104a與外界呈現電性 隔離的狀態。 請參照第1D圖，在基底100上沉積一層氮化層（未繪示 於圖），續進行一蝕刻步驟，以在氧化間隙壁U0側壁形 成一氮化間隙壁112。 請參照第1E圖，在基底100上全面覆蓋一層第二複晶 石夕層114，續定義第二複晶砂層114，以在複晶砂氧化層 l〇8a上形成分離閘極式快閃記憶體的控制閘（Control gate)。其中，分離閘極式快閃記憶體的製作更包括在基底 100表面下，浮置閘l〇4a的側邊形成有汲極區與源極區。 5 (請先閲讀背面之注意事項再填寫本頁) 〇 裝. 訂 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 4 3 2462 A7 5691twf.doc/008 gy 五、發明説明（0) 由於後續製程係爲熟悉該項技藝者所知悉的技術，所以 在此不多做贅述。 由於氮化間隙壁112形成於厚氧化層丨〇3生成之後，所 以在形成氮化間隙壁112的蝕刻過程中，會破壞厚氧化層 103的品質（Quality)、均勻性（Unif〇rmity)與厚度 (Thickness) ’致使厚氧化層1〇3劣化。而由於厚氧化層1〇3 係做爲周邊高壓元件之閘氧化層之用，故較薄的閘極氧化 層厚度將使其所能承受捕獲電荷(Trapping Charge)的數目 減少，造成閘極氧化層崩潰（Oxide Breakdown)現象的提 前發生，而嚴重地影響閘極氧化層的長期可靠度（L〇n卜 Term Reliability)。所以厚氧化層1〇3的劣化將會導致 邊高壓元件的效能降低。 ° 因此，本發明的主要目的就是在提供一種改善分離閘極 式快閃記憶體氧化層品質的方法，以避免做爲周邊高麼元 件之閘氧化層之用的厚氧化層品質劣化，進而維持周邊高 壓元件的效能。 ％ 本發明提出一種改善分離閘極式快閃記憶體氧化層品胃 的方法。其包括下列步驟：提供一矽基底，以及在砂 上形成有一層穿隧氧化層、一浮置閘與一複晶矽氧化層。 繼之，進行一熱氧化步驟，以在浮置閘的側壁形成氧化間 隙壁，且連帶增厚複晶矽氧化層與穿隧氧化層，而變厚$ 穿隧氧化層係成爲一厚氧化層，以做爲周邊高壓元件閘氧 化層之用。由於浮置閘被複晶矽氧化層與氧化間隙壁& 覆，故其與外界呈現電性隔離的狀態。接著，在氧化間隙 6 本紙張尺度適用中國國家橾牟（CNS > A4规格（210X297公釐） --------装------訂- (請先閲讀背面之注意事項再填寫本頁) k- Λ Ο 〇 / Ό Α/ ϋ ^5 ^'9 ltwf , d〇c/〇〇8 gy 五、發明説明（Κ )A7 B7 A 9/1 〇 2 5691twf.doc / 008 V. Description of the invention (I) The present invention is a method for manufacturing a flash memory, and in particular, it relates to an improved separation gate type Method of flash memory oxide quality. Non-volatile memory (Nonvolatile memory) is currently applied to the use of various electronic components, such as storage structure data, program data and other data that can be repeatedly accessed. On programmable non-volatile memory, recently, the emphasis is on erasable and programmable read-only memory (EPROM) such as flash memory structure, or programmable and programmable read-only memory (EPROM). Reading memory (Electrically Erased Programmable ROM) application. Flash memory usually has two gates, which are divided into a floating gate made of polycrystalline silicon to store charge and a control gate used to control data access. The floating gate is located below the control gate and is usually in a "floating" state. It is not connected to any line, and the control gate is usually connected to the Word Line. Because the data in flash memory can be stored, read, and erased multiple times, it has become a fast-growing product in the semiconductor market. Recently, in order to reduce the cost and simplify the process steps of semiconductor devices, it has become a trend to integrate the components in the memory area (Memory 11) and the peripheral circuit area on the same chip. For example, dynamic random The process structure of the access memory (DRAM) and peripheral circuit components on the same chip is' embedded dynamic random access memory (Embedded DRAM), and the flash memory and peripheral circuit components are integrated on the same chip , It ’s called embedded flash memory (Embedded, please read it before you can write it); This page is printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives. (Mm) 4 3?-6 2 5691twf.doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention (1) flash memory). Under the priority order of pursuit of reliability in the memory area components' pursuit of high performance in the peripheral circuit area, and considering the level of voltage applied to the components, the memory area and peripheral circuit area The components are integrated in the same wafer process, and gate oxide layers with different thicknesses need to be manufactured so that the components can meet the requirements in operation. FIG. 1A to FIG. 1E are schematic cross-sectional views illustrating a manufacturing process of a conventional gate-type flash memory. Referring to FIG. 1A, a silicon substrate 100 is provided, and then a tunneling oxide layer 102 is formed on the silicon substrate 100 by a thermal oxidation method. Then, a first polycrystalline silicon layer 104 and a silicon nitride layer 106 are sequentially formed on the through-thickness oxide layer 102. Please refer to FIG. 1B to define the silicon nitride layer 106 to form a floating layer that is exposed to the predetermined formation. The mask layer 106a of the first polycrystalline silicon layer 104 of the gate. Next, a polycrystalline silicon oxide layer 108 is formed on the exposed first polycrystalline silicon layer 104 by a thermal oxidation method. Since the mask layer 106a formed of the silicon nitride material has a good barrier ability to the diffusion of water molecules and oxygen at high temperature, no silicon oxide is generated on the surface of the silicon substrate 100 covered by the mask layer 106a. The surface not covered by the mask layer 106a is oxidized to form a polycrystalline silicon oxide layer 108 composed of silicon oxide. In addition, because water molecules and oxygen still have the ability to diffuse horizontally at the corners of the mask layer 106a, the silicon substrate 100 located at the corner of the mask layer 106a will still produce different degrees of oxidation. , So that a part of the formed polycrystalline silicon oxide layer 108 appears as a bird's beak. First read the note i The size of the paper is applicable to the Chinese national standard (CNS) M size (210X297 mm) 4324b2 A7 5691twf, doc / 008 5. Description of the invention (3) Please refer to Figure 1C, and remove the cover layer 106a To expose part of the first polycrystalline silicon layer 104. Then, using the polycrystalline silicon oxide layer 108 as a mask and the tunneling oxide layer 102 as an etching stopper, the exposed first polycrystalline silicon layer 104 is removed to A floating gate 104a is formed on the tunnel oxide layer 102. Next, a thermal oxidation method is performed again to form an oxidation spacer 110 on the side wall of the floating gate 104a. However, in the step of forming the oxidation spacer 110 However, the exposed polycrystalline silicon oxide layer 108 and the tunneling oxide layer 102 will still react with oxygen and water molecules to form a silicon oxide layer. Therefore, the exposed polycrystalline silicon oxide layer 108 will slightly thicken and become a polycrystalline silicon oxide layer. 108a, and the tunneling oxide layer 102 will become slightly thicker to become a thick oxide layer (Thick Oxide) 103. Among them, the thickness of the thick oxide layer 103 is the tunneling oxide layer 102 and the tunnel oxidation in the formation step of the oxidation spacer 110. Thick oxide layer formed on layer 102 Taken together, the thickness of the thick oxide layer 103 is greater than the thickness of the tunneling oxide layer 102. Since the polycrystalline silicon oxide layer 108a and the oxidation spacer 110 are covered with the floating gate 104a, the floating gate 104a and the outside world appear A state of electrical isolation. Referring to FIG. 1D, a nitride layer (not shown) is deposited on the substrate 100, and an etching step is continued to form a nitride spacer 112 on the sidewall of the oxidation spacer U0. Referring to FIG. 1E, a second polycrystalline stone layer 114 is completely covered on the substrate 100, and the second polycrystalline sand layer 114 is further defined to form a separated gate flash memory on the polycrystalline oxide layer 108a. Control gate of the body. Among them, the manufacture of the split gate flash memory further includes a drain region and a source region formed on the side of the floating gate 104a under the surface of the substrate 100. 5 ( Please read the notes on the back before filling this page) 〇 Packing. Ordered by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the consumer co-operatives, this paper applies Chinese national standards (CNS > A4 size (210X297 mm)) Printed by Employee Consumer Cooperatives 4 3 2462 A7 5691twf.doc / 008 gy 5. Description of the invention (0) Since the subsequent process is a technology familiar to those skilled in the art, it will not be repeated here. Since the nitrided spacer 112 is formed in a thick oxide layer 丨 〇 After 3 is generated, the quality, uniformity, and thickness of the thick oxide layer 103 will be destroyed during the etching process of forming the nitrided spacer 112, and the thick oxide layer 103 will be deteriorated. . Since the thick oxide layer 103 is used as the gate oxide layer of the surrounding high-voltage components, the thinner gate oxide layer thickness will reduce the number of trapping charges that it can withstand, resulting in gate oxidation. The layer breakdown (Oxide Breakdown) phenomenon occurs in advance, which seriously affects the long-term reliability of the gate oxide layer (Term Reliability). Therefore, the degradation of the thick oxide layer 103 will cause a decrease in the efficiency of the high-side element. ° Therefore, the main purpose of the present invention is to provide a method for improving the quality of the oxide layer of the separated gate flash memory, so as to avoid the deterioration of the thickness of the thick oxide layer used as the gate oxide layer of the peripheral high-level device, and then maintain Efficiency of peripheral high-voltage components. The present invention provides a method for improving the stomach of the gated flash memory oxide layer. It includes the following steps: providing a silicon substrate, and forming a tunneling oxide layer, a floating gate, and a polycrystalline silicon oxide layer on the sand. Next, a thermal oxidation step is performed to form an oxidation gap wall on the side wall of the floating gate, and the thickened polycrystalline silicon oxide layer and the tunneling oxide layer are thickened together, and the thickening $ tunneling oxide layer becomes a thick oxide layer. , As a gate oxide layer for surrounding high-voltage components. Since the floating gate is covered by the polycrystalline silicon oxide layer and the oxide spacer, it is electrically isolated from the outside. Next, in the oxidation gap of 6 paper sizes, the Chinese national standard (CNS > A4 size (210X297 mm)) -------- install -------- order- (Please read the precautions on the back first (Fill in this page again) k- Λ Ο 〇 / Α Α / ϋ ^ 5 ^ '9 ltwf, d〇c / 〇〇8 gy V. Description of the invention (K)
壁側壁形成一氮化間隙壁，續以氮化間隙壁爲罩幕，去除 未被氮化間隙壁所遮蓋之第一厚氧化層，以暴露出矽基 底。然後’在裸露的矽基底上形成一層第二厚氧化層。最 後，於複晶矽氧化層上形成一控制閘，以完成分離閘極式 快閃記憶體的製作D 本發明的特徵在於先去除原先遭受鈾刻破壞的厚氧化 層，再重新於裸露的矽基底上形成一做爲周邊高壓元件閘 氧化層之用的厚氧化層，以維持厚氧化層應有的品質、均 勻性與厚度，進而保有周邊高壓元件應有的效能。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1A圖至第1E圖所繪示的是習知一種分離閘極式快 閃記憶體的製造流程剖面示意圖；以及 第2A圖至第2F圖所繪示的是依照本發明一較佳實施 例，一種分離閘極式快閃記憶體的製造流程剖面示意圖。 其中，各圖標號之簡單說明如下： 100，200 :矽基底 102，202 :穿隧氧化層 103，203，203a，214 :厚氧化層 104，204 :第一複晶矽層 104a，204a :浮置閘 106，l〇6a，206，206a :絕緣層 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (諳先閱讀背面之注意事項再^'寫本頁) .裝. 經濟部智慧財產局員工消費合作社印製 λ 6 2 5691twf.doc/008 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明u ) 108，108a ’ 208，208a :複晶矽氧化層 Π0，210 :氧化間隙壁 112 ’ 212 :氮化間隙壁 114，216 :第二複晶矽層 實施例 第2A圖至第2F圖所繪示的是依照本發明一較佳實施 例，一種分離閘極式快閃記憶體的製造流程剖面示意圖。 請參照第2A圖’提供一矽基底200，接著在矽基底200 上形成一層名爲穿隧氧化層的薄氧化層202。其中，穿隊 氧化層202的形成方法比如是利用熱氧化法，在矽基底200 上形成厚度約爲85-95埃的氧化矽層。然後，依序在穿隧 氧化層202上形成一層第一複晶砂層204和一層絕緣層 206，其中絕緣層206的材質比如爲氮化矽。 請參照第2B圖，定義絕緣層206，以形成一暴露出預 定形成浮置閘之第一複晶矽層2〇4的罩幕層206a。接著， 在所暴露出的第一複晶砍層204上形成一複晶较氧化層 2〇8，以做爲快閃記億體中控制閘與浮置閘之間的介電層。 其中’複晶矽氧化層208的形成方法例如是利用熱氧化法， 較佳的是濕式氧化法，且其材質比如爲氧化矽。 由於氮化矽材質所形成之罩幕層2〇6a在高溫下對水分 子與氧氣的擴散具有良好的阻擋能力，因此，在罩幕層206a 所覆蓋的矽基底200表面並不會生成氧化矽，而未被罩幕 層2〇6a所覆蓋的表面，則被氧化而形成由氧化矽所構成 的複晶矽氧化層208。另外，由於水分子與氧氣對罩幕層 g (請先聞讀背面之注意事項再填寫本頁) 、-口A nitrided spacer is formed on the side wall of the wall, and the nitrided spacer is used as a mask to remove the first thick oxide layer not covered by the nitrided spacer to expose the silicon substrate. A second thick oxide layer is then formed on the exposed silicon substrate. Finally, a control gate is formed on the polycrystalline silicon oxide layer to complete the production of the separated gate flash memory. The present invention is characterized in that the thick oxide layer originally damaged by the uranium etching is removed first, and then the exposed silicon is re-exposed. A thick oxide layer is formed on the substrate as a gate oxide layer for the surrounding high-voltage components to maintain the quality, uniformity, and thickness of the thick oxide layer, thereby maintaining the proper performance of the surrounding high-voltage components. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1A to FIG. FIG. 1E shows a schematic cross-sectional view of a conventional manufacturing process of a split gate flash memory; and FIGS. 2A to 2F show a split gate according to a preferred embodiment of the present invention. Schematic cross-sectional view of the manufacturing process of flash memory. Among them, a brief description of each icon number is as follows: 100, 200: silicon substrate 102, 202: tunneling oxide layers 103, 203, 203a, 214: thick oxide layer 104, 204: first polycrystalline silicon layer 104a, 204a: floating Set the gate 106, 106a, 206, 206a: Insulating layer 7 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (谙 Read the precautions on the back before you write the page). Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs λ 6 2 5691twf.doc / 008 Α7 Β7 Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention 210: Oxidation spacer 112 '212: Nitrid spacer 114, 216: Second embodiment of a polycrystalline silicon layer Figures 2A to 2F show a separation gate according to a preferred embodiment of the present invention. Schematic cross-sectional view of the manufacturing process of the flash memory. Referring to FIG. 2A, a silicon substrate 200 is provided, and then a thin oxide layer 202 called a tunneling oxide layer is formed on the silicon substrate 200. The method for forming the through-layer oxide layer 202 is, for example, a thermal oxidation method to form a silicon oxide layer with a thickness of about 85-95 angstroms on the silicon substrate 200. Then, a first polycrystalline sand layer 204 and an insulating layer 206 are sequentially formed on the tunneling oxide layer 202, and the material of the insulating layer 206 is, for example, silicon nitride. Referring to FIG. 2B, the insulating layer 206 is defined to form a mask layer 206a that exposes the first polycrystalline silicon layer 204 which is intended to form a floating gate. Next, a polycrystalline oxide layer 208 is formed on the exposed first polycrystalline cutting layer 204 as a dielectric layer between the control gate and the floating gate in the flash memory. The method of forming the 'multicrystalline silicon oxide layer 208 is, for example, a thermal oxidation method, preferably a wet oxidation method, and the material is, for example, silicon oxide. Since the mask layer 206a formed by the silicon nitride material has a good blocking ability for the diffusion of water molecules and oxygen at high temperatures, no silicon oxide is generated on the surface of the silicon substrate 200 covered by the mask layer 206a. The surface not covered by the mask layer 206a is oxidized to form a polycrystalline silicon oxide layer 208 composed of silicon oxide. In addition, due to the water molecules and oxygen on the cover layer g (please read the precautions on the back before filling in this page),-
I % 本紙張尺度適用中國國家標準（CNS > Μ規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 4 3 2^2 - i7 A 7I% This paper size applies Chinese National Standard (CNS > M size (210X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 2 ^ 2-i7 A 7
5691twf.d〇c/〇〇R _____ B7 _^ ___ 五、發明説明（1) 206a角落的部份依然有能力進行水平方向的擴散，因此位 於罩幕層2〇6a角落的矽基底200，仍會產生不同程度的氧 化，而使所形成之複晶矽氧化層208的部份呈現鳥嘴的外 觀，如第2B圖所示。 請參照第2C圖，剝除罩幕層206a，以暴露出部分第一 複晶矽層204。接著，利用複晶矽氧化層208爲罩幕，穿 隧氧化層202爲蝕刻終止層，去除所暴露出的第一複晶矽 層204’以在穿隧氧化層202上形成一浮置閘204a。繼之， 再次進行熱氧化法以在浮置閘204a的側壁形成氧化間隙 壁210。然而，在形成氧化間隙壁210的步驟中，裸露之 複晶矽氧化層208與穿隧氧化層202上依舊會與氧氣和水 分子反應而生成氧化砂層，故裸露之複晶砂氧化層208會 些微變厚成爲複晶矽氧化層208a，而穿隧氧化層202亦會 些微變厚成爲厚氧化層203。其中，厚氧化層203的厚度 爲穿隧氧化層202與在氧化間隙壁210形成步驟中穿隧氧 化層202上所生成的氧化層厚度之總和，故厚氧化層203 的厚度大於穿隧氧化層202的厚度。由於複晶矽氧化層 208a與氧化間隙壁210包覆著浮置閘204a，故使得浮置 閘204a與外界呈現電性隔離的狀態。 請參照第2D圖，在基底200上沉積一層氮化層(未繪示 於圖），續進行一蝕刻步驟，例如傳統的触刻製程，以在 氧化間隙壁210側壁形成一氮化間隙壁212。由於氮化間 隙壁212形成於厚氧化層203生成之後，所以在形成氮化 間隙壁212的蝕刻過程中，會破壞厚氧化層203的品質、 9 本紙張尺度適用中國國家橾準（CMS ) Μ规格（210X297公釐） ---------------ITii--^——-}線 (請先H讀背面之注意事項再填寫本頁) :/008 :/008 A7 B7 4 3 24-6 2 5691twf 五、發明説明（¾ ) 均勻性以及減少其厚度，致使厚氧化層2〇3劣化。而由於 厚氧化層203係做爲周邊高壓元件之閘氧化層之用，故較 薄的閘極氧化層厚度將使其所能承受捕獲電荷的數目減 少，造成閘極氧化層崩潰現象的提前發生，而嚴重地影 響閘極氧化層的長期可靠度。所以厚氧化層2〇3的劣化將 會導致周邊高壓元件的效能降低。 因此，請參照第2E圖，本發明係以氮化間隙壁212爲 罩幕，利用傳統的蝕刻製程去除未被氮化間隙壁212所遮 蓋之裸露的厚氧化層203，以暴露出矽基底200，且在氧 化間隙壁210和氮化間隙壁212下方殘留厚氧化層203a。 接著，在矽基底200上再次形成一層厚氧化層214。其中， 此厚氧化層214的形成方法例如是利用熱氧化法於裸露之 矽基底200上形成氧化矽層，且其厚度視製程需要而定， 大致上與厚氧化層213a的厚度相同，大約爲200-220埃左 右。 最後，請參照第2F圖，在基底200上全面覆蓋一層第 二複晶矽層216，續定義第二複晶矽層216，以在複晶矽 氧化層208a上形成分離閘極式快閃記憶體的控制閘。其 中，分離閘極式快閃記憶體的製作更包括在基底200表面 下，浮置閘204a的側邊形成有汲極區與源極區。由於後 續製程係爲熟悉該項技藝者所知悉的技術，所以在此不 多做贅述。 由於厚氧化層203在氮化間隙壁212蝕刻過程會遭受破 壞，影響其品質、均勻性與厚度，導致厚氧化層203劣化 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (諳先閱讀背面之注意寧項再填寫本頁) 、τ 經濟部智慧財產局員工消費合作社印製 432462 A7 B7 5691twf.doc/008 五、發明説明（f ) 而造成周邊高壓元件的效能降低。因此，本發明先去除原 先的厚氧化層203，再重新於矽基底200上形成一層厚氧 化層2〇4 ’以維持厚氧化層應有的品質、均勻性與厚度， 進而保有周邊高壓元件的效能。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圔內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 經濟部智慧財產局員工消費合作社印製 張 紙 本 Μ5691twf.d〇c / 〇〇R _____ B7 _ ^ ___ V. Description of the invention (1) The part at the corner of 206a is still capable of horizontal diffusion, so the silicon substrate 200 located at the corner of the mask layer 206a is still Oxidation will occur to different degrees, so that the part of the polycrystalline silicon oxide layer 208 formed has the appearance of a bird's beak, as shown in FIG. 2B. Referring to FIG. 2C, the mask layer 206a is stripped to expose a portion of the first polycrystalline silicon layer 204. Next, using the polycrystalline silicon oxide layer 208 as a mask and the tunneling oxide layer 202 as an etch stop layer, the exposed first polycrystalline silicon layer 204 ′ is removed to form a floating gate 204 a on the tunneling oxide layer 202. . Then, the thermal oxidation method is performed again to form an oxidation spacer 210 on the side wall of the floating gate 204a. However, in the step of forming the oxidation spacer 210, the exposed polycrystalline silicon oxide layer 208 and the tunneling oxide layer 202 will still react with oxygen and water molecules to form an oxide sand layer, so the exposed polycrystalline sand oxide layer 208 will The slightly thickened layer becomes the polycrystalline silicon oxide layer 208a, and the tunneling oxide layer 202 also becomes slightly thickened to become the thick oxide layer 203. The thickness of the thick oxide layer 203 is the sum of the thickness of the tunneling oxide layer 202 and the thickness of the oxide layer generated on the tunneling oxide layer 202 in the step of forming the oxidized spacer 210. Therefore, the thickness of the thick oxide layer 203 is greater than that of the tunneling oxide layer. 202 thickness. Since the polycrystalline silicon oxide layer 208a and the oxidizing spacer 210 cover the floating gate 204a, the floating gate 204a is electrically isolated from the outside. Referring to FIG. 2D, a nitride layer (not shown) is deposited on the substrate 200, and an etching step is continued, for example, a conventional touch-etching process to form a nitride spacer 212 on the sidewall of the oxidation spacer 210. . Since the nitrided spacer 212 is formed after the thick oxide layer 203 is formed, the quality of the thick oxide layer 203 will be destroyed during the etching process to form the nitrided spacer 212. 9 This paper is applicable to China National Standards (CMS). Specifications (210X297mm) --------------- ITii-^ ——-} line (please read the precautions on the back before filling this page): / 008: / 008 A7 B7 4 3 24-6 2 5691twf V. Description of the invention (¾) The uniformity and reduction of its thickness cause the thick oxide layer 203 to deteriorate. And because the thick oxide layer 203 is used as the gate oxide layer of the surrounding high-voltage components, the thinner gate oxide layer thickness will reduce the number of trapped charges it can bear, causing the gate oxide layer to collapse in advance. , And seriously affect the long-term reliability of the gate oxide layer. Therefore, the degradation of the thick oxide layer 203 will cause the efficiency of peripheral high-voltage components to decrease. Therefore, referring to FIG. 2E, the present invention uses the nitrided spacer 212 as a mask, and uses a conventional etching process to remove the exposed thick oxide layer 203 that is not covered by the nitrided spacer 212 to expose the silicon substrate 200. A thick oxide layer 203a remains under the oxidation spacer 210 and the nitride spacer 212. Next, a thick oxide layer 214 is formed on the silicon substrate 200 again. The method for forming the thick oxide layer 214 is, for example, using a thermal oxidation method to form a silicon oxide layer on the bare silicon substrate 200. The thickness of the silicon oxide layer 214 depends on the process requirements, and is approximately the same as the thickness of the thick oxide layer 213a. About 200-220 Angstroms. Finally, referring to FIG. 2F, a second polycrystalline silicon layer 216 is completely covered on the substrate 200, and the second polycrystalline silicon layer 216 is further defined to form a split gate flash memory on the polycrystalline silicon oxide layer 208a. Control gate of the body. Among them, the fabrication of the split gate type flash memory further includes below the surface of the substrate 200, and a drain region and a source region are formed on the sides of the floating gate 204a. Since the subsequent process is a technique known to those skilled in the art, it will not be repeated here. The thick oxide layer 203 will be damaged during the etching process of the nitrided spacer 212, which will affect its quality, uniformity and thickness, which will cause the thick oxide layer 203 to deteriorate. (谙 Please read the note on the back before filling in this page), τ printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 432462 A7 B7 5691twf.doc / 008 V. Description of the invention (f) causes the efficiency of peripheral high-voltage components to decrease. Therefore, the present invention first removes the original thick oxide layer 203, and then re-forms a thick oxide layer 203 'on the silicon substrate 200 to maintain the quality, uniformity and thickness of the thick oxide layer, thereby maintaining the surrounding high-voltage components. efficacy. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
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