TWI234197B - Structure capable of effectively reducing or avoiding wire bonding crack of semiconductor device - Google Patents

Abstract

A semiconductor device structure is disclosed in the present invention. In the invention, a special via hole pattern is used to divide the inter-metal dielectric (ILD) layer into plural independent blocks so as to limit the wire-bonding crack and to lower the probability of generating crack. In addition, as one single layer of the invented via hole pattern is used, particularly when the via hole is closer to the position of the upper layer of wire bonding, it is capable of effectively reducing the generation of bonding pad crack. If two layers of the invented via hole patterns are used, the generation of bonding pad crack can be completely avoided.

Description

1234197

FIELD OF THE INVENTION The present invention relates to a semiconductor device KI θ. The invention relates to a semiconductor device that can effectively reduce or avoid wafer causes; and particularly has a cracked structure. Chip closure I causes components when wiring. [Previous technology] Modern electronic products are gradually moving towards thin on board (COB), which has become a common board connection.

Li packaging technology. The key technology of COB lies in wire connection (commonly known as Wire Bonding) and molding (Moiding), which refers to the process of packaging exposed integrated circuit chips (ic "丨" to form electronic components. The body circuit is based on technologies such as wire bonding, flip chip, or tape automatic bonding (TAB) to extend the circuit of the pot 1 / 〇 铗 package. ^ ^ During wire bonding, 'the power of wire bonding will cause trauma to conventional semiconductor devices. Figure 1A of the Ming Zhizhi' shows a schematic cross-sectional view of a conventional semiconductor device. To clearly illustrate the technical characteristics of the traditional and the present invention% All diagrams of the invention only show relevant elements. In the u figure, below the metal layer, the semiconductor element 100 has a substrate 102, a field oxide layer 104, and an inner layer " dielectric layer 106. By dopant diffusion or ion implantation In this way, an n-type or P-type semiconductor region (called N-well or p-well) is formed on the surface of a portion of the material 102, or a dual-well design including the two. In addition, a complete integrated circuit is usually composed of to make Composed of tens of thousands M0S transistor. In order to prevent adjacent said body electrically short-circuited, the electrical connection between the crystal must be adjacent to (not shown in FIG. Α of Shu) plus 3

1234197 V. Description of the invention (2) A dielectric layer for isolation is called Field Oxide (FOX) 104. The inter-layer dielectric layer (Inter-Layer Dielectric Layer) 106 is used to isolate the metal wire from the MOS device. The material is, for example, Borophosphosilicate glass with a lower Glass Transition Temperature. (Referred to as BPSG). A chemical vapor deposition (Chemical Vapor Deposition, CVD) method can be used to deposit BPSG over the substrate 102 and cover the field oxide layer 104. Then, subsequent metal layer deposition can be performed. The metal layer can be deposited in single or multiple layers, depending on the process requirements. Figure 1A is illustrated with two metal layers ’as the first metal layer (First

Metallic Layer) 108, a second metal layer 114, and a third metal layer 120. An inner metal dielectric layer for isolation between two metal layers ^ "^ 一

Metal Dielectric Layer (IMD Layer), and Via Hole for metal connection. The intermediary window is further filled with a metal such as tungsten (Tungsten, W). Therefore, in FIG. 1A, there is a first inner metal dielectric layer 110 between the first metal layer 108 and the second metal layer 114, and a plurality of First Intermediary Window 112. Between the second metal layer 114 and the third metal layer 120, there is a second inner metal dielectric layer 116, and a plurality of second intermediary windows 118. The first intermediary window 112 and the second intermediary window 118 are filled with metal tungsten to connect the metal layers. For the first inner metal dielectric layer 110 and the second inner metal dielectric layer 116 for isolation, for example, plasma chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition can be selected. (High-Density-Plasma CVD, HDP CVD)

TW1260F (Wang Hong) .ptd Page 6 1234197 V. Description of the Invention (3) Silicon Oxide (Si02) Figure 1B does not show the top view of the middle window in Figure 1A. The figure "shows the three-dimensional schematic diagram of the upper two metal layers, the inner metal dielectric layer and the intermediary window in Fig. 1A. As shown in Figs. 1B and 1C, the second intermediary window 丨 丨 8 is like a needle bed Distributed in the second inner metal dielectric layer 116. When the C0B line is connected, when the wire power (as indicated by the arrow F in FIG. 1C) is transmitted to the third inner metal layer 12 and the second inner metal below When the dielectric layer 116 is filled, the material (town) filled in the dielectric window 118 is different from the material (such as silicon oxide) of the dielectric layer 116, so the interface between the two is likely to be dislocated and cracks are formed. This is called welding. Pad crack (Crack), as shown in Figure 1C cracks 1Π, 172, 173. In addition, because the dielectric window is distributed like a needle bed in the inner dielectric, the dielectric material of the inner metal dielectric layer (such as stone oxide) ) ^ State. When the tungsten and oxidation wear interface due to the impact of the wire @ = caused by the pad crack will extend until it encounters another = surface 'as shown in Figure lc longer cracks 171 and 173. Evening, 丨

If the application product is equipped with an IC chip (IC chip), it may cause 1C of integrated electricity leakage, which will cause the battery to be used in the product. There is no electricity at this time, so how can the film have good performance? The problem of human scarring makes integrated circuit crystals an important research target. [Summary of the Invention] In view of this, the structure of the object of the present invention uses a special intermediary window # 疋 to provide a semiconductor element τ, solid pattern at k to separate the inner metal dielectric layer ’

1234197 V. Description of the invention (4) J: Establish j ′ to effectively reduce or even completely avoid welding electrodes, thereby improving product yield.

= J The first object of the present invention is to propose a knot for a semiconductor device, which can effectively reduce wire bonding cracks caused by wire bonding during chip packaging. The structure of a semiconductor element includes: a substrate; an inner two electric layer (ILD) formed on the substrate; a plurality of metal layers, in order y, on the inner layer; above the electric layer; and a plurality of metal dielectric layers. Layer (Isen), = do not form between two metal layers, where the metal dielectric layer within each frame has several via holes. Among them, the dielectric windows having at least one inner metal dielectric layer can separate the inner metal dielectric layer into a plurality of independent electric material blocks. In addition, the intermediary windows can preferably be connected to a metal layer closest to a bonding pad.

According to a second object of the present invention, a structure of a semiconductor device is proposed, which can completely avoid cracks caused by wire bonding during chip packaging. The structure of the semiconductor element includes: a substrate; an inner dielectric layer formed on the substrate; a plurality of metal layers, which are sequentially formed over the inner dielectric layer; and a plurality of inner metal dielectric layers, which are formed separately Between the two metal layers, each of the inner metal dielectric layers has a plurality of intervening windows. Among them, there are at least two intermediary windows with a metal dielectric layer inside, which can separate the metal dielectric layer into a plurality of independent dielectric material blocks. And preferably, the dielectric window of one of the metal dielectric layers can be connected to the metal layer closest to the pad. [Embodiment] The present invention is to change the structure of an intermediary window in a semiconductor device, using a special diagram

TW1260F (wanghong) .ptd " page 8 ---- 1234197

In the case, the Via Hole uses a separate block of dielectric material to avoid stretching. In the following two preferred embodiments, a single layer of the special intermediary of the present invention is used to achieve the purpose of effectively reducing cracks in the pads. The special intermediary window of the present invention and the inner metal are free of cracks in the pads. In addition, only relevant components are shown in the figure. The metal dielectric layer (IMD) is divided into a plurality of extensions of pad cracks in the case of non-wiring, which will be described in detail. The first embodiment relates to the structure of the window and the inner metal dielectric layer. The second embodiment uses a double-layered dielectric layer structure to completely avoid the technical differences of the present invention. One embodiment, > Please refer to FIG. 2, which illustrates a first implementation according to the present invention. Example is a three-dimensional schematic view of a semiconductor device. In Fig. 2, under the metal layer, the half-V body element 200 has a substrate 202, a field oxide layer 204, and an inner dielectric layer 206. Using dopant diffusion or ion implantation, the surface of part of the substrate 202 may form n-type or P-type semiconductor regions (known as v-well or p-well), or a dual-well design that includes both. Field Oxide (FOX) 204 is a dielectric layer used to isolate adjacent transistors (not shown in Figure 2). The inner-layer dielectric layer (Inter-Layer Dielectric Layer, ILD Layer) 20 6 is used to isolate the metal wire from the M OS element, and the material is, for example, a side-filled stone glass with a lower Glass Transition Temperature ( Borophosphosilicate glass (hereinafter referred to as BPSG). A chemical vapor deposition (CVD) method can be used to deposit BPSG over the substrate 202 and cover the field oxide layer 204. Then, subsequent metal layer deposition can be performed.

TW1260F (wanghong) .ptd Page 9 1234197 V. Description of the invention (6) The metal layer can be deposited in single or multiple layers, depending on the process requirements. In this embodiment, three metal layers are used for description, namely a first metal layer 20 8, a second metal layer 214 and a third metal layer 220. And between the two metal layers there is an inner metal dielectric layer (Inter-Metal Dielectric Layer, IMD Layer) for isolation, and an intermediary window (Via Hole) for metal connection. The intermediary window is also filled with a metal such as a crane (Tungsten, W). In the second figure, there is a first inner metal dielectric layer 210 between the first metal layer 208 and the second metal layer 214, and a plurality of first intermediary windows. 212. There is a second inner metal dielectric layer 216 between the second metal layer 214 and the third metal layer 220, and a plurality of second intermediary windows 218. The first intermediary window 212 and the second intermediary window 218 are both filled with metal tungsten to connect the metal layers. The first inner metal dielectric layer 210 and the second inner metal dielectric layer 2 1 6 ′ for isolation may be, for example, electro-chemical vapor deposition (p 1 asma —j; nhanc e (j CVD, PECVD), Or high density plasma chemical vapor deposition (High-Density-Plasma CVD (HDP CVD)) deposited silicon oxide (Si 1 icon Oxide (Si02)) 〇 In the first embodiment, a layer of metal The interlayer window with a special graphic design in the electrical layer is used for illustration. Among them, the closer the position of the metal dielectric layer is to the bonding line, the better the effect of preventing pad cracks. Here, the first The second intermediary window 218 in the two inner metal dielectric layers 216 will be described. As shown in FIG. 2, the upper surface of the second intermediary window 218 is formed with a special pattern like a checkerboard, and the second inner metal is dielectric. Segment 216 is plural

1234197 V. Description of the invention (7) ^-~ independent blocks of dielectric material. It was confirmed by experimental results that the report passed to the second inner metal dielectric layer 216_, even if it was a second force intermediary window 218 (filled with tungsten) and the dielectric layer 216 (silicon oxide) of different second materials. The interface is dislocated due to different materials, and it will be limited to a small piece of independent electrical material, which will not extend around, so it can effectively reduce the pad cracks caused by wire bonding. Of course, the dielectric window pattern in the present invention is not limited to the checkerboard pattern as shown in FIG. 2, such as figures such as zigzag pattern, water ripple, spider web, etc., as long as the inner metal dielectric layer can be separated into a plurality of numbers The patterns of the individual dielectric blocks conform to the technical features of the present invention. ^ Second Embodiment The semiconductor device structure of the second embodiment is substantially the same as that of the first embodiment, except that the second embodiment is a structure in which two layers of the special dielectric window and the inner metal dielectric layer of the present invention are applied. And the experimental results confirm that the second embodiment can achieve the purpose of completely avoiding cracks in the pads. Please refer to FIG. 3, which is a schematic perspective view of a part of a semiconductor device according to a second embodiment of the present invention. The same parts as those in Fig. 2 are given the same reference numerals. Below the metal layer, the semiconductor device 300 also has a substrate 202, a field oxide layer 204, and an inner dielectric layer 206. The inner dielectric layer 206 is, for example, borophosphosilicate glass (BPSG) deposited by a chemical vapor deposition (CVD) method. The metal layer can be deposited in single or multiple layers, depending on the process requirements. In this embodiment, three metal layers are also used for description, namely the first metal layer 208 ', the second metal layer 214, and the third metal layer 22o.

TW1260F (Wang Hong) .ptd Page 11 1234197 V. Description of the invention (8) There is a first internal metal dielectric layer (First IMD layer) 210 between the first metal layer 208 and the second metal layer 214, and a plurality of First Intermediary Window 312. Between the first metal layer 214 and the second metal layer 220, there is a second internal metal dielectric layer (Second IMD layer) 216, and a plurality of second intermediary windows 318. The first intermediary window 312 and the second intermediary window 318 are both filled with a metal crane Γ to connect the metal layers. The first inner metal dielectric layer 21 and the second inner metal dielectric layer 216 for isolation can be selected by plasma chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition (HDp CVD). Deposited silicon oxide (S i 02). 'side,

In the second embodiment, the median window pattern of the zigzag pattern is used for description. The upper and lower layers of the metal dielectric layer are separated into a plurality of independent dielectric blocks, thus increasing the stress area during wire bonding, thereby reducing the stress on the material. And the experimental results have confirmed that: the intermediary window with a special pattern can completely avoid the occurrence of cracks in the pads. However, the present invention does not use the zigzag pattern in FIG. 3 as the others. Others, such as FIG. 2 Checkerboard patterns, water ripples, insect spider webs and other graphics are also available. The patterns capable of separating the inner metal dielectric layer into a plurality of independent dielectric materials all conform to the technical features of the present invention. In addition, in practical applications, the number of metal layers may be more than two internal metal dielectric layers. However, at 5: 2, the two crimes in the metal dielectric sound within the two layers of the wire are close to completely avoid the pad cracks. In addition, the figures formed by the first intermediary window 312 and the second intermediary window 31 may be the same or different. The shape of the upper surface of the

TW1260F (Wanghong) .ptd Page 12 1234197

Yes: For $, as long as both of them can identify the block of dielectric material in which it is located, it can be recognized as ..., or misaligned (such as slightly staggered). … Octagenus; 丨 the electrical layer is divided into a plurality of separates, completely avoiding & • Hong Nong (Wire-Bonding two-layer traditional needle-shaped interposer (control group) Experiment 1 Doze i There are two layers of traditional semiconductor devices such as pin-shaped interposer. The structure is shown in Figures 1A ~ lc. This experiment is to use the conditional parameters of the line date ^ to observe whether the welding cracks have reduced. The experimental fruit is shown in Table 1. Table sample test ------- wire Participant test results: Power, Force, Time, Zinc pad crack tensile test "85mw 30g 20ms Occurred-2--___ 95mw 3〇g 20ms Serious-3 75mw 26g 20ms Occurred_ 4 70mw 25g Occurr Passd Pass 5 70mw 20g Occurred Fail 6 60mw 25g. Occurred Fail 7 60mw 2〇g Like Less Fail *: The current standard parameter value

TW1260F (Wang Hong) .ptd Page 13 1234197 V. Description of the Invention (1) 1 ---- ^ The experimental results show that the increase of the threading force will produce more cracks, and the lower threading force Ϊ y will reduce the cracks, but There are side effects that cannot be linked. Therefore, changing the wiring parameters of soap can not improve the condition of the pad crack. It is advisable to perform a wiring experiment on a semiconductor device having a layer of a special patterned interposer according to the present invention. Please refer to Figure 2 for component structure. In this experiment, a single-layer dielectric window pattern was used to separate the inner metal dielectric layer into multiple independent blocks to observe whether the pad cracks were reduced. The experimental results are shown in Table 2. Among them, the pattern l (Pat · υ ~ pattern 12 (Pat · 12)) in the sample number corresponds to the fourth person ~ 41, and represents the top view of the uppermost intermediary window. In the 4A ~ 4L, the fruit color part ^ Represents the intermediary window filled with metal, and the self-colored part represents, for example, the inner dielectric layer of oxygen. And the intermediary window patterns in Figures 4B to 4F are checkerboard-shaped, except for the independent dielectric block and the width of the intermediary window Different. Sentence is

TW1260F (Wang Hong) .ptd Page 14 1234197 Five 'invention description (11) Pin tt wire line Pat. 1 Pat. 2 Pat. 3 P at. 4 Pat. 5 Pat. 6 Pat. 7 P at. 8 Pat. 9 Pat. 10 Pat. 11 Pat. 12 100m w / 3 0 g 8/8 cracke 2/12 5/12 3/12 3/12 8/12 11/12 6/8 10/12 8/12 4/8 4/8 90m w / 30g 8/8 4/12 5/12 2/12 5/12 10/12 10/12 8/8 8/12 6/12 7/8 7/8 80m w / 3 0 g * 8/8 0/12 0/1 2 0/12 0/12 6/12 10/12 6/8 4/12 4/12 4/8 2/8 100m w / 2 0 g 8/8 7/12 6 / 12 4/12 8/12 9/12 1 2/1 2 6/8 11/12 1 2Π2 6/8 8/8 90m w / 3 0 g 6/8 6/12 6/12 1/12 3 / 12 8/12 11/12 6/8 12/12 10/12 7/8 7/8 80m w / 3 0 g 4/8 1/12 5/1 2 2/12 peeling 1/12 4/12 11 / 12 5/8 peeling 11/12 10/12 4/8 5/8 Sample number Pat.2: A = 0.6 / zm, B = 2 // m Sample number Pat.3 · A = 1 / z id, B = 2 // in Sample number Pat · 4: A = 2 // m, B = 2 // m Sample number Pat. 5: A = 0.6 // m, B = 1 μm Sample number Pat. 6: A = l // m, B = 1 // m *: The current standard parameter value for wire making. The experimental results are expressed as (the number of welds with cracks / the total number of welds). It is known from the experimental results that when using a single layer having the * of the present invention, the cracks in the metal dielectric layer therein can be effectively effectively reduced. ; 1 self-explanatory. Three or two layers of the intermediate window with a special pattern according to the present invention are tested. Refer to Figure 3 for component structure. , Semiconductor element + is used

1234197 V. Description of the invention (12) The double layer has an intermediary window with the same special pattern to observe the condition of the pad cracks. The experimental results are shown in Table 3. Similarly, pattern 1 (Pat · 1) to pattern 12 (Pat. 12) in the sample number correspond to Figures 4A to 4L and represent the top view of the intermediary window. In Figs. 4A to 4L, the dark portion represents the dielectric window filled with metal tungsten, and the white portion represents, for example, the metal dielectric layer within the oxide. In addition, the graphs of the dielectric windows in Figures 4B to 4F are all in a checkerboard pattern, except that the widths of the individual dielectric blocks and the dielectric windows are different.表 三 打 线 参 Pat. 1 Pat. 2 Pat. 3 P at. 4 Pat. 5 P at. 6 P at. 7 Pat. 8 Pat. 9 Pat. 10 Pat. 11 Pat. 12 70m w / 3 0 g 4 / 6 0/49 0/49 peeling 0/9 0/9 0/9 4/6 peeling 0/9 5/9 0/9 2/6 80m w / 3 0 g * 2/6 0/49 0/49 0/9 0/9 5/9 0/9 6/9 0/9 0/6 9 0m w / 3 0 g * 4/6 0/49 0/49 0/9 0/9 6/9 0/9 5/9 0/9 0/6 70m w / 20g 3/6 0M9 0/49 0/9 0/9 7/9 0/9 8/9 0/9 0/6 80m w / 20g 4/6 0 / 49 0M9 0/9 0/9 5/9 0/9 9/9 0/9 3/6 90m w / 2 0g 6/6 0/49 0/49 0/9 0/9 9/9 0/9 9 / 9 0/9 3/6 Sample number Pat.2: A = 0. 6 // m, B = 2 // m Sample number Pat · 3 · A = 1 μ m, B = 2 // m Sample number Pat .4 · A = 2 // m, B = 2 // m sample number Pat · 54 = 0.6 // 111, B = 1 // m sample number Pat. 6 · A = 1 // m, B = 1 / / m *: The current standard parameter value for wire bonding.

TW1260F (Wang Hong) .ptd Page 16 1234197 V. Description of the invention (13) The results of the steam test are expressed as (the number of pads with cracks / the total number of pads). It is known from the experimental results that the pattern 2, 3, 5, 6, q,. The invention can separate the inner metal dielectric layer into a plurality of sentences. It conforms to this ^ after wiring, there is no crack = = Window: A crack in the electrical layer. In order to avoid the limitation of the metal interlayer through the above metal dielectric layer, the intermediary window pattern can effectively clarify the intermediary window pattern. The present invention can be summarized as described above. As for the protection of the invention, it is known that the present invention can reduce the number of cracks, especially the local reduction of welding shape, which can be greatly improved by half. Although the present invention is made within the scope of this invention, when it is used as an accessory, The block, the raw machine, and the intermediary cracks are completely avoided by the conductor. Yuan Ming has applied any special method to make it special, so as to make the rate of hitting. And the closer the window should be generated. If the yield rate of welding cracks is better to implement the modification of this technique, the scope of the patent, the single-layer layer is used to create the exposed example, and the internal crack layer is defined by the retouching. The present invention has two layers of hair. Therefore, I ’m not out of this, so I will prevail.

1234197 Brief description of the drawings [Simplified description of the drawings] Figure 1A shows a conventional part of a semiconductor device; Sectional view shows the top view of the intermediary window in Figure 1A; Figure 1C shows the 1A 3D schematic diagram of an intermediary window in the figure; FIG. 2 illustrates a schematic diagram of a part according to the first embodiment of the present invention; 'ya7L FIG. 3 illustrates a schematic diagram of a part and a half according to the second embodiment of the present invention; and π 7L, 4A ~ 4L are top views corresponding to the sample numbers of experiments 2 and 3. ; | The upper two metal layers, the inner metal dielectric layer and the component window pattern label description 100, 200, 300: semiconductor element 1 0 2, 2 0 2: substrate 104, 204: field oxide layer (fox) 106 : 206: inner dielectric layer (ild) 108, 208: first metal layer 110, 210: first inner metal dielectric layer (First 10) 112, 212, 312: first dielectric window 114, 214: second Metal layers 116, 216: second inner metal dielectric layers 118, 218, 318: second intermediary window

TW1260F (Wang Hong) .ptd Page 18 1234197 Brief description of the drawings 120, 220 · · Third metal layer 171, 172, 173: Pad crack

I Page 19 TW1260F (Wanghong) .ptd

Claims (1)

1234197 VI. Scope of patent application 1 · A semiconductor device structure can effectively reduce the wire bonding cracking caused by wire bonding during chip packaging. The structure of the semiconductor device includes: a substrate; an inner dielectric layer ( Inter-Layer Dielectric Layer (ILD Layer) is formed on the substrate; a first metal layer is formed on the inner dielectric layer; a first metal layer is located above the first metal layer, and the first There is a first inner metal dielectric layer between the metal layer and the second metal layer (a Metal Dielectric layer, IMD layer), and the first inner metal dielectric layer has a plurality of first via holes (First Via Hole ); And a third metal layer located above the second metal layer, and a second internal metal dielectric layer (Inter-Metal Dielectric Layer, IMD Layer) between the second metal layer and the third metal layer, And the second inner metal dielectric layer has a plurality of second via holes; the second inner metal dielectric layer is formed by a special pattern formed on the upper surface of the second intermediary windows. A plurality of separate compartments for the dielectric block material, while effective to reduce wire breakage caused. 2. The structure as described in item 1 of the scope of patent application, wherein the line ratio of the second intermediary windows to the inner metal dielectric layer is greater than the first dielectric windows and the first inner metal dielectric layer Line proportions. 3. The structure according to item 1 of the scope of patent application, wherein the substrate is a silicon substrate. 4. The structure described in item 1 of the scope of patent application, wherein the inner layer TW1260F (Wang Hong) .ptd Page 20 1234197 6. Scope of patent application The electric layer is a borophosphosilicate glass (BPSG). = 5 · The structure as described in item 1 of the scope of patent application, wherein a field oxide layer (Field — OXide Layer) is provided between the substrate and the inner dielectric layer. 86. The structure described in item 1 of the scope of patent application, wherein the materials of the first inner metal dielectric layer and the second inner metal dielectric layer are both silicon oxide (Silicon Oxide). 7. The structure described in item 1 of the declaration of patent scope, the first one of the middle :) the intermediate window and the second intermediate windows are filled with the material u (Tu; Specially refers to the structure described in item 1 where the second surfaces form a checkerboard pattern. Among them, the second, among the first, among which the others are covered. The surname M Ί nf described in item 1 forms a sub-pattern pattern. -Medium A & ^ mentioned in item 1 of the scope of patent application ^ A structure on the upper surface of the intermediary window is 11 as shown by 1 * $ Form a water ripple pattern. The first and second intermediary windows in the middle-month patent scope are on the table, and the structure described in / item 1 forms a spider web pattern. ^, The structure of the cattle conductor element can be broken, each of which can be broken, in which, except for the chip packaging when the chip is packaged; the structure of the body 7 " includes: a dielectric layer ( ILD Uye〇 Two, a metal layer is formed on the inner layer and formed on the substrate; the layer is above the first and second metal layers, There is a first internal metal dielectric layer (IMD TW1260F (Wang Hong) .ptd ms on page 21 1234197) between the metal layer and the second metal 屦 μ '屦 Α metal layer. Range layer), and the first inner metal dielectric layer has a plurality of first via holes; and a third metal layer is located above the second metal layer, and the second metal layer and the first metal layer There is a second inner metal dielectric layer (IMD Layer) between the three metal layers, and the second inner metal dielectric layer has a plurality of second intermediary windows (Second Via Holes); The first inner metal dielectric layer is separated into a plurality of independent first dielectric material blocks, and the second intermediary windows are used to separate the second inner metal dielectric layer into a plurality of independent second dielectrics. Material block. 13. The structure described in item 12 of the scope of patent application, wherein the positions of the second intermediary windows are stacked directly above the positions of the first intermediary windows. 14. If the scope of patent application The structure according to item 12, wherein the positions of the second intermediate windows and the second intermediate windows are The positions of an intermediary window are misaligned. 15. The structure described in item 12 of the scope of patent application, wherein the upper surface of the first intermediary windows forms a first special pattern, and the second intermediary windows are The upper surface is formed with a second special pattern. 16. The structure described in item 13 of the scope of patent application, wherein the first special pattern is the same as the second special pattern. 17. As item 16 of the scope of patent application In the structure, the first special figure and the second special figure are a checkerboard figure. 18. The structure described in item 16 of the scope of patent application, wherein the first TW1260F (Wanghong) .ptd Page 22 1234197 6. Scope of patent application The special pattern and the second special pattern are / back pattern. 19. The structure described in item 16 of the scope of patent application, wherein the first special pattern and the second special pattern are a water ripple pattern. 2 0. The structure as described in item 16 of the scope of the patent application, wherein the first special pattern and the special pattern are a spider web pattern. 21. The structure as described in item 12 of the scope of patent application, wherein the substrate is a silicon substrate, and the inner dielectric layer is a rural phosphorous silicon glass (BPSG). 2 2 · The structure as described in item 12 of the scope of patent application, wherein there is a field-oxide layer between the substrate and the inner dielectric layer 〇 2 3 · As item 12 of the scope of patent application The structure, wherein the materials of the first inner metal dielectric layer and the second inner metal dielectric layer are both Silicon Oxide 〇24. The structure according to item 12 in the scope of patent application, wherein The first intermediary windows and the second intermediary windows are filled with a material tungsten, W) 〇25 · —a structure of a semiconductor device, which can effectively reduce the wire packaging cracks caused by wire bonding (Wire Bonding Crack). Among them, = The structure of the semiconductor element includes: eight 'the one substrate; an inner dielectric layer (ILD Layer) formed on the substrate; a plurality of metal layers' are sequentially formed over the inner dielectric layer. Metal dielectric layer (IMD layer) TW1260F (Wang Hong) .ptd Page 23 1234197 VI. Patent application scope 'a'-between metal layers, where each inner metal dielectric layer has a plurality of via holes; at least one inner metal layer The dielectric windows of the dielectric layer can separate the metal dielectric layer in the dielectric layer into a plurality of independent dielectric material blocks, and the dielectric windows can be connected to the metal layer closest to the bonding pad. 26. The structure as described in item 25 of the scope of patent application, wherein the line ratio of the metal dielectric layer with the independent dielectric material blocks to the dielectric windows is greater than that without the independent dielectric material blocks. Line ratio of other metal dielectric layers to their intervening windows. Person 27. The structure described in item 25 of the scope of patent application, wherein the inner dielectric layer is a borophosphosilicate glass (BPSG), and there is a field oxide layer between the substrate and the inner dielectric layer (Field- Oxide Layer). 28. The structure described in item 25 of the scope of patent application, wherein the material of the inner electric layers is silicon oxide (Silicon Oxide), and the intermediary windows are filled with tungsten (Tungsten, W). A certain 29. The structure as described in item 25 of the scope of the patent application, wherein the two metal dielectric layers can be separated into the independent dielectric material blocks, and the upper surfaces of the intermediaries are formed as one. Special graphics. 30. The structure as described in item 29 of the scope of patent application, wherein the special pattern is a checkerboard pattern. 31. The structure as described in item 29 of the scope of the patent application, wherein the special pattern is A ^ Ma Yi zigzag pattern. 32. The structure described in item 29 of the scope of patent application, wherein the special 圚 -shaped system 1 is a water ripple pattern. 1234197, patent application scope 3 3 · The structure described in item 29 of the patent application scope, in which the special picture is opened) / / is a spider web figure. 34 · — A kind of semiconductor device structure, which can avoid wire bonding cracking caused by wire bonding during chip packaging. “Among them” the structure of 70 semiconductors includes: a substrate; ~ an inner dielectric layer (ILD Layer), Formed on the substrate; a plurality of metal layers are sequentially formed over the inner dielectric layer; and a plurality of inner metal dielectric layers (10layer) are formed between two metal layers, each of which The inner metal dielectric layer has a plurality of intermediary windows (Via Holle); the intermediary windows having at least two inner metal dielectric layers can 'separate the inner metal " electric layer into a plurality of independent dielectrics Discussing blocks. 35. The structure described in item 34 of the scope of patent application, wherein an n-th layer (Ji is a large positive integer, η-2) and a plurality of η-layer intermediaries of a (η-1) metal dielectric layer Window and (η-1) layer intervening window, the metal dielectric layer inside can be separated into a plurality of independent dielectric material blocks, and the η layer intermediary window and the (η-1) layer intermediary window can be established The upper surface forms a first intermediary window pattern and a second intermediary window pattern, respectively. 36. The structure according to item 35 of the scope of application for a patent, wherein the positions of the n-level intermediary windows are stacked directly above the positions of the (n-1) intermediary windows. 々37. The structure described in item 35 of the scope of patent application, wherein the positions of the 11th layer intermediary windows and the positions of the (η-1) layer intermediary windows are related 1234197 6. Scope of patent application 38. The structure as described in claim 35, wherein the first intermediary window pattern is the same as the second intermediary window pattern. 39. The structure described in item 38 of the scope of patent application, wherein the first intermediary window pattern and the second intermediary window pattern are a chessboard. 40. The structure described in item 38 of the patent application scope Structure, wherein the first intermediary window pattern and the second intermediary window pattern are a concentric frame ° 41 · The structure described in item 38 of the scope of patent application, wherein the first intermediary window pattern And the second intermediary window pattern is a concentric circles ° 4 2 · The structure as described in item 38 of the patent application scope, wherein the first intermediary window pattern and the second intermediary window pattern are One! The spider web is known as the structure described in item 34 of the scope of patent application, wherein the inner dielectric layer is a borophosphosilicate glass (BPSG), and the substrate and the inner layer are dielectric. There is a Field-Oxide Layer between the layers. 44. The structure described in item 34 of the scope of patent application, wherein the material of the inner metal dielectric layers is Silicon Oxide, and the dielectric windows are filled with tungsten (Tungsten, W). 4 5 · —Structure of a semiconductor device, which can avoid wire bonding cracking caused by wire bonding during chip packaging. 'Where' the structure of the semiconductor device includes: TW1260F (Wang Hong) .ptd Page 26 1234197 Six patent application scopes a substrate; an inner dielectric layer (ILD Layer) formed on the substrate · multiple metal layers, which are sequentially formed on the inner dielectric layer Top · A plurality of inner metal dielectric layers (IMD layers), which are respectively formed between the metal layers, and each of the inner metal dielectric layers has a plurality of Via Holes; ® at least two inner metal dielectric layers The layer has a plurality of independent dielectric material blocks, and the intermediary windows of one of the metal dielectric layers can be connected to the metal layer closest to the Bonding pad. 46. The structure described in item 45 of the scope of patent application, wherein the line ratio of the metal dielectric layer with the independent dielectric material blocks to the dielectric windows is greater than that without the independent dielectric. Line ratio of the other metal dielectric layers of the material block to its intervening windows. 47. The structure according to item 45 of the scope of the patent application, wherein the independent dielectric material blocks respectively located in at least two metal dielectric layers are aligned up and down. 48. The structure according to item 45 of the scope of the patent application, wherein the positions of the independent dielectric material blocks respectively located in at least two metal dielectric layers are slightly shifted from each other. 49. The structure according to item 45 of the scope of patent application, wherein a plurality of independent dielectric material blocks located in at least two metal dielectric layers each have a first dielectric block pattern and a first Two dielectric block graphics. 50. The structure described in item 49 of the scope of patent application, in which the first country TW1260F (Wang Hong) .ptd page 27 1234197 VI. The scope of the patent application dielectric block pattern and the second dielectric block pattern are the same. 51. The structure described in item 50 of the scope of patent application, wherein the first dielectric block pattern and the second dielectric block pattern include a plurality of independent rectangular rectangular (isolated and rectangular IMD blocks) ° 52. The structure described in item 50 of the scope of the patent application, wherein the first dielectric block pattern and the second dielectric block pattern include a plurality of independent and concentric IMD frames. 53. The structure described in item 50 of the scope of the patent application, wherein the first dielectric block pattern and the second dielectric block pattern include a plurality of independent and concentric IMD circles. 54. The structure described in item 50 of the scope of the patent application, wherein the first dielectric block pattern and the second dielectric block pattern include a plurality of independent and honeycombed IMD blocks. 55. The structure described in item 45 of the scope of patent application, wherein the inner dielectric layer is phosgene glass (BPSG) on one side, and there is a field oxide layer between the substrate and the inner dielectric layer (Field- Oxide Layer). 56. The structure according to item 45 of the scope of the patent application, wherein the material of the inner metal dielectric layers is Silicon Oxide, and the dielectric windows are filled with tungsten (Tungsten, W). TW1260F (Wang Hong) .ptd Page 28