TWI233020B - A computer system with multi-specification transmission channel compatible - Google Patents

Abstract

A computer system which adopts a memory bus with a plurality of specifications of transmission channel, and that system includes a CPU, a north bridge chip, which connects to the CPU with FSB, a system memory, which connects to the north bridge chip with multi-specification transmission channel, a VGA module, which connects to the north bridge chip with AGP bus, a south bridge, which connects a plurality of communication ports. The system memory mentioned above is compatible with a plurality of specifications.

Description

1233020

V. Description of the Invention (1) [Technical Field] The present invention relates to the computer department

Compatible with multiple specifications of transmission channels, the structure of the connection bus uses a computer system with QBM specifications of the transmission channel. Don't worry about it—a kind of compatible DM. [Previous technology] μ # 〇 In current or conventional technology, because

The processing speed of the processing unit CPU (Cen Qira 1 1 ο. ^ ^. 'Is much faster than this central processing early system and system memory (that is, the moving bear is also larger than the central processing bank (bU "Data transfer speed, γΛΛ memory, DiLAM.) The access to the system memory at any time < when Wang Zao 70 is processing shellfish, it must be done in Shanghai, V tear red alone 丨 丨 * Therefore, in order to improve the effectiveness of the overall computer system, it is necessary to make improvements to the buses of poor materials. In terms of the current general architecture, the internal structure of the social system is a schematic diagram: Q; Management of all kinds of information in the overall computer system: the brain architecture includes a central processing unit 11 that handles a few differences in data, central = logical early, 11 by the 12th connection system, unified memory 13 and other peripheral elements 4. This first chip 12 is commonly used as a common bridge chip (n0 "h bridge Chip) in the chipset, and the first system bus 101 of the central processing unit 11 and the first chip 12 is called It is a front-end system bus (fr0nt side bus), the first chip 1 A memory controller is provided in 2. The memory controller is connected to the system memory 1 2 by the second system bus 1 102. Currently, most of the current data rates are 64% of the double-bit data rate (Doubl e Data Rate, DDR) bus to connect, the system memory 13 is a memory module (D0ub) e with a double data transmission rate.

Data Rate-Synchronous DRAM (DDR-SDRAM), the first chip 12 and the third system bus 103 are used to access data to the graphics card module

Page 5 I ·· V. Description of the invention (2) 1 4 'This third system bus 1 03 is currently the bus of the Accelerated Graphic Port (AGp), the graphics acceleration port is a computer A slot on the motherboard interface is designed for graphics cards with graphics acceleration ports. Its function is to transfer image information between the central processing unit and the graphics card. The first chip 12 is also connected to the second chip 6 through a fourth system bus 104. This fourth system bus 4 is currently based on the Hub Link technology proposed by Intel a, VIA Implementation of V-Link, AMD ’s Hyper Transport, etc., and Intel ’s △ Division promoted PC I Express to replace these non-physical buses, and unified the standards of buses, and AMD also raised Similar technology of AHyper Transport. This second chip 16 is commonly used as the south bridge chip js ^ uth bridge chip commonly used in the chipset, and is connected and controlled by the second chip 16 to peripherals 2, such as keyboards, mice and other peripheral devices 17, such as disk control ... Controllers, floppy disk controllers, and other peripheral storage devices are more complex. Port 19, such as serial port (serial port), parallel bee (parauei face% H bus) (USB), and more Various expansion buses connected to computer systems, such as sound cards, network cards, and other peripheral components. P = bur) (eHPh⑽1 GGmp ° nent Heart and dirty heart US, is the second illustration of the internal structure of the computer system of the conventional technology 13 之 ； 二;:; The structure is the same as that in the first picture, only the control system memory is set in the central processing unit 11, and the fifth system transfers the data ^ now 仃 64-bit double data transmission speed ㈣ To connect with the bus, 1233020 V. Description of the invention (3) Or you can use the synchronous random random number ^-system bus 101 to § itself: hidden body (let M) to implement. Use the system bus 103 to Give = ί system bus (FSB) implementation, the third -Γ, / speed connection Tan bus (agp) Ξ ^: f The third schematic diagram of the internal structure of the computer system used in the conventional technology. The second module 14 is connected, and the n / e system bus 103 is connected to the display card 100, and the system bus 106 is connected to a frame. The register buffer (ra ^ ie buffer) 31, the fifth system bus 0 bus is implemented, and the display card module U of the frame register bank is additionally ^. In order to make U accelerate the connection and converge, the fourth picture is the fourth sound chart of the internal architecture of the computer system of conventional technology. This picture shows the memory controller moved from the first chip 12 to the center: Rizhao Wu 11, And the seventh system bus 107 is connected to the control system memory; 3, seven system bus: 107 is currently implemented as a 64-bit double data stream, where the central processing unit u and the first chip 12 are connected. The first unified bus 1 10 is implemented as a front-end system bus. The first chip—the 2nd, the sixth system bus of the register 3 1 丨 〇6 is currently a 64-bit double-speed bus. Implementation, the system bus 10 connecting the first chip 12 and the graphics card module 14 is connected to the bus by drawing to accelerate the implementation. One of the above-mentioned 2 current computer motherboard architectures, the first chip called the North Bridge chip, a 12-t acceleration port bus connection to the graphics card module 14, and a 64: multiplied rate bus connected to the system memory 13 The "central processing unit η" such as "the register 31" is also provided with a memory controller to 64 1233020 V. Description of the invention (4) System: Connect the system memory 13. The present invention 12 and the system memory 13 The computer system connected to the drama channel is connected to the first chip 13 to change the central processing unit u and the system memory. [Content of the invention] 1. Find a target. The present invention is a computer system with evening green system. Two = phase transmission channel of the computer is a capacitive transmission channel connection system and chipset using a variety of specifications. The computer system includes: 1 ^ central; management M _ hunting system bus connection center ^ m early, — Northbridge chip, wrong with a variety of specifications compatibility # 二 早 70, — System memory, a graphics card module, pass: 11 wooden structure of the bus connected to the Northbridge chip; [Power of the bus connected to the North Bridge crystal connection computer system Uniform peripheral equipment: connect 5 north bridge chip 'south bridge chip and compatible transmission channel _ heart = several ports, of which there are multiple specifications modules. The structure of the bus can connect several different specifications of memory. This computer system includes Yes ·· One middle school · Borrowing a front-end system to produce production schedules, tables, and early-morning, one Northbridge chip, borrowing-a variety of rules 二 f two central processing units; one system memory, system unit, one display ^ The bus of the valley transmission channel structure is connected to the central processing single-bridge chip. "Second South Two: The bus from the graphics acceleration port is connected to the north chip and the computer; it is connected to the north bridge chip through the interface bus. The capacitive transmission wheel is connected to several cockroaches, among them, a variety of memory modules. The bus of Daomu structure can be connected to several different specifications. Page 8 1233020 A bus chip with a central front-end bus north bridge chip, a bridge chip with multiple specifications or a schematic diagram of the present invention, central processing of the brain system Single-memory memory 52) and two kinds of transmission channels with multiple specifications are compatible, including the central processing unit, the north bridge chip and the south bridge central processing unit, the south bridge chip is called a chip, and the traditional memory is There are multiple = buses connected to the Northbridge chip or the central processing unit. See the memory module. This bus can be used to connect the Northbridge chip or S5. Description of the invention (5) [Implementation content] The present invention is a disclosure system, this computer system tablet, Northbridge The chip is connected to the grid-compatible transmission channel by another bus so that the central processing units of different specifications can be used. The present invention is a disclosure system. The computer system chip 'Northbridge chip connects grid-compatible transmission channels with another bus and the frame register uses another Northbridge chip.' The first shown architecture of the computer system is the first side of the first system 1 2 and the system 5 1 and the second system memory and the first system 12 of the first chip 12 in the calculation of electrical information and data. The computer processing unit, north bridge chip and south bridge crystal bar of various specifications compatible transmission channels are connected to the central processing unit and south bridge chip, and the system memory is connected to the north bridge chip or central processing unit with a variety of specifications. The bus connection memory module and frame register can be borrowed from the central processing unit. That is, the first pass with multiple specifications is compatible with the transfer channel. The first structure shown in the figure is like conventional technology, which includes the processing unit (CPU) 11, and the central processing unit u (including the first system in the figure). The memory is connected to other peripherals. The central processing unit ^ ^ 101 is a front-end system bus chip 12. A memory controller is set in the first.

Page 9 1233020 V. Description of the invention (6) It is connected to the system memory (51, 52) with a bus that is compatible with multiple specifications of transmission channels. The 501 is compatible with the brother ’s little huddle wheel channel bus 502, among which the plurality of buses are compatible with the conventional 64-bit double data rate (Double Data Rate, DDR two buses). This is a combination of multi-band memory and multi-bandwidth memory technology. For this, Vt-band wide-body technology is used. The present invention is a 64-bit double data transmission rate (Double Data) using quad-band memory technology Uuad band memory (QBM) Rate (DDR) bus. The above-mentioned computers with multiple specifications compatible transmission channels are designed to improve the rapid production of the popular computer architecture motherboards, buses, and transmission wheels. Mu Ming borrowed the first chip from the central processing unit ii! 2 and the first The first series: The second system uses multiple transmission channels between the memory 52 and f51 /, and supports the 64-bit double data transfer rate, which can be used with the same memory technology ( QBM) memory. This and many ”four-bandwidth computer M is improved in the existing dual-transport (_-SDRAM) architecture, and the system memory system data frequency is increased without increasing the number of input modules. , And the n-rate conditional system ’s transmission line between memory and the conventional usage: Medium :: the memory element of the unit and the rate 'Therefore, this computer system also has a clock frequency that makes the design of the high-speed transfer wheel that realizes the data bus more convenient. ; = Recognizing leaves, frequency, this high-speed, cost-effective, and scalable solution, ^ $ will realize a contradiction between increased processing power and memory bandwidth. ; · Number of operations to be prepared

Page 10 Principles of the Technology Structure of Quadruple Bandwidth Memory 1 Wood 1233020 V. Description of the Invention (7) = System: Memory Body, 52) Output to the central processing unit f via the first chip 12 to output at the reference frequency of transmission Use one as the switching base: frequency C rate two I: body, double the data transmission rate of the bus, the phase time of the transmission output, the ancient shift output is switched, when each transmission bit is not occupied; internal; effective The data bits are inserted into the previous data bus structure: two: to achieve the purpose of double the current double data transmission rate ... four times the bandwidth memory architecture. Row 103 to access the data. One chip 12 more Use the third system to converge the current Tutus $, Songbu card module 1, 4 of this third system, and # 2 (ACCelerated Graphic Port, two borrowed AGP samples) , 'This graphics acceleration port is the interface to the computer motherboard. It is designed for graphics acceleration port graphics cards. Its function is L crystal. Ίίί The image information between the graphics unit and the graphics card. The busbar 104 is connected to the second chip 16 and the second The daily film 16 connects and controls various peripherals. For example, the peripheral F is set to 17 for keyboards and mice. The disk drive is connected to the hard disk controller and the floppy disk control bank. Daily effect card, network card, etc. Refer to Figure 6 for details. The present invention has a variety of specifications, ^ ^ ^; the second schematic diagram of the system, the central processing unit shown in the figure is connected, the first chip 12 is accessed by the third ^ wood. Beko to the graphics card module 4, the first crystal 104 is connected to the second chip 16, the first door can be connected to the fourth system bus ^ can also be connected to the peripheral component connection interface 15, 1233020 V. Description of the invention (8) f: Controlling peripheral devices 17, disk controller 18, and other devices in connection unit 11 < Ϊ Ϊ 19, etc. The present invention is a central processing unit for a computer system, a body controller, and a central processing unit. 11 With the simultaneous compatibility habit = the bus of the evening transmission channel is like the third type of regulation bus 6 0 1 The 4th trick is to use it ~ α I admit that Yangzhuang Degoutong should urgently continue the first season P / Ritual perseverance transmission channel bus 602 is connected respectively: the body 51 and the second system memory 52, of which < Second of multiple types: i) The bus and multi-bandwidth memory technology. The present invention uses the 4x bandwidth memory technology (0BM) to pay 7G double lean data transmission rate of fi4 to achieve multiplied transmission. The seventh picture is the present invention and the right picture is particularly useful. The third schematic diagram of the system shows the computer-system bus 101 connection of the smart transmission channel. The first, 70 and the first chip 12 are stored in the first. Take the data to the display card module 曰 4, said; ^ three system bus m to 104 to connect to the second chip 16, i-gate-Ding, $ / 12 fine fourth system bus No.-said m-Quila can be connected to the surroundings The component connection interface 15 and the first and second film 16 are connected to control peripheral devices! 7 Connection ": A plurality of types of ports 19 and other devices. The present invention is 18, and the first film with a more compatible grid transmission channel structure 1 2 uses a variety of gauges 53 and a connection control system of a variety of compatible transfer wheels to memorize the control-frame register 31, the same time is reached = stream row 702 even the eighth picture is for the purpose of the present invention. The fourth schematic diagram of the system, in the center of the picture, is the first system bus of the computer, which is connected to the transmission channel of the Megu Valley. The first, the first, the early, the first 11 and the first chip 12 access the data. Go to the graphics card module 14. The third system bus is 103. The daily film 2 is borrowed from the fourth system bus. Ι Ι page 12 1233020 V. Description of the invention (9) 1 0 4 is connected to the second chip 16 during which You can connect peripheral elements # 篦-said Hied pieces connection interface 15, a Japanese film 1 6 connected to control peripherals j 7, a plurality of types of ports η Sheng limbs discouraged ηη is not controlled to 18, more connected grid compatible Sexual transmission, "The central processing unit 11 of the sad month" borrows a variety of rules 53, the first structure; the assembly 801 connection control system memory connection control chart ^ temporary storage ^ frequency, see the C memory body structure The above four busbars 802 are the details of the embodiments of the present invention with various specifications ~, the evaluation details of the computer system of the Qihezhuang Fu transmission channel are detailed in the computer system ... 70 传 Compatibility is passed to the recitation, The tone and "L" row is used for the purpose and effectiveness of several rounds of transmission bandwidth. Substitute to increase the computer system table, the above-mentioned "fully show the brain of the hair channel prostitutes-k You Xi specifications compatible passerial ih ::! For the purpose and efficacy of rich implementation Progressiveness II: Conforms to the invention patent: 丄 i is a new invention that has not been seen in the market before. It completely clarifies the essentials of the patent and applies according to law. King 70 The only thing mentioned above is the private example of the apricots of the present invention, which is 4 *, and it is only a good example. It goes beyond the scope of the present invention. That is to say, everyone who responds to the equal repercussions of the invention according to the present invention shall be still in the patent of the invention, and the modifications should still belong to the invention patent. prayer. (crossbar for yoking horses

1233020 Schematic illustration [Schematic illustration] The first diagram is the first diagram of the internal structure of a conventional technology computer system; the second diagram is the second diagram of the internal structure of a conventional technology computer system; the third diagram is a conventional technology computer system The third diagram of the internal architecture; the fourth diagram is the fourth diagram of the internal architecture of the conventional computer system; the fifth diagram is the first diagram of the computer system with multiple specifications compatible transmission channels of the present invention; the sixth diagram is the present invention Computer system with multiple specifications compatible transmission channels is not intended; the seventh figure is a third schematic diagram of the computer system with multiple specifications compatible transmission channels; the eighth figure is the present invention with multiple specifications compatible transmission channels The fourth schematic diagram of the computer system of the sexual transmission channel. [Symbol description] 11 central processing unit; 1 2 first chip; 1 3 system memory, 1 4 graphics card module; 15 peripheral component connection interface; 16 2 chip, 1 7 peripheral device; 1 8 disk Controller; 19 ports; 101 bus of the first system;

Page 14 1233020 Brief description of the drawings 1 0 2 The second system bus 1 0 3 The third system bus 1 0 4 The fourth system bus 1 0 5 The fifth system bus 1 0 6 The sixth system bus 1 0 7 The seventh system bus 3 1 Picture frame register; 5 0 1 The first multiple specifications compatible transmission channel bus 5 0 2 The second multiple specifications compatible transmission channel bus 5 1 The first system memory 5 2 second system memory; 5 3 conventional system memory, 601 third multi-standard compatible transmission channel bus 6 0 2 fourth multi-standard compatible transmission channel bus 7 0 1 first Bus 7 0 2 Second bus 8 0 1 Third bus 8 0 2 Fourth bus _

Page 15

Claims (1)

1233020 VI. Patent-applicable channel computer system, the computer 1 · a variety of compatible systems with at least: Danbei a central processing unit; a first chip, will be stationed, yuan; you are wrong The system bus connects the central processing unit with a single multi-specification compatible God & 1 1 t memory to the first channel and the bus, so as to connect-the first day of the system, the first chip, the second Peripherals of the Crystal Brain System and multiple ports. The computer system with a variety of specifications and channels described in item 1 of "Li Dian 2 · Li Qian Wei", wherein the first chip is a computer system with a phase y channel, and Λ is / Γ :: capacitive transmission 4. Bridge chip as described in item i of the patent application. Channel computer μ, Λ, Λ / ΛΛ compatibility transfer wheel: compatible with -64 bit double data rate bus: two pieces: 2 memory technology 64 bit double data rate rate queue. "Member = computer system of specification compatibility transmission channel, the computer is a central processing unit; this type of specification compatibility transfer wheel pass-^ n is connected to the central processing single single system memory by m system bus, It is connected to the central processing unit by a first multi-channel bus; 1233020 VI. Patent application scope / first system memory is connected to the first chip by a second multi-channel bus; phase ... The first display card module is connected to the chip via a bus of a graphics acceleration port, and the first chip is connected to the first chip, the second chip is connected to peripheral devices of the computer system and a plurality of 6. The computer system with multiple specifications and compatible channels as described in item 5 of the scope of patent application, wherein the first chip is a Northbridge chip. 7. As described in item 5 of the scope of patent application A computer system with multiple specifications compatible channels, wherein the second chip is a south bridge chip. 刖 8 · A computer system with multiple specifications compatible channels as described in item 5 of the scope of patent application Among them, the first multiple specification-compatible transmission bus has been compatible with a 64-bit double-data-rate-rate bus ^ I. 64-bit double-data-rate memory technology 4 9 · A computer system with 1-channel compatibility with multiple specifications as described in item 5 of the scope of patent application, wherein the second multiple specification-compatible rain and bus are compatible with the 64-bit double data transmission Rate Convergence: = 64-bit bandwidth memory technology, 64-bit double data transmission speed 224 * Computer Li Si with compatible transmission channels of different specifications ^ The brain system includes at least: Edge Power is a central processing unit; a system memory is connected to the central processing unit by a multi-specification compatible transfer bus; and the first chip is connected to the T 3¾ • processing by a front-end system bus. Page 17 1233020 6. Patent application scope unit; a graphics card module connected to the first chip by a bus of a graphics acceleration port; and a first chip connected by a peripheral component connection interface bus (p CI bus) The first chip, the first chip, and the peripheral devices of the computer system are connected to a plurality of ports. 1 1 · A computer system with multiple regulatory compatibility transmission channels as described in item 10 of the scope of patent application, wherein the first chip is a Northbridge chip. 12 · The computer system with a plurality of regulatory compatible transmission channels as described in item 10 of the scope of patent application, wherein the second chip is a south bridge chip. 1 3. The computer system having multiple transmission channels as described in Item 10 of the scope of patent application, wherein the transmission channel bus having multiple specifications compatible transmission bus is compatible with a 64-bit double data transmission Round rate confluence = 64-bit double data transmission with one or four times the bandwidth memory technology -rJ b Λ " 1 4 · A computer computer system with multiple specifications compatible transmission channels includes at least: '' a central A processing unit; a first chip XJTJ early in the morning; is connected to the central processing unit by a front-end system bus, unified memory is connected to the first chip by a bus of a first multi-spec .. lattice structure; Transmission 21: Temporary storage 1 'is connected to the first chip by a bus with a second multi-specification structure; [Transportation Heart 1233020 VI. Patent application scope: a display card module, which is accelerated by a meeting plan The bus of the port is connected to the first chip; and the peripheral component connection interface is connected to the chip and connected to the peripheral device of the computer system. Aa and a second chip are borrowed from the first chip, and the first and the second are connected. Alas. 15 · A computer system with multiple specifications and compatible transmission channels as described in item 14 of the scope of patent application, wherein the first chip is a Northbridge chip. 16. A computer system with multiple specifications and transmission channels as described in item 14 of the scope of patent application, wherein the second chip is a south bridge chip. 17. It has multiple specifications as described in item 14 of the scope of patent application. The computer system of the target value transmission channel, in which the first multiple specifications are compatible. The two buses are compatible with the second multiple specifications. The transmission channel is only doubled in a 64-bit data transmission rate. Confluence 1 18. The 64-bit double data transmission of the Rabbit Memory Technology is a multi-format compatible transmission system. The brain system includes at least: a computer system of the transmission channel, the electrical unit is a central processing unit; a system memory is connected to a first chip of the central processing phase transmission channel via a bus of a first structure, which is borrowed from a The front bar is early, unit; ", the washing bus is connected to the central processing and frame register, which is connected to the first ^ type of compatible transmission wheel channel display card module through the bus of the second night architecture. Group, which is a bus connection for ^ 1 ', theta diagram acceleration port, page 19, 1233020 /, the scope of the patent application of the first chip a second chip, the first chip, and a plurality of connections 19. If applied Computer with patented channel 20. Computer with patented channel 21. Computer channel with patented channel and bus compatible with 64-bit wide memory technology; and a second connection Chun. The 18th system, the 18th system, and the 18th system. The 6-bit peripheral component connection interface bus that is doubled to the second unit is connected to the chip and the peripheral device of the computer system. Wherein the item described in the item, the item described in the item, the data transmission element with multiple specifications is doubled, has one more chip, has two chips, and has multiple compatibility rates. The North specification is a South specification. The phase transmission bus and the rate sink are compatible with the bridge chip. The compatible bridge chip is compatible. The compatible capacitor wheel • The channel bus is a quadruple frequency bus. . Page 20