TWI231974B - Method of manufacturing a trench capacitor - Google Patents

Abstract

A method of manufacturing a trench capacitor is provided. A substrate with a trench is provided. A diffusion region is formed in the substrate around the lower trench. A capacitor dielectric is formed on a surface of the trench, and then a first conductive layer is filled in the lower trench, a spacer is formed on the sidewall of the trench. A portion of the first conductive layer is then removed to form a hollow top surface A thermal oxidation process is performed to oxidize the hollow top surface of the first conductive layer, the exposed capacitor dielectric, and the exposed substrate to become a thermal oxide layer. The spacer and a portion of the thermal oxide layer in the trench are removed to form a buried collar oxide. A second conductive layer is then filled in the trench, and a top of that is higher than a top of the buried collar oxide.

Description

1231974 _Case No. 92120052_Year Month __. V. Description of the Invention (1) The technical field to which the invention belongs The invention relates to a method for manufacturing a capacitor, and in particular to a trench capacitor ) 的 制造 方法 ·. In the prior art, capacitors are an important part of a memory cell to store signals. If the capacitor stores more electric charge, the influence of noise during reading data will be greatly reduced. There are many ways to increase the capacity of a capacitor to store charge, for example, by increasing the area of the capacitor and increasing the total amount of charge stored in the capacitor. In addition, as the degree of accumulation continues to increase, the size of memory cells will continue to shrink. Therefore, a new storage capacitor structure and a manufacturing method thereof are sought, so that the required capacitance value can be maintained while the plane occupied by the storage capacitor is reduced. Currently, a type of capacitor called a "channel capacitor" is gradually being widely used in memory elements. As shown in Figures 1A to 1G, it is a schematic cross-sectional view of the manufacturing process of a trench capacitor. Please refer to FIG. 1A first. A conventional trench capacitor is first provided with a substrate 100 having a trench 110 therein. Moreover, a pad oxide layer 101 and a silicon nitride layer 103 are left on the substrate 100, which serve as a mask when the trench 110 is formed. After that, a diffusion doped region 102 is formed in the substrate 100 around the lower half of the trench 110, and then a surface of the trench 110 is covered with a capacitor dielectric 104, such as a silicon oxide / silicon nitride / silicon oxide stack. Layer (0N0) or silicon nitride / silicon oxide stacked layer (NO).

11490twf1.ptc Page 7 1231974 __MM 92120052_ year, month and year_ 5. Description of the invention (2) Next, please refer to Figure 1 B, fill a trench 1 1 0 with a first polycrystalline silicon layer 106a, and then remove part The first polycrystalline silicon layer 106a is made to exist in the lower half of the trench 110, and the capacitor dielectric layer 104 which is not covered by the first conductive layer 106a is removed. Subsequently, referring to FIG. 1C, an oxide layer 108 is deposited in the trench 110 on the first polycrystalline silicon layer 106a, and then an annealing process is performed to make it dense. Then, referring to FIG. 1D, the oxide layer 108 is etched back to form a collar oxide layer 108a in the capacitor.

After that, please refer to FIG. 1E, fill a second polycrystalline silicon layer 10 6b in the trench 1 10, and then remove a part of the second polycrystalline silicon layer 丨 〇6 b, so that the top surface is lower than The top surface of the substrate 100. Since the second polycrystalline silicon layer 106b at this time is surrounded by the collar oxide layer 108a, the cross-sectional area of the second polycrystalline silicon layer 106b is significantly smaller than that of the first polycrystalline silicon layer 106c. . Subsequently, please refer to FIG. 1F, remove the second polycrystalline silicon layer 10 + 6b / exposed collar oxide layer 108a, and when the diameter of the trench 110 is about 15◦, the collar oxide is formed as an example. The length and thickness of the layer 10a are 800nm and 20nm, respectively. Please refer to FIG. 1G. Fill the trench u with a third polycrystalline A and then remove a portion of the third polycrystalline silicon layer 106c to make it Top surface below

i 8a becomes a surface-embedded and covered in 4 ”and more f Shixi layer 1 _ and collar ^ but p ^ straP (referred to as BS). The distance is also 5 5 2 3 As the trend toward smaller size develops, the distance between components also decreases. Therefore, in terms of trench capacitors,

1231974 _Case No. 92120052_Year_Month__, V. Description of the Invention (3) The width has been continuously reduced, but the thickness and length of the oxide layer 108a, which is used for isolation, cannot be reduced accordingly to prevent vertical parasitic elements (vertica 1 parasitic device). Therefore, the filling step of the second polycrystalline silicon layer (such as FIG. 1E) is difficult to perform, and the problem of increasing the polycrystalline stone gap (s e a m) when the critical dimension (CD) is reduced. In addition, the thickness of the collar oxide layer 10 8 a is constant and the critical dimension of the trench 1 10 is reduced, resulting in a small contact area between the second polycrystalline silicon layer and the third polycrystalline silicon layer of the buried tape (BS). , And increase the contact resistance (Rc_BS) of the buried tape (BS). In addition, the length of the collar oxide layer will cause the effective surface area (effective a r e a) of the capacitor to decrease. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a trench capacitor, which provides a collar oxide layer sufficient to prevent leakage of electricity on a vertical parasitic element after the component is miniaturized. Another object of the present invention is to provide a method for manufacturing a trench capacitor without affecting the filling step of the second conductive layer. Another object of the present invention is to provide a method for manufacturing a trench capacitor, which can avoid the problem of polycrystalline silicon gaps. Another object of the present invention is to provide a method for manufacturing a trench capacitor, which can maintain the contact area between the first conductive layer and the buried tape (BS) and prevent the contact resistance (Rc_BS) of the buried tape (BS). )increase. Another object of the present invention is to provide a method for manufacturing a trench capacitor, which can greatly increase the thickness of the buried collar oxide layer, and can reduce the buried type.

11490twf1.ptc Page 9 1231974 _Case No. 92120052_Year Month__, V. Description of the invention (4) The length of the oxide layer is increased, thereby increasing the effective deep trench height of the capacitor. According to the above and other objectives, the present invention provides a method for manufacturing a trench capacitor, which includes providing a substrate, wherein the substrate has at least one trench, and thereafter, a diffusion-doped region is formed around the substrate in the lower portion of the trench, and then formed on the surface of the trench. A capacitive dielectric layer. Then, a first conductive layer is formed in the trench, wherein the first conductive layer fills the lower half of the trench. Subsequently, a gap wall is formed on the sidewall of the trench on the first conductive layer, and a part of the first conductive layer is removed so that the top surface of the first conductive layer is concave, and then a thermal oxidation process is performed to make The concave first conductive layer is oxidized into a thermal oxide layer by the top dielectric layer, the lateral surface, and the capacitive dielectric layer and the substrate in contact with the lateral surface. Then, a part of the thermal oxide layer in the spacer and the trench is removed to form a buried collar oxide layer, wherein the buried collar oxide layer partially overlaps the diffusion doped region. Thereafter, a second conductive layer is formed in the trench, the top surface of which is higher than the top of the buried collar oxide layer. The invention further provides a method for manufacturing a trench capacitor, which comprises providing a substrate having at least one trench. Then, a diffusion doped region is formed around the substrate below the first depth of the trench, and a capacitive dielectric layer is formed on the surface of the trench. Thereafter, a first conductive layer is formed in the trench to fill the trench below a second depth, where the second depth is shallower than the first depth. Then, a gap wall is formed on the side wall of the trench on the first conductive layer, and then the gap wall is used as a cover, and a part of the first conductive layer is removed so that the top surface thereof is concave. Next, a thermal oxidation process is performed to form a thermal oxidation layer on the capacitor dielectric layer and the substrate in contact with the top surface, the side surface, and the side surface of the first conductive layer. Then, the spacer wall is removed, and then a part of the thermal oxide layer in the trench is removed.

11490twf1.ptc Page 10 1231974 ------- 5. Description of the invention (5) and exposed the structure of the factor of the present invention formed in the trench first, because the vertical parasitic element does not affect the problem of the lightning gap : The cross-sectional area is reduced, and the contact area is increased. In addition, since the addition is connected, the height of the deep trench is two levels. The production efficiency of the present invention is improved to make the present invention easier to understand. The following description is as follows. Schematic diagram of the manufacture of a trench capacitor in a preferred embodiment. Please refer to FIG. 2A, the trench 2110, and since a substrate 200 is provided first, the step of forming an oxide trench on at least one trench is, for example, prior to the substrate 20. 92120052 The first and second conductive layers are those that use the layers on the component, so they can be prevented from being buried in the hair to make them longer. In addition, it only needs to be compared to the two-dimensional omnibus, and it is possible to maintain the first-in-light-type invention with the full leakage of the conductive process parts. The phase layer is modified to form an embedded layer. After the design of the collar is shaped, it does not happen, because of the sudden, so the contact of the buried collar oxygen-conductive layer and the buried tape (BS) of the hair buried collar oxidation is reduced, which is more than the previous case. The trench can be completed and the oxide layer can be reduced. Finally, the oxide layer is made to be buried but can provide enough to prevent the buried collar oxide layer from having polycrystalline stones. The layer will not increase the resistance (Rc_BS) between the trench's penetration band (BS). The thickness of the layer can be greatly increased, and the conductive layer inside the capacitor needs to be reduced in process complexity, so that these and other purposes, features, and advantages can be more clearly implemented. In conjunction with the drawings, a detailed mask is provided. Layer 2 0 3, which is formed on the patterned layer 201-patterned patterned mask layer 2 3 as the mask, in the base m

1231974 No. 92120052 V. Description of the invention (6) Form a ditch 2 ^ 〇. Therefore, a pad oxide layer 201 and a patterned mask layer 203 remain on the substrate 2000. Please continue to refer to FIG. 2A. Then, a diffusion doped region 2 0 2 is formed around the substrate 2 0 with the first depth d 1 of the trench 2, and the step of forming the “2 0 2” region is, for example, first A doping (not shown) is formed on the surface of the trench 210, and the material is, for example, silicon oxide doped with arsenic ions. Subsequently, a photoresist layer (not shown) is formed in 210 to fill the bottom half of the trench 20 a predetermined degree and exposes: a doped f insulating layer. After that, the doped insulating layer not covered by the photoresist layer f is removed to expose a part of the substrate 200 on the sidewall of the trench 210. After the defect, the photoresist layer is removed, and a shielding layer is formed on the structure described above, and then a thermal process is performed to diffuse the dopants in the doped insulating layer into the substrate 200 to form a diffusion doped region. 202. After that, the quasi-doped insulating layer and the shielding layer need to be removed. Next, a surface of the trench 21 is covered with a capacitive dielectric layer 204, wherein the capacitive dielectric layer 204 is, for example, a silicon oxide / silicon oxide stacked layer (NO) or a silicon nitride / silicon oxide stacked layer (n · then Please refer to FIG. 2B, form a layer 206a in the trench 21o, and the first conductive layer 206a fills the trench 21o. The second deep production ... part, and this second depth D2 is more than the first The depth ^ is shallow. The material of the electrical layer 2 6 a is like polycrystalline polysilicon. The aforementioned step of the first conductive layer 206 a is, for example, first forming on the substrate 2000: ^ layer filling Full trench 21〇, and then etch this back-conductive, where the step of: engraving: layer is, for example, dry etching. "Then, remove the capacitor dielectric layer 2 04 'that is not covered by the first 2 0 6a. Subsequent steps remove 0

Case No. 92120052 1231974

V. Description of the invention (7) Then, referring to FIG. 2C, a gap wall 208 is formed on the side wall of the first conductive layer 206 & 2 10, and then the gap wall 208 and the pattern are formed. The mask layer 203 is used as a mask, and a part of the first conductive layer 206a is removed, so that the top surface of the first conductive layer 206a is concave, and its depth is about the same as the first depth ^. The first conductive layer 206a is partially removed, for example, in a dry-engraved manner. The step of forming the spacer 208 may include forming a silicon oxide layer 209a and a silicon nitride layer 209b. The silicon nitride layer 209b and the silicon oxide layer 20 may be formed. 9 a until the _ ° \ top surface is exposed 2 0 6 a. In addition, by controlling the degree of depression of the first conductive layer 206 & shown in the figure, the length of the buried collar oxide ^ a (buried collar oxide) formed later can be controlled. In the aforementioned 2B figure, the capacitor dielectric layer 204 covered by the conductive layer 206a has not been removed, and the cushion layer of argon layer 2 0 9b can be used. The layer 2 09a, the gap ", and the volume 208 are composed of a capacitor dielectric layer 204 and a silicon nitride layer 209b. "" Then, referring to Figure 2D, a thermal oxidation process is performed to oxidize the top surface, side surfaces, and side surfaces of the concave first conductive layer 206a = the dielectric layer 2 0 4 and the substrate 2 0 0. It is a thermal oxidation layer 212, and its parameters of the electro-thermal oxidation process are to obtain the following embedded type 2: predetermined thickness. In other words, if the capacitor dielectric layer m is an oxide layer, such as oxidized stone / nitride The oxygen / oxygen layer 204 includes silicon nitride stacked layers (i.e.,), and can be used in ;;: stacking (ii) or nitridation / oxidation and oxidation processes. The silicon nitride wafer is removed, After applying the thermal conductive layer 20a (as shown in FIG. 2C), the initial method is, for example, to remove a part of the first layer by applying a wet etching process to make the first conductive layer

1231974 __ + case number 92120 of 9_year f. 5. Description of the invention (8) ί Π: 移除: remove the valley using a wet coin engraving method; 丨 the silicon nitride layer in the electric layer 2 04 For example, if a phosphoric acid substrate 200 is used to reserve a part of the partition wall 2 0 8 in the subsequent thermal oxidation process "& the next two, please refer to Figure 2E, go to the figure), in which the step of removing the partition wall 2 08 The silicon layer 2 0 9 b is removed by wet etching to remove the dielectric layer 2 0 4. Remove the spacer 2 0 8 (See step 2D. For example, first remove the remaining nitride to remove the remaining silicon oxide layer 2 09a or electricity. Then, refer to Figure 2F to remove the layer of the trench 210 order. " The first conductive layer 206a is exposed to form one ::, oxide layer 2 1 2a, and the buried collar oxide layer 2 1 2 a partially overlaps with the diffusion doped region 202. The method for removing a part of the thermal oxide layer 2 in the trench 2 10 is, for example, dry etching. And, for example, when the diameter of the trench 2 is about 150 nm, for example, the final embedded The length and thickness of the collar oxide layer 2 丨 2a are, for example, 600nm and 30ηπ, respectively. Next, referring to FIG. 2G, the top surface of the first conductive layer 206a and the trench 2 can be selectively selected. A thin nitrided stone layer (not shown) is formed on the 10 side wall as a buried tape (BS) lining layer. Then, a second conductive layer 206b is formed in the trench 210, and its top surface is higher than the buried type. On the top of the collar oxide layer 212a, the material of the second conductive layer 206b is, for example, doped polycrystalline silicon. In addition, the step of forming the second conductive layer 206b is, for example, first A conductive layer is formed on the substrate 200 to fill the trench 210, and then this conductive layer is etched back to form a second conductive layer 206b. In summary, the present invention is characterized by the use of a process design leader

11490twf1.ptc Page 14 1231974 V. Description of the invention (9) The oxide layer is made into a buried type but can provide enough to prevent leakage on the device (the Le layer will not affect the seam of the conductive layer) The contact resistance of the contact surface (BS) between the cross-sectional area band (BS) of the trench (the thickness of the Rc_-type collar oxide layer can be reduced, which can increase the capacitance. In addition, compared with the previous case, it can be completed with two layers. It can be high. Although the present invention has been limited to the present invention, within any scope and scope, it can be regarded as the modified structure of the attached application. Therefore, after the component is miniaturized, the vertical parasitic akage is not vertical. The occurrence of the oxide is also due to the buried collar oxide filling step, so the present invention does not have polycrystalline stones. Furthermore, the buried collar oxide layer of the present invention is reduced, so that the first conductive layer and the buried layer can be maintained. The contact area is increased, and the embedded belt BS is prevented from increasing. In addition, since the embedding of the present invention is greatly increased, the length thereof can be reduced by the effective area of the retractor. The conductivity in the trench The layer requires three layers. The present invention only reduces the complexity of the process, so that the production efficiency is improved. The preferred embodiment is disclosed above, but it is not used! This artist does not depart from the spirit of the present invention. The patent protection of the invention shall prevail.

1231974 _Case No. 92120052_Year Month Day Amendment __ Drawings Brief Description Figures 1A to 1G are schematic cross-sectional schematic diagrams of the manufacturing process of a trench capacitor; and Figures 2A to 2G are based on A schematic sectional view of a manufacturing process of a trench capacitor according to a preferred embodiment of the present invention. Description of the drawings: 1 00, 2 0 0: substrate 101, 201: pad oxide layer 102, 202: diffusion doped region 103, 209b: silicon nitride layer 1 04 • oxidation / nitride layer 1 0 6 a, 1 0 6 b, 1 0 6 c: polycrystalline silicon layer 1 0 8: oxide layer 1 0 8 a: collar oxide layer 1 1 0, 2 1 0: trench 2 0 3 ·· patterned mask layer 204: capacitor dielectric layer 206a, 206b: conductive layer 208: partition wall 209a: silicon oxide layer 2 1 2: thermal oxide layer 2 1 2a: buried collar oxide layer

11490twf1.ptc Page 16

Claims (1)

1231974 Case No. 92120052 Amendment VI. Patent Application Scope 1. A trench-type electrical supply provides a substrate 'the lower part of the trench is formed on the surface of the trench in the trench formed in the first conductive layer removal part the first implementation A thermally oxidized surface, and the layer in contact with the sides; removing the spacer; removing the electrical layer in the trench to form an embedded and diffused doped region in the trench 2. Such as a patent application A method comprising providing the patterned mask based on the substrate formed on the pad oxide layer. If the method is a patent application, the steps in the trench area include: a method of manufacturing a container on the surface of the trench, The substrate comprises at least one trench; a diffusion doped region is formed in the periphery of the substrate; a capacitive dielectric layer is formed; a first conductive layer fills the lower half of the trench; a gap is formed on the sidewall of the trench; Layer so that its top surface is concave; forming a thermally oxidized portion of the thermally oxidized layer on the top surface of the first conductive layer, the lateral capacitive dielectric layer, and the substrate; and The first conductive collar oxide layer is exposed, wherein the buried collar oxide layers overlap; and a second conductive layer. The steps surrounding the manufacturing of the trench capacitor described in item 1 include: an oxide layer; forming a patterned mask layer; and the layer is a mask to form the trench in the substrate. The diffusion doping is formed in the periphery of the base of the trench capacitor described in item 1 to form a doped insulating layer; 11490twf1.ptc Page 17 1231974 _Case No. 92120052_Year Month Amendment _: _ Sixth, the scope of the patent application forms a photoresist layer in the trench to fill the lower half of the trench and expose a part of the doped insulating layer; Removing the doped insulating layer not covered by the photoresist layer to expose part of the substrate on the side wall of the trench; removing the photoresist layer; forming a shielding layer on the structure: performing a thermal process to make The dopant in the doped insulating layer diffuses into the substrate to form the diffused doped region; and the doped insulating layer and the shielding layer remaining in the trench are removed. 4. The method for manufacturing a trench capacitor according to item 1 of the scope of the patent application, wherein the material of the doped insulating layer includes oxidized stone doped with arsenic ions. 5. The method for manufacturing a trench capacitor according to item 1 of the scope of the patent application, wherein the capacitor dielectric layer is selected from the group consisting of silicon oxide / silicon nitride / silicon oxide stacked layer (NO) and silicon nitride / silicon oxide stacked Layer (NO). 6. The method for manufacturing a trench capacitor according to item 5 of the scope of patent application, wherein before performing the thermal oxidation process and after removing a portion of the first conductive layer to make the top surface concave, the method further includes removing the capacitor. A silicon nitride layer in a dielectric layer. 7. The method for manufacturing a trench capacitor as described in item 6 of the scope of patent application, wherein the method of removing the nitride layer includes: removing the concave sides of the first conductive layer; and removing by a wet etching method A silicon nitride layer in the capacitor dielectric layer, and a part of the spacer is reserved. 11490twf1.ptc page 18 1231974 _ case number 92120052 _ month and month ___ 6. patent application scope 8. The method for manufacturing a trench capacitor as described in item 1 of the patent scope, wherein the first conductive layer is The step of forming the gap wall on the side wall of the trench includes: removing the capacitive dielectric layer not covered by the first conductive layer; forming a silicon oxide layer on the top surface of the first conductive layer and on the side wall of the trench; Forming a silicon nitride layer on the silicon oxide layer; and etching back the silicon nitride layer and the silicon oxide layer until the top surface of the first conductive layer is exposed. 9. The method for manufacturing a trench capacitor according to item 1 of the scope of patent application, wherein the step of forming the spacer on the trench side wall on the first conductive layer includes: forming a top surface of the first conductive layer and A silicon nitride layer is formed on a side wall of the trench; and the silicon nitride layer and the capacitor dielectric layer are etched back until the top surface of the first conductive layer is exposed. 10. The method for manufacturing a trench capacitor as described in item 2 of the scope of the patent application, wherein the step of removing part of the first conductive layer to make its top surface concave is using the gap wall and the patterned mask The layer is used as a mask, and a portion of the first conductive layer is removed by dry etch-back. 1 1. The method for manufacturing a trench capacitor as described in item 1 of the scope of patent application, wherein before forming the second conductive layer in the trench, it further comprises forming a nitrogen on the top surface of the first conductive layer and the sidewall of the trench. Silicone liner. 12. Manufacturing of trench capacitors as described in item 1 of the scope of patent application 11490twf1.ptc Page 19 1231974 _ Case No. 92120052_Year____ Sixth, the scope of patent application method, wherein the material of the first conductive layer and the second conductive layer includes doped polycrystalline silicon. 13. A method for manufacturing a trench capacitor, comprising: providing a substrate having at least one trench; forming a diffusion doped region around the substrate below a first depth of the trench; forming a capacitor on the surface of the trench A dielectric layer; forming a first conductive layer in the trench to fill the trench below a second depth, where the second depth is shallower than the first depth; forming a gap wall on the sidewall of the trench on the first conductive layer ; Removing part of the first conductive layer so that its top surface is concave; performing a thermal oxidation process to form the capacitor dielectric layer and the substrate in contact with the top surface, the side surface, and the side surface of the first conductive layer; A thermal oxide layer; removing the spacer; removing a portion of the thermal oxide layer in the trench and exposing the first conductive layer to form a buried collar oxide layer; and forming a second conductive layer in the trench Floor. 14. The method for manufacturing a trench capacitor as described in item 13 of the scope of the patent application, wherein the step of providing the substrate includes: forming a pad oxide layer on the substrate; forming a pattern on the pad oxide layer. A mask layer; and using the patterned mask layer as a mask, the trench is formed in the substrate. 1 5. The system of trench capacitors as described in item 13 of the scope of patent application 11490twf1.ptc Page 20 1231974 _Case No. 92120052_Year_Month____ VI. Patent application method, wherein the step of forming the diffusion-doped region around the substrate below the trench includes the steps of: Forming a doped insulating layer; forming a photoresist layer in the trench to fill the lower half of the trench and exposing a part of the doped insulating layer, removing the doped insulating layer not covered by the photoresist layer, so as to A part of the substrate on the side wall of the trench is exposed; the photoresist layer is removed; a shielding layer is formed on the above structure: a thermal process is performed to diffuse the dopants in the doped insulating layer into the substrate to form the diffusion A doped region; and removing the doped insulating layer and the shielding layer remaining in the trench. 1 6. The method for manufacturing a trench capacitor as described in item 13 of the scope of patent application, wherein the material of the doped insulating layer includes arsenic ion-doped oxide stone. 7. As item 13 of the scope of patent application In the method for manufacturing a trench capacitor, the capacitor dielectric layer is selected from a silicon oxide / silicon nitride / silicon oxide stacked layer (NO) or a silicon nitride / silicon oxide stacked layer (NO). 1 8. The method for manufacturing a trench capacitor as described in item 17 of the scope of patent application, wherein before performing the thermal oxidation process and after removing a portion of the first conductive layer to make its top surface concave, it further includes removing A silicon nitride layer in the capacitor dielectric layer. 19. The method for manufacturing a trench capacitor as described in item 18 of the scope of patent application, wherein the method for removing the nitride layer includes: 11490twfl.ptc Page 21 1231974 _Case No. 92120052_Year Month __ · _ 6. Apply for a patent to remove the concave sides of the first conductive layer; and use a wet etching method to remove the capacitor dielectric The silicon nitride layer in the layer, and a part of the spacer is retained. 2 0. The method for manufacturing a trench capacitor according to item 13 of the patent application, wherein the step of forming the spacer on the sidewall of the trench on the first conductive layer includes: removing A capacitive dielectric layer covered by a conductive layer; forming a silicon oxide layer on a top surface of the first conductive layer and a side wall of the trench; forming a silicon nitride layer on the silicon oxide layer; and etching back the silicon nitride layer And the silicon oxide layer until the top surface of the first conductive layer is exposed. 2 1. The method for manufacturing a trench capacitor as described in item 13 of the scope of patent application, wherein the step of forming the gap wall on the trench side wall on the first conductive layer includes: on top of the first conductive layer A silicon nitride layer is formed on the surface and the side wall of the trench; and the silicon nitride layer and the capacitor dielectric layer are etched back until the top surface of the first conductive layer is exposed. 2 2. The method for manufacturing a trench capacitor according to item 14 of the scope of the patent application, wherein the step of removing part of the first conductive layer to make the top surface concave is using the gap wall and the patterned cover The curtain layer is used as a mask, and a part of the first conductive layer is removed by dry etch-back. 2 3.The system of trench capacitors as described in item 13 of the scope of patent application 11490twf1.ptc Page 22 1231974 _Case No. 92120052_Year Month _ Amendment ___ 6. Method for applying for a patent application, in which a part of the first conductive layer is removed to make its top surface concave. The steps are as follows: The concave depth of the top surface of a conductive layer is about the same as the first depth. 2 4 · The method for manufacturing a trench capacitor according to item 13 of the patent application, wherein before forming the second conductive layer in the trench, the method further includes forming on the top surface of the first conductive layer and the sidewall of the trench. A silicon nitride liner. 25. The method for manufacturing a trench capacitor according to item 13 of the scope of the patent application, wherein the material of the first conductive layer and the second conductive layer includes doped polycrystalline silicon. 11490twf1.ptc Page 23