TWI231974B - Method of manufacturing a trench capacitor - Google Patents
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- TWI231974B TWI231974B TW092120052A TW92120052A TWI231974B TW I231974 B TWI231974 B TW I231974B TW 092120052 A TW092120052 A TW 092120052A TW 92120052 A TW92120052 A TW 92120052A TW I231974 B TWI231974 B TW I231974B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 239000004575 stone Substances 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- -1 arsenic ions Chemical class 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 229920001296 polysiloxane Polymers 0.000 claims 1
- 230000000717 retained effect Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000005192 partition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241001080526 Vertica Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
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Abstract
Description
1231974 _案號 92120052_年月日__. 五、發明說明(1) 發明所屬之技術領域 本發明是有關於一種電容器(capacitor)之製造方 法,且特別是有關於一種溝渠式電容器(t r e n c h capacitor)之製造方法·。 先前技術 電容器是記憶胞藉以儲存訊號的重要部位,如果電容 器所儲存的電荷愈多,則在讀取資料時受雜訊的影響將大 大的降低。要增加電容器儲存電荷能力的方法有很多種, 例如是以增加電容器的面積,使整個儲存於電容器内的電 荷數量增加之方式。另外,隨著積集度不斷的增加,記憶 胞的尺寸仍會繼續縮小。因此,找尋新的儲存電容器結構 及其製造方法,藉以使得在儲存電容器所佔的平面縮小的 情況下,仍能維持所需的電容值。 目前有一種稱為「溝渠式電容器」的電容器正逐漸廣 泛應用於記憶元件中,如第1 Α圖至第1 G圖所示,其係習知 一種溝渠式電容器的製造流程剖面示意圖。 請先參照第1 A圖,習知的溝渠式電容器的製作是先提 供一基底100,其中具有一溝渠110。而且,在基底100上 殘留有一墊氧化層1 0 1以及一氮化矽層1 0 3,其係作為形成 溝渠110時的罩幕(mask)。之後,於溝渠110下半部周圍的 基底100中形成一擴散摻雜區102,再於溝渠110表面覆蓋 一電容介電層(capacitor dielectric)104,例如是氧化 矽/氮化矽/氧化矽堆疊層(0N0)或氮化矽/氧化矽堆疊層 (NO) 〇1231974 _Case No. 92120052_Year Month __. V. Description of the Invention (1) The technical field to which the invention belongs The invention relates to a method for manufacturing a capacitor, and in particular to a trench capacitor ) 的 制造 方法 ·. In the prior art, capacitors are an important part of a memory cell to store signals. If the capacitor stores more electric charge, the influence of noise during reading data will be greatly reduced. There are many ways to increase the capacity of a capacitor to store charge, for example, by increasing the area of the capacitor and increasing the total amount of charge stored in the capacitor. In addition, as the degree of accumulation continues to increase, the size of memory cells will continue to shrink. Therefore, a new storage capacitor structure and a manufacturing method thereof are sought, so that the required capacitance value can be maintained while the plane occupied by the storage capacitor is reduced. Currently, a type of capacitor called a "channel capacitor" is gradually being widely used in memory elements. As shown in Figures 1A to 1G, it is a schematic cross-sectional view of the manufacturing process of a trench capacitor. Please refer to FIG. 1A first. A conventional trench capacitor is first provided with a substrate 100 having a trench 110 therein. Moreover, a pad oxide layer 101 and a silicon nitride layer 103 are left on the substrate 100, which serve as a mask when the trench 110 is formed. After that, a diffusion doped region 102 is formed in the substrate 100 around the lower half of the trench 110, and then a surface of the trench 110 is covered with a capacitor dielectric 104, such as a silicon oxide / silicon nitride / silicon oxide stack. Layer (0N0) or silicon nitride / silicon oxide stacked layer (NO).
11490twf1.ptc 第7頁 1231974 __MM 92120052_年月日_ 五、發明說明(2) 接著,請參照第1 B圖,於溝渠1 1 0中填滿一第一多晶 矽層106a,再去除部分第一多晶矽層l〇6a,使其存在於溝 渠110下半部,並去除未被第一導電層106a覆蓋之電容介 電層1 04。 隨後,請參照第1 C圖,於第一多晶矽層1 0 6 a上之溝渠 110中沈積一層氧化層108,再進行一回火製程(anneal process),使其緻密化。 然後’請參照第1 D圖,回蝕刻氧化層1 0 8,以形成電 容器中的領氧化層(collar 〇xide)108a。11490twf1.ptc Page 7 1231974 __MM 92120052_ year, month and year_ 5. Description of the invention (2) Next, please refer to Figure 1 B, fill a trench 1 1 0 with a first polycrystalline silicon layer 106a, and then remove part The first polycrystalline silicon layer 106a is made to exist in the lower half of the trench 110, and the capacitor dielectric layer 104 which is not covered by the first conductive layer 106a is removed. Subsequently, referring to FIG. 1C, an oxide layer 108 is deposited in the trench 110 on the first polycrystalline silicon layer 106a, and then an annealing process is performed to make it dense. Then, referring to FIG. 1D, the oxide layer 108 is etched back to form a collar oxide layer 108a in the capacitor.
之後,請參照第1 E圖,於溝渠1 1 0中填滿一第二多晶 石夕層1 0 6 b,再去除部分第二多晶矽層丨〇 6 b,使其頂面低於 基底100頂面。由於此時的第二多晶矽層106b被領氧化層 1 0 8 a所包圍,所以第二多晶矽層丨〇 6 b的截面積明顯小於第 一多晶矽層l〇6c的截面積。 隨後’請參照第1 F圖,去除第二多晶矽層1 〇 6 b以上戶/ 裸露出的領氧化層108a,其中當溝渠11〇之直徑約為15〇⑴ 為例終形成的領氧化層1 〇8a之長度與厚度分別為 8 0 0nm 與20nm 〇 放,請參照第1G圖,於溝渠u〇中填滿一第三多晶 A 再去除部分第三多晶矽層106c,使其頂面低於After that, please refer to FIG. 1E, fill a second polycrystalline silicon layer 10 6b in the trench 1 10, and then remove a part of the second polycrystalline silicon layer 丨 〇6 b, so that the top surface is lower than The top surface of the substrate 100. Since the second polycrystalline silicon layer 106b at this time is surrounded by the collar oxide layer 108a, the cross-sectional area of the second polycrystalline silicon layer 106b is significantly smaller than that of the first polycrystalline silicon layer 106c. . Subsequently, please refer to FIG. 1F, remove the second polycrystalline silicon layer 10 + 6b / exposed collar oxide layer 108a, and when the diameter of the trench 110 is about 15◦, the collar oxide is formed as an example. The length and thickness of the layer 10a are 800nm and 20nm, respectively. Please refer to FIG. 1G. Fill the trench u with a third polycrystalline A and then remove a portion of the third polycrystalline silicon layer 106c to make it Top surface below
i 8a而成為面埋入且式覆4於』二多f石夕層1 _與領^ 不過p ^式帶(b ed straP,簡稱BS)。 距離也合5 5 2 3往更小型化的趨勢發展後,各元件間之 距離也"斷縮減。因此,以溝渠式電容器而言,溝渠的i 8a becomes a surface-embedded and covered in 4 ”and more f Shixi layer 1 _ and collar ^ but p ^ straP (referred to as BS). The distance is also 5 5 2 3 As the trend toward smaller size develops, the distance between components also decreases. Therefore, in terms of trench capacitors,
1231974 _案號 92120052_年月日__ , 五、發明說明(3) 寬度不斷縮小,但作為隔離用之領氧化層108a的厚度及長 度無法隨之縮小,以防止在垂直寄生元件(v e r t i c a 1 parasitic device)上之漏電。 因此會導致第二多晶矽層之填滿步驟(如第1 E圖)難以 施行,而於關鍵尺寸(critical dimension,簡稱CD)縮減 下增加多晶石夕產生縫隙(s e a m )的問題。此外,領氧化層 1 0 8 a厚度不變而溝渠1 1 0的關鍵尺寸縮小,造成第二多晶 矽層與埋入式帶(BS)之第三多晶矽層之間的接觸面積過 小,而增加埋入式帶(BS)之接觸電阻(Rc_BS)。另外,領 氧化層的長度還會造成電容器之有效表面積(effective a r e a )減少。 發明内容 因此,本發明之目的是提供一種溝渠式電容器之製造 方法,以於元件小型化之後,提供足以防止在垂直寄生元 件上之漏電的領氧化層。 本發明之再一目的是提供一種溝渠式電容器之製造方 法,不會影響第二導電層之填滿步驟。 本發明之另一目的是提供一種溝渠式電容器之製造方 法,可避免發生多晶矽縫隙的問題。 本發明之又一目的是提供一種溝渠式電容器之製造方 法,可保持第一導電層與埋入式帶(BS )之間的接觸面積, 而防止埋入式帶(BS)之接觸電阻(Rc_BS)增加。 本發明之又一目的是提供一種溝渠式電容器之製造方 法,可大幅增加埋入式領氧化層之厚度,而能減少埋入式1231974 _Case No. 92120052_Year_Month__, V. Description of the Invention (3) The width has been continuously reduced, but the thickness and length of the oxide layer 108a, which is used for isolation, cannot be reduced accordingly to prevent vertical parasitic elements (vertica 1 parasitic device). Therefore, the filling step of the second polycrystalline silicon layer (such as FIG. 1E) is difficult to perform, and the problem of increasing the polycrystalline stone gap (s e a m) when the critical dimension (CD) is reduced. In addition, the thickness of the collar oxide layer 10 8 a is constant and the critical dimension of the trench 1 10 is reduced, resulting in a small contact area between the second polycrystalline silicon layer and the third polycrystalline silicon layer of the buried tape (BS). , And increase the contact resistance (Rc_BS) of the buried tape (BS). In addition, the length of the collar oxide layer will cause the effective surface area (effective a r e a) of the capacitor to decrease. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a trench capacitor, which provides a collar oxide layer sufficient to prevent leakage of electricity on a vertical parasitic element after the component is miniaturized. Another object of the present invention is to provide a method for manufacturing a trench capacitor without affecting the filling step of the second conductive layer. Another object of the present invention is to provide a method for manufacturing a trench capacitor, which can avoid the problem of polycrystalline silicon gaps. Another object of the present invention is to provide a method for manufacturing a trench capacitor, which can maintain the contact area between the first conductive layer and the buried tape (BS) and prevent the contact resistance (Rc_BS) of the buried tape (BS). )increase. Another object of the present invention is to provide a method for manufacturing a trench capacitor, which can greatly increase the thickness of the buried collar oxide layer, and can reduce the buried type.
11490twf1.ptc 第9頁 1231974 _案號 92120052_年月日__ , 五、發明說明(4) 領氧化層之長度,進而增加電容器之有效深溝渠高度。 根據上述與其它目的,本發明提出一種溝渠式電容器 之製造方法,包括提供一基底,其中基底具有至少一溝 渠,之後,於溝渠下部的基底周圍中形成一擴散摻雜區, 再於溝渠表面形成一電容介電層。接著,於溝渠中形成一 第一導電層,其中第一導電層填滿溝渠下半部。隨後,於 第一導電層上之溝渠側壁上形成一間隙壁,及移除部分第 一導電層,使第一導電層之頂面呈下凹狀,再施行一熱氧 化製程,以使呈下凹狀的第一導電層頂面、側面、及側面 接觸之電容介電層及基底氧化為一熱氧化層。接著,去除 間隙壁及溝渠中之部分熱氧化層,以形成一埋入式領氧化 層,其中埋入式領氧化層與擴散摻雜區係部份重疊。之 後,於溝渠中形成一第二導電層,其頂面高於埋入式領氧 化層頂端。 本發明另外提出一種溝渠式電容器之製造方法,包括 提供一基底,其中具有至少一溝渠。然後,於溝渠第一深 度以下的基底周圍中形成一擴散摻雜區,再於溝渠表面形 成一電容介電層。之後,於溝渠中形成一第一導電層填滿 該溝渠第二深度以下,其中第二深度較第一深度為淺。隨 後,於第一導電層上之溝渠側壁上形成一間隙壁,再以間 隙壁作為罩幕,移除部分第一導電層使其頂面呈下凹狀。 接著,施行一熱氧化製程,以於第一導電層之頂面、側 面、及側面接觸之該電容介電層及該基底形成一熱氧化 層。然後,去除間隙壁,再去除溝渠中之部分熱氧化層,11490twf1.ptc Page 9 1231974 _Case No. 92120052_Year Month__, V. Description of the invention (4) The length of the oxide layer is increased, thereby increasing the effective deep trench height of the capacitor. According to the above and other objectives, the present invention provides a method for manufacturing a trench capacitor, which includes providing a substrate, wherein the substrate has at least one trench, and thereafter, a diffusion-doped region is formed around the substrate in the lower portion of the trench, and then formed on the surface of the trench. A capacitive dielectric layer. Then, a first conductive layer is formed in the trench, wherein the first conductive layer fills the lower half of the trench. Subsequently, a gap wall is formed on the sidewall of the trench on the first conductive layer, and a part of the first conductive layer is removed so that the top surface of the first conductive layer is concave, and then a thermal oxidation process is performed to make The concave first conductive layer is oxidized into a thermal oxide layer by the top dielectric layer, the lateral surface, and the capacitive dielectric layer and the substrate in contact with the lateral surface. Then, a part of the thermal oxide layer in the spacer and the trench is removed to form a buried collar oxide layer, wherein the buried collar oxide layer partially overlaps the diffusion doped region. Thereafter, a second conductive layer is formed in the trench, the top surface of which is higher than the top of the buried collar oxide layer. The invention further provides a method for manufacturing a trench capacitor, which comprises providing a substrate having at least one trench. Then, a diffusion doped region is formed around the substrate below the first depth of the trench, and a capacitive dielectric layer is formed on the surface of the trench. Thereafter, a first conductive layer is formed in the trench to fill the trench below a second depth, where the second depth is shallower than the first depth. Then, a gap wall is formed on the side wall of the trench on the first conductive layer, and then the gap wall is used as a cover, and a part of the first conductive layer is removed so that the top surface thereof is concave. Next, a thermal oxidation process is performed to form a thermal oxidation layer on the capacitor dielectric layer and the substrate in contact with the top surface, the side surface, and the side surface of the first conductive layer. Then, the spacer wall is removed, and then a part of the thermal oxide layer in the trench is removed.
11490twf1.ptc 第10頁 1231974 ------- 五、發明說明(5) 並暴露出第一 於溝渠中形成 本發明因 式的結構,因 在垂直寄生元 不會影響導雷 隙的問題: 截面積縮減, 接觸面積,而 加。另外,由 加,所以連帶 =深溝渠高度 二層,本發明 生產的效率提 為讓本發 顯易懂,下文 說明如下: 第2A圖至笛9 式電容器的製ί ^ G圖係依照本發明之一較佳實施例之溝渠 式電容器的製造,程剖面示意圖。請先參照第2 Α圖,溝渠 渠2 1〇 ,而且因\是先提供一基底2 00,其中具有至少一溝 上形成一塾氧化溝的步驟例如是先於基底20。 92120052 導電層 一第二 為利用 此於元 件上之 層之填 者,本 故可保 防止埋 於本發 使其長 。此外 僅需二 向 〇 明之上 特舉較 ,以 導電 製程 件小 漏電 滿步 發明 持第 入式 明之 度可 ,相 層即 曰 修正 形成一埋入式 層。 上的設計將領 型化之後,不 的發生,還因 驟,所以本發 之埋入式領氧 一導電層與埋 帶(BS)之接觸 埋入式領氧化 被縮減,進而 較於前案在溝 可完成,可減 領氧化層。最後, 氧化層製作成埋入 但能提供足以防止 為埋入式領氧化層 明不會有多晶石夕縫 化層不會使溝渠之 入式帶(BS)之間的 電阻(Rc_BS)增 層的厚度可大幅增 能增加電容器之有 渠内的導電層需要 少製程複雜度,使 述和其他目的、特徵、和優點能更明 佳實施例,並配合所附圖式,作詳細 罩幕層2 0 3,,以=化Π 2化層201上形成-圖案化 圖案化罩幕層2 0 3為罩幕,於基底m中11490twf1.ptc Page 10 1231974 ------- 5. Description of the invention (5) and exposed the structure of the factor of the present invention formed in the trench first, because the vertical parasitic element does not affect the problem of the lightning gap : The cross-sectional area is reduced, and the contact area is increased. In addition, since the addition is connected, the height of the deep trench is two levels. The production efficiency of the present invention is improved to make the present invention easier to understand. The following description is as follows. Schematic diagram of the manufacture of a trench capacitor in a preferred embodiment. Please refer to FIG. 2A, the trench 2110, and since a substrate 200 is provided first, the step of forming an oxide trench on at least one trench is, for example, prior to the substrate 20. 92120052 The first and second conductive layers are those that use the layers on the component, so they can be prevented from being buried in the hair to make them longer. In addition, it only needs to be compared to the two-dimensional omnibus, and it is possible to maintain the first-in-light-type invention with the full leakage of the conductive process parts. The phase layer is modified to form an embedded layer. After the design of the collar is shaped, it does not happen, because of the sudden, so the contact of the buried collar oxygen-conductive layer and the buried tape (BS) of the hair buried collar oxidation is reduced, which is more than the previous case. The trench can be completed and the oxide layer can be reduced. Finally, the oxide layer is made to be buried but can provide enough to prevent the buried collar oxide layer from having polycrystalline stones. The layer will not increase the resistance (Rc_BS) between the trench's penetration band (BS). The thickness of the layer can be greatly increased, and the conductive layer inside the capacitor needs to be reduced in process complexity, so that these and other purposes, features, and advantages can be more clearly implemented. In conjunction with the drawings, a detailed mask is provided. Layer 2 0 3, which is formed on the patterned layer 201-patterned patterned mask layer 2 3 as the mask, in the base m
1231974 銮號 92120052 五、發明說明(6) 形成溝渠2^〇。所以’在基底2 0 0上殘留有一墊氧化層2〇1 以及一圖案化罩幕層203。 請繼續參照第2 A圖,之後於溝渠2丨〇第一深度d 1以 的基底2 0 0周圍中形成一擴散摻雜區2 0 2,且成" 區2 0 2之步驟譬如是先於溝渠210表面形成一摻雜 (未繪示),其材質如摻雜砷離子之氧化矽。隨後,於 2 1 0内形成一光阻層(未繪示)填滿溝渠2丨〇下半部一預定^ 度且暴露出:分摻f絕緣層。之後,移除未被光阻層覆f 之摻雜絕緣層,以暴露出部分溝渠210側壁之基底200。缺 後,移除光阻層,並於上述結構上形成—遮蔽層…、 示),再進行一熱製程,使摻雜絕緣層中的摻質擴散進入 基底2 00中而形成擴散摻雜區202,之後需移除準 的摻雜絕緣層與遮蔽層。接著,於溝渠21〇表面覆蓋一 容介電層2 0 4,其中電容介電層2〇4譬如是氧化矽/ 氧化矽堆疊層(ΟΝΟ)或氮化矽/氧化矽堆疊層(n · 接著,請參照第2B圖,於溝渠21〇中形θ成一 層2〇6a,且第一導電層2〇6a填滿溝渠21〇第二深产… 部,且此第二深度D2較前述第一深度^為淺。其夂中 電層2 0 6 a之材質如換雜多晶石夕。而前述於 |第 第一導電層206a之步驟例如是先在基底2〇〇上形:^ 層填滿溝渠21〇,再回蚀刻此—導電,,其中回:刻:: 層之步驟例如是乾式蝕刻《隨後,去除未被第一 2 0 6a覆蓋之電容介電層2 04 ’亦可選擇於後續步驟再去 除01231974 No. 92120052 V. Description of the invention (6) Form a ditch 2 ^ 〇. Therefore, a pad oxide layer 201 and a patterned mask layer 203 remain on the substrate 2000. Please continue to refer to FIG. 2A. Then, a diffusion doped region 2 0 2 is formed around the substrate 2 0 with the first depth d 1 of the trench 2, and the step of forming the “2 0 2” region is, for example, first A doping (not shown) is formed on the surface of the trench 210, and the material is, for example, silicon oxide doped with arsenic ions. Subsequently, a photoresist layer (not shown) is formed in 210 to fill the bottom half of the trench 20 a predetermined degree and exposes: a doped f insulating layer. After that, the doped insulating layer not covered by the photoresist layer f is removed to expose a part of the substrate 200 on the sidewall of the trench 210. After the defect, the photoresist layer is removed, and a shielding layer is formed on the structure described above, and then a thermal process is performed to diffuse the dopants in the doped insulating layer into the substrate 200 to form a diffusion doped region. 202. After that, the quasi-doped insulating layer and the shielding layer need to be removed. Next, a surface of the trench 21 is covered with a capacitive dielectric layer 204, wherein the capacitive dielectric layer 204 is, for example, a silicon oxide / silicon oxide stacked layer (NO) or a silicon nitride / silicon oxide stacked layer (n · then Please refer to FIG. 2B, form a layer 206a in the trench 21o, and the first conductive layer 206a fills the trench 21o. The second deep production ... part, and this second depth D2 is more than the first The depth ^ is shallow. The material of the electrical layer 2 6 a is like polycrystalline polysilicon. The aforementioned step of the first conductive layer 206 a is, for example, first forming on the substrate 2000: ^ layer filling Full trench 21〇, and then etch this back-conductive, where the step of: engraving: layer is, for example, dry etching. "Then, remove the capacitor dielectric layer 2 04 'that is not covered by the first 2 0 6a. Subsequent steps remove 0
案號 92120052 1231974Case No. 92120052 1231974
五、發明說明(7) 隨後,請參照第2C圖,先於第一導電層2〇6&上之溝渠 2 1 0側壁上形成一間隙壁2 0 8,再以間隙壁2 〇 8及圖案化罩' 幕層203作為罩幕,移除部分第一導電層2〇6a,使第' —導 電層206a之頂面呈下凹狀,且其深度約與前述第—深度^ 相同’其中移除部分第一導電層206a例如是以乾式刻 的方式完成。其中,形成間隙壁2 0 8之步驟可以是形成一 氧化矽層209a墊層(liner)及一氮化矽層2〇9b餘列 該氮化矽層2 0 9 b及該氧化矽層2 0 9 a直到暴露出第_ ° \ 頂面2 0 6 a。另外,藉由控制本圖所示之第一導電層2 〇 6 & 了^ 面的下凹程度,可控制後續形成之埋入式領氧化^ a (buried collar oxide)的長度。前述2B圖中,^未、皮第 了導電層2 0 6a覆蓋之電容介電層204未被去除,則可^ 氬化^夕層2 0 9 b之墊層’此時則不須氧化石夕層2 〇 9 a,間隙"、卷 208則為電容介電層204及氮化矽層209b所組成。 曰” 然後,請參照第2 D圖,施行一熱氧化製程,以 凹狀的第一導電層2 0 6a之頂面、側面、及側面接 = 介電層2 0 4及基底2 0 0氧化為一熱氧化層212,其电# 熱氧化製程的參數,以期得到後續形成之埋入式二 :預定厚度。換言之,若電容介電層m為氧化芦曰 層,如氧化石夕/氮化石夕/氧電層204包括氮化矽 石夕堆疊層⑽),則可在;;::疊層⑽〇)或氮化妙/氧化 氧化製程。而去除氮化矽片、、的氮化,層後,再施以熱 導電層2 0 6a(如第2C圖)後:始方法例如是在移除部分第一 施以一濕式蝕刻製程使第一導V. Description of the invention (7) Then, referring to FIG. 2C, a gap wall 208 is formed on the side wall of the first conductive layer 206 & 2 10, and then the gap wall 208 and the pattern are formed. The mask layer 203 is used as a mask, and a part of the first conductive layer 206a is removed, so that the top surface of the first conductive layer 206a is concave, and its depth is about the same as the first depth ^. The first conductive layer 206a is partially removed, for example, in a dry-engraved manner. The step of forming the spacer 208 may include forming a silicon oxide layer 209a and a silicon nitride layer 209b. The silicon nitride layer 209b and the silicon oxide layer 20 may be formed. 9 a until the _ ° \ top surface is exposed 2 0 6 a. In addition, by controlling the degree of depression of the first conductive layer 206 & shown in the figure, the length of the buried collar oxide ^ a (buried collar oxide) formed later can be controlled. In the aforementioned 2B figure, the capacitor dielectric layer 204 covered by the conductive layer 206a has not been removed, and the cushion layer of argon layer 2 0 9b can be used. The layer 2 09a, the gap ", and the volume 208 are composed of a capacitor dielectric layer 204 and a silicon nitride layer 209b. "" Then, referring to Figure 2D, a thermal oxidation process is performed to oxidize the top surface, side surfaces, and side surfaces of the concave first conductive layer 206a = the dielectric layer 2 0 4 and the substrate 2 0 0. It is a thermal oxidation layer 212, and its parameters of the electro-thermal oxidation process are to obtain the following embedded type 2: predetermined thickness. In other words, if the capacitor dielectric layer m is an oxide layer, such as oxidized stone / nitride The oxygen / oxygen layer 204 includes silicon nitride stacked layers (i.e.,), and can be used in ;;: stacking (ii) or nitridation / oxidation and oxidation processes. The silicon nitride wafer is removed, After applying the thermal conductive layer 20a (as shown in FIG. 2C), the initial method is, for example, to remove a part of the first layer by applying a wet etching process to make the first conductive layer
1231974 __+案號 92120的9_年月 f 五、發明說明(8) ί Π :丄:移除用—濕式钱刻法來移除電 谷;丨電層2 04中的氮化矽層,如使用磷酸 基底200 保留部份間隙壁2 0 8,以在後續熱氧化製程中』&其下二 之後,請參照第2 Ε圖,去 圖),其中去除間隙壁2 〇 8之步 矽層2 0 9 b,再利用濕式蝕刻去 容介電層2 0 4。 除間隙壁2 0 8 (請見第2D 驟譬如是先去除剩餘之氮化 除剩餘之氧化矽層2 〇 9 a或電 隨後,請參照第2F圖,去除溝渠21〇令之 層”2,並暴露出第一導電層2 0 6a,以形成一』:式、;氧 化層2 1 2 a,此埋入式領氧化層2 1 2 a與擴散摻雜區2 〇 2係部 份重疊。其中去除溝渠2 1 0中之部分熱氧化層2〗2的方法例 如是乾式蝕刻。而且’舉例來說,當溝渠2丨〇之直徑約為 1 5 0 n m時為例,最終形成的埋入式領氧化層2丨2 a之長度與 厚度譬如是分別為6〇〇nm與30ηπι。 接著,請參照第2 G圖,可選擇性地於第一導電層2 〇 6 a 頂面與溝渠2 1 0側壁上形成一薄氮化石夕層(未繪示),作為 埋入式帶(BS)襯層。然後,於溝渠210中形成一第二導電 層206b,其頂面高於埋入式領氧化層212a頂端,其中第二 導電層206b之材質譬如是摻雜多晶矽。而且,形成第二導 電層2 0 6 b之步驟例如先於基底2 0 0上形成一導電層填滿溝 渠210,再回蝕刻此一導電層,以形成第二導電層206b。 綜上所述,本發明之特點在於利用製程上的設計將領1231974 __ + case number 92120 of 9_year f. 5. Description of the invention (8) ί Π: 移除: remove the valley using a wet coin engraving method; 丨 the silicon nitride layer in the electric layer 2 04 For example, if a phosphoric acid substrate 200 is used to reserve a part of the partition wall 2 0 8 in the subsequent thermal oxidation process "& the next two, please refer to Figure 2E, go to the figure), in which the step of removing the partition wall 2 08 The silicon layer 2 0 9 b is removed by wet etching to remove the dielectric layer 2 0 4. Remove the spacer 2 0 8 (See step 2D. For example, first remove the remaining nitride to remove the remaining silicon oxide layer 2 09a or electricity. Then, refer to Figure 2F to remove the layer of the trench 210 order. " The first conductive layer 206a is exposed to form one ::, oxide layer 2 1 2a, and the buried collar oxide layer 2 1 2 a partially overlaps with the diffusion doped region 202. The method for removing a part of the thermal oxide layer 2 in the trench 2 10 is, for example, dry etching. And, for example, when the diameter of the trench 2 is about 150 nm, for example, the final embedded The length and thickness of the collar oxide layer 2 丨 2a are, for example, 600nm and 30ηπ, respectively. Next, referring to FIG. 2G, the top surface of the first conductive layer 206a and the trench 2 can be selectively selected. A thin nitrided stone layer (not shown) is formed on the 10 side wall as a buried tape (BS) lining layer. Then, a second conductive layer 206b is formed in the trench 210, and its top surface is higher than the buried type. On the top of the collar oxide layer 212a, the material of the second conductive layer 206b is, for example, doped polycrystalline silicon. In addition, the step of forming the second conductive layer 206b is, for example, first A conductive layer is formed on the substrate 200 to fill the trench 210, and then this conductive layer is etched back to form a second conductive layer 206b. In summary, the present invention is characterized by the use of a process design leader
11490twf1.ptc 第14頁 1231974 五、發明說明(9) 氧化層製作成埋入式 但能提供足以防止在 device)上之漏電(le 層不會影響導電層之 產生縫隙(s e a m )的問 不會使溝渠之截面積 帶(BS)之間的接觸面 (BS)之接觸電阻(Rc_ 式領氧化層的厚度可 減,進而能增加電容 此外’相較於前案在 需二層即可完成,可 高。 雖然本發明已以 限定本發明,任何熟 和範圍内,當可作各 範圍當視後附之申請 曰 修正 的結構,因此於元件小型化之後,不 垂直寄生元件(vertical parasitic akage)的發生,還因為埋入式領氧化 填滿步驟,所以本發明不會有多晶石夕 題。再者,本發明之埋入式領氧化層 縮減,故可保持第一導電層與埋入式 積(contact area),而防止埋入式帶 B S )增加。另外,由於本發明之埋入 大幅增加’所以連帶使其長度可被縮 器之有效表面積(effective area)。 溝渠内的導電層需要三層,本發明僅 減少製程複雜度,使生產的效率提 車佳實施例揭露如上,然其並非用以 !此技藝者,在不脫離本發明之精神 f ϋ動與潤飾,因此本發明之保護 專利乾圍所界定者為準。11490twf1.ptc Page 14 1231974 V. Description of the invention (9) The oxide layer is made into a buried type but can provide enough to prevent leakage on the device (the Le layer will not affect the seam of the conductive layer) The contact resistance of the contact surface (BS) between the cross-sectional area band (BS) of the trench (the thickness of the Rc_-type collar oxide layer can be reduced, which can increase the capacitance. In addition, compared with the previous case, it can be completed with two layers. It can be high. Although the present invention has been limited to the present invention, within any scope and scope, it can be regarded as the modified structure of the attached application. Therefore, after the component is miniaturized, the vertical parasitic akage is not vertical. The occurrence of the oxide is also due to the buried collar oxide filling step, so the present invention does not have polycrystalline stones. Furthermore, the buried collar oxide layer of the present invention is reduced, so that the first conductive layer and the buried layer can be maintained. The contact area is increased, and the embedded belt BS is prevented from increasing. In addition, since the embedding of the present invention is greatly increased, the length thereof can be reduced by the effective area of the retractor. The conductivity in the trench The layer requires three layers. The present invention only reduces the complexity of the process, so that the production efficiency is improved. The preferred embodiment is disclosed above, but it is not used! This artist does not depart from the spirit of the present invention. The patent protection of the invention shall prevail.
1231974 _案號92120052_年月日 修正__ 圖式簡單說明 第1 A圖至第1 G圖係習知一種溝渠式電容器的製造流程 剖面示意圖;以及 第2 A圖至第2 G圖係依照本發明之一較佳實施例之溝渠 式電容器的製造流程剖面示意圖。 圖式標示說明 1 00,2 0 0 :基底 101 ,201 :墊氧化層 102,202 :擴散摻雜區 103,209b :氮化矽層 1 04 ·•氧化/氮化層 1 0 6 a ,1 0 6 b ,1 0 6 c :多晶矽層 1 0 8 :氧化層 1 0 8 a :領氧化層 1 1 0,2 1 0 :溝渠 2 0 3 ··圖案化罩幕層 204 :電容介電層 206a , 206b :導電層 2 0 8 :間隙壁 2 0 9 a :氧化矽層 2 1 2 :熱氧化層 2 1 2 a :埋入式領氧化層1231974 _Case No. 92120052_Year Month Day Amendment __ Drawings Brief Description Figures 1A to 1G are schematic cross-sectional schematic diagrams of the manufacturing process of a trench capacitor; and Figures 2A to 2G are based on A schematic sectional view of a manufacturing process of a trench capacitor according to a preferred embodiment of the present invention. Description of the drawings: 1 00, 2 0 0: substrate 101, 201: pad oxide layer 102, 202: diffusion doped region 103, 209b: silicon nitride layer 1 04 • oxidation / nitride layer 1 0 6 a, 1 0 6 b, 1 0 6 c: polycrystalline silicon layer 1 0 8: oxide layer 1 0 8 a: collar oxide layer 1 1 0, 2 1 0: trench 2 0 3 ·· patterned mask layer 204: capacitor dielectric layer 206a, 206b: conductive layer 208: partition wall 209a: silicon oxide layer 2 1 2: thermal oxide layer 2 1 2a: buried collar oxide layer
11490twf1.ptc 第16頁11490twf1.ptc Page 16
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