TWI231599B - Self-aligned MIM capacitor process for embedded dram and semiconductor device manufactured thereby - Google Patents

Abstract

A semiconductor device includes a group of capacitors and a trench. Each of capacitor includes a first conductive material, a dielectric layer, and a second conductive material. The dielectric layer is located between the first and second conductive material layers. The first conductive material layer coats an inside surface of a cup-shaped opening formed in an insulating layer. The trench is formed in the insulating layer. The trench extends between and crosses each of the capacitors in the group. The dielectric layer and the second conductive material layer are formed over the first conductive material layer in the cup-shaped openings and over an inside surface of the trench. The second conductive material layer extends between the capacitors of the group via the trench. Also, the second conductive material layer forms top electrodes for the capacitors of the group.

Description

1231599 V. Description of the invention (1) [Technical jaw field to which the invention belongs] w The present invention relates to a semiconductor device, and in particular, to a self-aligned metal / insulator / for an embedded dynamic random access memory / Manufacturing method of metal and metal (MIM) capacitors. [Previous technology] When we want to integrate logic circuit and DRAM array into a single chip, we should consider compatibility in design and manufacturing. FIG. 1 is a cross-sectional view of a single chip, which is a part of the conventional technology. The single chip has a logic region and a DRAM array region 32. In the DRAM region of FIG. / Insulator / Metal (MIM) capacitors 34 are used for each DRAM cell. Each metal / insulator / metal (MIM) capacitor 34 in Figure 1 includes an upper electrode to a lower electrode, with an insulated upper electrode contact design. . The continued reduction in device size requires addressing the limitations of more DRAM cell array isolation designs. In FIG. 1, as the size of the component is reduced, the overlapping margin 36 between the upper flat-plate 1-electrode contact area 38 and the bit line contact area 40 may be insufficient. In other words, due to the reduction in component size, it will not be able to provide precise The alignment process of the dish ensures that the upper electrode contact area 38 does not overlap the bit line contact area 40. In order for the DRAM device 32 to operate normally, the bit line contact area and the upper electrode 42 contact area 38 need to have a minimum margin value. Therefore, it is necessary to propose a design for improving the overlap margin 'to be suitable for the shrinking element size in future chips. [Summary of the Invention]

Page 7 1231599 V. Description of the invention (2) ---------__ The embodiments of the present invention can be used to solve the above-mentioned aspects. The present invention provides a semiconductor chip and its requirements, and several capacitor elements. And trenches, a plurality of electrical = pieces "层 on the insulation layer 'Each capacitor element contains a lower electrode part of the dielectric layer is located in the lower electrode holder j1 ^ is formed in a cup-shaped opening, the cup-shaped opening is located in the insulation: : The J electrode is formed on the electrode below the cup-shaped opening. In the second one, :: channel is connected between the capacitor elements and crosses the electricity d, bar :: ::: forms a recessed area and the trench crosses the electricity:发明 一 最好 者 # ^ t Connected to the upper part of the moving and capacitive element 1 When the upper electrode is used to shape the upper electrode material, it is specially formed by two methods. However, in another preferred conductive material And the upper electrode of the capacitor: the second yoke example is a storage capacitor, which is not the same as the second. One part of the body cell on this evening ^ 1 ", another day-by-day dynamic failure phase on the film is another basis Report # μ This month Dagger 3 logic circuit area method, = Shi, Bei Shi evil, the present invention provides a method of manufacturing Feng Bi. Dagger The legal system is based on the following steps: Steps Zhanmiao 5 First provide an intermediary structure step: the order can be formed on the layer: two; two, and then the first conductive material is coated in a cup-shaped channel in the insulating layer , Conductive material. Cheng-depression "is located in the conductive material of the first y across each cup-shaped opening. Then the dielectric is deposited according to a set including a part of the-upper electrode, lower electrode-shaped w electric layer And the upper L layer, its ^ channel is powered down [the material is located at the L pole. In the L electrical material system ^ 5 channels, the capacitor element b accesses memory ^ 〇 • changes in the body device. In structure, a conductive The inside of the material opening is then formed horizontally and horizontally. The trench-shaped material is in the middle 1231599 V. Description of the invention (3) Second, σ and σ are formed so that the dielectric material is coated on the inside of the trench, and the exposed first conductive layer is coated. The surface of the material. Then deposit a second conductive material on the structure, so that the first conductive material is coated on the inside of the trench and on the surface of the exposed dielectric material. Finally, the intermediate structure is removed. Two conductive materials. In the embodiment, the 'semiconductor device includes a dynamic random access memory cell with complex and Zhao storage capacitors, and the storage capacitor has two shaped openings. In another embodiment, the semiconductor device includes a logic, Cup and an embedded dynamic random Access memory area, wherein the access memory area has a cup-shaped opening and a capacitive dynamic state. According to an embodiment, the present invention provides a semiconductor device, including a plurality of capacitive elements. And the trench, the capacitor element is on the second, the conductor edge layer, each capacitor element includes the first conductive material layer, the second conductive material layer, and a part of the dielectric layer is located on the first and second conductive layers. Between the material layers, the inner surface of the first conductive material layer 2 material layer mouth, the cup-shaped opening is located in the insulating layer. Said, straight; ~ cup-shaped opening t, the trench extends and crosses the capacitor element, trench medicine / ditch The first and second electric cells located in the insulating layer forming a recessed area and the trench crossing the capacitor. The electric layer and the second conductive material layer in the mass layer are formed in the cup-shaped opening, the j-layer, the intermediary layer, and the inner surface of the trench. The first conductive material of the second 'two port t extends to the capacitive element i and the second conductive f is extended from the upper electrode of the trench. [Electric material layer forms a capacitive element] [Embodiment] First, please refer to the drawings described in the present invention In each not In the same view, phase 1231599 V. Description of the invention (4) " '------- The same reference numerals refer to the same elements. The drawings are not drawn according to size proportions, and for clarity, some The drawings have close-up or simplified forms. Those skilled in the art can understand the spirit of the present invention, and without departing from the spirit of the invention, they can make some modifications and equivalent changes to the embodiments of the present invention. 1 is a cross-sectional view of a single chip according to a part of the conventional technology, wherein the single chip has a logical area 30 and an embedded dynamic random access memory (DRAM) array area 32. The DRAM in FIG. 1 In area 32, a metal-insulator-metal (MIM) capacitor 34 is used for each DRAM cell. Each MI capacitor 34 includes an upper electrode to a lower electrode, which is contacted with an insulated upper electrode. the design of. As described above, in the first figure, 'as the size of the device shrinks, the overlap margin 36 between the upper plate electrode contact area 38 and the bit line contact area 40 may be insufficient. An accurate alignment process cannot be provided to ensure that the upper electrode contact region 38 does not overlap the bit line contact region 40. In order for the 元件 -element 32 to operate normally, the bit line contact region 40 and the contact region 38 of the upper electrode 42 need to have a minimum boundary value. 2-24, a method according to an embodiment of the present invention is shown. In Figure 2-24, some process steps are shown in logic and]) RAM area integrated manufacturing process. Because those skilled in the art should know the detailed methods of these processes', so each process step is not described in detail. The component layout shown in the present invention is only an embodiment. Therefore, due to the disclosure of the present invention, those skilled in the art should be The invention may be used to implement other possible component layouts. Referring first to the DRAM region 32 of FIG. 2, a gate oxide layer is deposited on a substrate 44

Page 10 1231599 5. In the description of the invention (5), the substrate 44 has a shallow trench isolation 46, and a gate material 48 (such as polysilicon) and a mask 50 (such as silicon oxynitride) are deposited and patterned. As shown in FIG. 2, the cover 50, the substrate 44 doped (LDD implanted) a part 52, and the spacer 54 are formed, and the spacer 54 is aligned to further dope the substrate. To form a source / drain region 56 (eg, N + / p + implant), as shown in FIG. 3. A self-aligned metal silicide 58 'is formed on the source / drain region 56 as shown in FIG. Moreover, in FIG. 4, a first insulating layer 60 (such as silicon oxide) is deposited and planarized (such as CMP process), and then an opening 62 is formed in the insulating layer 60 as a contact area of the logic area and a healthy area of the money area 32. The contact area of the storage node (see Figure 4). Referring to FIG. 5, a barrier layer 64 is formed in the contact opening 62, and then the contact material is filled into the opening 62, and the contact material 66 (such as tungsten) needs to be etched (such as etch back or CMP process) to remove Excess material, Ding Shi / For the surface of the flat intermediary structure. Then, as shown in FIG. 5, an f-etch stop layer 68 (for example, silicon nitride) is deposited for subsequent processes. The advantage is that the logic element 30 and the DRAM device 32 are formed at the same time. For example, the transistor and region 30 and 32 of the fifth process are optimized using the same process. The weighting steps are optimized, and the number of process steps is minimized. In so that the second insulating layer 70 is deposited and patterned to form a cup-shaped opening of a gold 6th body / metal (MIM) storage capacitor element.纟 巴 缘 Figures 7-9 show different views of the intermediary structure. In this step, a lower substrate 74 (such as titanium nitride) is deposited on the opening 72 of the capacitor element, and the electrode material is removed (such as etch back or CMP process). The excess lower electrode material is required. Structure, Figure 7 is a top view of DRAM; Figure 8 is formed along Figure 7

Page 11 1231599

A cross-sectional view of the icon line 18; FIG. 9 is a cross-sectional view taken along the curve 9 in FIG. Although the cup-shaped opening 72 has an oval cross-section and a flat bottom, the cup-shaped opening 72 may also have any different cross-section or bottom surface including a rectangular scraped surface shape, a circular cross-sectional shape, an arbitrary shape cross-sectional shape, a circular bottom surface, and a sawtooth Bottom surface or one of its combinations. Next, a curved trench 73 is formed in the quilted area 32 and traverses the position 72 of the capacitor element, as shown in FIG. Fig. 10 is a top view of the DRM area 32; Fig. 11 is an enlarged perspective view of the dashed area of the DRAM area 32 in Fig. 10)). Fig. 1 L is a sectional view taken along the 10th icon line 1 2_1 2 (Such as the cross-sectional view of curve 13'13 in Fig. 6 and Fig. 10, the structure of the second U figure is shown with a dashed line as a control; Fig. 14 A shows the curve groove of the 10th icon line 14-14 The quasi / σ edge shows a cross-sectional view along Fig. 10 \ line 13 according to the present invention; Fig. 15 is a cross-sectional view in which, for example, the channel 73 is located in the lower electrode 74 and crosses each of them. The depth and width can be changed: the position of the element 72 'varies. Although the ditch 73 has a rectangular shape == according to the design parameters of the embodiment, including different bottom sections: the ditch 73 can also be combined. 1. In addition, the ditch 73 may be a curved green hexagonal cross-sectional shape or between the positions 72, but the ditch 73 may also be bubbly and extend to the position 72 of the capacitor element, including the curve: different shapes And extends to the angular shape, the angular sine wave shape formed by a series of straight line segments, straight lines, &Amp; Arbitrary shapes or groups of them Refer to Figures 16 and 17 ’to deposit an insulating film on the photographs of Figures 15-16.

1231599 V. Description of the invention (7) " ~ " 76 'And f is distributed on the exposed surface of the lower electrode 74 (better conformal), the insulating film 76 is a high dielectric constant material 42 (such as pentoxide Hepta-O5 'gill titanate (SrTiO3, alumina ai203). After depositing the insulating film 76, an electrode material 42 (such as titanium nitride) is deposited on the insulating film 76, and then the excess electrode material is removed (such as etch-back or CMP process) to form the structure shown in FIGS. 18-20. FIG. 19 is an enlarged perspective view of a portion of FIG. 18 in the DRAM area 32 to show some capacitor elements 34 and a 肫 尥 array structure. Since the upper electrode material 42 is deposited at the position 72 of the capacitor element, the electrode material 42 used as the electric valley element 34 will also be formed in the curved trench 73 to serve as the upper electrode 42 along the curved trench 73 (see section (Figure 9) The contact pads 38 or 疋 are electrically connected. Therefore, by using the method of manufacturing the DRAM capacitor element 34 of the present invention (as shown in FIGS. 2-20), the contact pads 38 of the electrode 42 on the capacitor element can be self-aligned, and formed by using the upper electrode material through the trench 73. . Refer to Figures 21 and 22 and continue the process steps of logic and dram areas 30 and 32. First, use an insulating cover 80 (such as silicon oxide) to cover the rest of the capacitor opening, and cover the upper electrode material 42. After the insulating cover layer 80 is deposited, a planarization process (such as a CMP process) is performed to provide a flat upper surface overall structure. For clarity, pass through the insulating cover 80 to show the bottom structure, as shown in Figure 21. Contact pad openings 82 are formed in the logic and DRAM regions 30 and 32 and aligned with the underlying contact pads 66. An etch stop layer is used to control the etch termination point of the contact pad openings 82, and the contact pad openings 82 in the dram region 32 As a bit line contact pad 40. Referring next to FIG. 23, a barrier layer 84 is formed within the contact pad opening 82, and a contact material 86 (such as a crane) is deposited in the contact pad opening 82 and removed.

Page 13 1231599 V. Description of the invention (8) (such as etch back or CMP process) Excess contact pad material 86 to improve the top surface, as shown in Figures 23 and 24. The area 88 surrounded by the dotted line in FIG. 24 is used to emphasize the use of the same process steps to form stacked contact pads in the DRAM area, which is another advantage of the present invention. In addition, the & limit between the upper electrode 42 and the bit line contact pad 40 has been improved compared to the first figure, and the improved overlapping margin, and the self-curved trench 73 of the upper electrode 42 of the storage capacitor Alignment feature 两者, both of which can result in higher component density and / or smaller component size. Because, “: The road is clear, it will make those skilled in the technology more clearly understand the advantages and other features provided by the present invention. Those skilled in the art should clearly understand the advantages of the embodiments of the present invention. This implementation provides improved structures and processes with logic circuits and embedded thank you methods and structures described in the present invention are also applicable to other devices. For example, ΐί 欣 app. Although the present invention has disclosed in the preferred embodiment that M 2 '2 is not intended to limit the present invention, anyone skilled in the art is skilled in the art, and therefore the present invention; For example: J Qianwei is bounded by the scope of the patent application attached. The present invention is applicable to other 2 materials with different materials and different thicknesses. Therefore, it is a schematic diagram for illustration; Used to limit the invention.

Page 14 1231599

Brief description of the drawings [Simplified description of the drawings] In order to make the above and other purposes, animal rights of the present invention ^ ^. M 々, the magical break, and the advantages can be more obvious, the following is a preferred implementation For example, f is easy to understand as follows: ^ The drawings are detailed, according to the cross-sectional view of a single chip according to a part of the conventional technology, 1 ΐ = two chips have a logic area and embedded dynamic random access. (Dram) Array area; Figures 2 to 6 of Figure 2 show the cross-sectional view of the manufacturing method of the intermediary structure according to the example of Zhao Tai private Ming φ every t, Jujube ^ Ming and Bei examples; The top view of the 8th figure is shown in green? The 9th figure is shown in accordance with the $ 10th figure. The top view of the 11th structure is shown in the 1st figure. The 12th figure is shown in the 9th figure. 13 is a diagram showing the figure of Jizhao J. 14 is a diagram showing a view of the diagram of the 15th ditch of Yizhao.% Is a section view of the ditch of Yizhao. FIG. 7 is another view of the DRAM area after FIG. 6 according to the present invention. Top view of the mediation structure: T;,

1231599 on page 15 Brief description of drawings Figures 16 and 17 are cross-sectional views of an intermediary structure after Figures 5 and 5 of the present invention; Figure 18 shows the 16th and 17th according to the present invention. Fig. 19 is a top view of an intermediary structure in a dragon area after the drawing; Fig. 19 is a perspective view showing a dotted area according to Fig. 8 of the present invention; Fig. 20 is a drawing along the 18th icon line 2 according to the present invention A cross-sectional view of 〇-2〇, FIG. 21 is a top view of an intermediary structure in a dragon area after FIG. 18-20 according to the present invention; FIG. 22 is a view along the 21st icon line according to the present invention Section 22_22; FIG. 23 is a top view of the intermediary structure in the Beaulieu area after FIGS. 21 and 22 of the present invention; and FIG. 24 is a cross-sectional view along the 23rd icon line 24_24 according to the present invention. [Simple description of component representative symbols] 3 0 logical area 3 2 dynamic with 34 capacitors 3 8 electrodes connected to 42 upper electrodes 46 shallow trenches 50 curtain machine access memory touch area isolator (dram) 0 36 heavy 40 bits 44 base 48 gate Material content of 52 L-domain overlapped finite element line contact areas Substrate

Page 16 1231599 Brief description of the diagram 54 Clearance wall 5 8 Metallic oxide 6 2 Contact opening 66 Contact material 7 0 Second insulation layer 73 Ditch 7 6 Insulating film 82 Contact pad opening 86 Contact pad material 56 Source / Drain Area 6 0 First insulating layer 6 4 Barrier layer 6 8 Etching stop layer 7 2 Cup-shaped opening 74 Electrode material 8 0 Insulating cover layer 84 Barrier layer 8 8 Area surrounded by dotted lines

Page 17

Claims (1)

1231599 Scope of patent application 1 · A semiconductor device, including at least: ^: = pieces, located on at least-part of the insulation layer, each ... a wound edge ^ electrical layer is located on the lower electrode and the upper electrode at least two The pole is formed in the cup-shaped opening. The cup-shaped opening is located in the insulation. Second: the dielectric layer and the upper electrode are formed in the thunder II of the cup-shaped opening, and: trench 1 = the insulating layer. "Where the trench is connected between the two capacitors and passes over the capacitive elements, the trench is in the π-sink region of the lower electrode and the trench crosses the lower electrode; and / or a conductive material is located in the In the trench, the conductive material is electrically connected to the upper electrode of the capacitor element. 2. The semiconductor device according to item 1 in the scope of patent application, wherein when the material of the upper electrode is formed, the conductive material is formed using the upper electrode to form two Γ 3. The semiconductor device according to item 丨 of the scope of patent application, The cup-shaped opening has an oval cross-sectional shape. 4. The semiconductor device as described in item 1 of the Shenjing patent scope, wherein the cup-shaped opening has a circular cross-sectional shape. 5. The semiconductor device according to item 1 of the scope of patent application, wherein the cup-shaped opening has a rectangular cross-sectional shape. 1231599 6. Scope of patent application 6. The semiconductor device described in item 5 of the scope of patent application, wherein the trench has a curved shape. 7. The semiconductor device according to item 1 of the scope of patent application, wherein the trench has a rectangular cross-sectional shape. 8. The semiconductor device according to item 1 of the patent application scope, wherein the trench has a round bottom cross-sectional shape. 9. The semiconductor device according to item 1 of the scope of the patent application, wherein the capacitor elements are storage capacitors as part of an embedded dynamic random access memory cell on the chip, and the chip includes at least A logic circuit area. 10. A method for manufacturing a semiconductor device, comprising at least the following steps: providing an intermediary structure provided with an insulating layer on the intermediary structure; forming a plurality of cup-shaped openings L on the insulating layer and depositing a first conductive material on the intermediary Structurally, the first conductive material is coated on the inside of the cup-shaped openings; the excess first conductive material on the intermediary structure is removed; a trench is formed in the insulation layer, wherein the trench extends to the Between the cup-shaped openings and across each of the cup-shaped openings, where the trench crosses each of the cup-shaped openings, the trench forms a recessed area in the first conductive material; Page 19, 1231599 Application 6. Deposit a dielectric material on the intermediary structure, so that the dielectric material is coated on the inside of the Wuhai trench, and the exposed surface of the first conductive material is coated; A second conductive material on the intermediary structure, so that the second conductive material is coated on the inside of the trench and on the exposed surface of the dielectric material; and the excess second conductive material on the intervening structure is removed Material. 11. The method for manufacturing a semiconductor device as described in item 10 of the scope of patent application, wherein the semiconductor device includes at least a dynamic random access memory cell with a plurality of storage capacitors, and the storage capacitors are located in the cup shapes. 12. The method for manufacturing a semiconductor device as described in item 10 of the scope of patent application, wherein the semiconductor device includes at least a logic circuit area and an embedded dynamic random access memory area, wherein the embedded dynamic random access memory area The memory region has storage capacitors located in the cup-shaped openings. 13. The method for manufacturing a semiconductor device as described in claim 10, wherein the cup-shaped opening has an oval cross-sectional shape. 14. The method for manufacturing a semiconductor device according to item 10 of the scope of patent application, wherein the cup-shaped opening has a circular other-surface shape. 15. The method of manufacturing a semiconductor device as described in item 10 of the scope of patent application 1231599 —- a '— method ~', wherein the cup-shaped opening has a rectangular cross-sectional shape. 16. The method for manufacturing a semiconductor device as described in item 10 of the scope of patent application, wherein the trench has a curved shape. The method for manufacturing a semiconductor device according to item 10 of the scope of patent application, wherein the trench has a rectangular cross-sectional shape. 18 '' The method of manufacturing a semiconductor device as described in item 10 of the scope of patent application, wherein the trench has a round bottom cross-sectional shape. 19 _ r * — A semiconductor device including at least: ^ j capacitor elements located on at least a portion of an insulating layer, each of which includes at least a first conductive material layer, a dielectric layer, and A second material layer, at least a part of the dielectric layer is located between the first conductive material layer and the second conductive material layer. The first conductive material layer is coated with a cup-shaped opening. The inner surface of the cup-shaped opening is located in the insulating layer; and A piece / ditch 'is located in the insulation layer, the trench extends and traverses the capacitors. The trench forms a recessed area in the first conductive material layer and the trench passes over the first conductive material of the capacitors. Layers, the dielectric layer and the first conductive material layer are formed on the first conductive material of the cup-shaped opening and on the inner surface of the trench, so that the second conductive material layer extends to the vias through the trench. On the capacitor element and making the second conductive material layer Page 21 1231599 6. Scope of patent application The upper electrodes of these capacitor elements are formed. 20. The semiconductor device as described in claim 19, wherein the cup-shaped opening has an elliptical cross-sectional shape. 21. The semiconductor device according to claim 19, wherein the cup-shaped opening has a circular cross-sectional shape. 22. The semiconductor device according to claim 19, wherein the cup-shaped opening has a rectangular cross-sectional shape. 23. The semiconductor device as described in claim 22, wherein the trench has a curved shape. 24. The semiconductor device according to item 19 of the application, wherein the trench has a rectangular cross-sectional shape. 25. The semiconductor device according to item 19 of the scope of patent application, wherein the trench has a round bottom cross-sectional shape. 2 6. The semiconductor device according to item 19 of the scope of the patent application, wherein the capacitor elements are storage capacitors as part of an embedded dynamic random access memory cell on the chip, and the chip At least one logic circuit area is included. Page 22