TWI231565B - Capacitor structure and the fabrication method thereof - Google Patents

Abstract

A method of forming a high density capacitor structure. An insulation layer having a first conductive layer is provided. A dielectric barrier layer is formed over the insulation layer. A first capacitor structure, including an upper electrode, a dielectric layer and a lower electrode, is formed on part of the barrier layer. An intermetal dielectric layer is formed over the first capacitor structure. Second and third conductive layers are embedded in the intermetal dielectric layer. The second conductive layer electrically connects the upper electrode and the first conductive layer. The third conductive layer electrically connects the lower electrode. Thus, a second capacitor structure is constructed by the lower electrode, the barrier layer and the first conductive layer.

Description

1231565 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a capacitor structure and a manufacturing method thereof, and particularly to a metal-insulation integrated into a damascene interconnect process Structure of metal-insulatorietal (MIM) capacitors and manufacturing methods thereof 0 Prior art capacitors are key passive components in today's semiconductor integrated circuits, such as are often used in mixed signal (MS) circuits, radio frequency (RF) Circuits, analog and digital 4-bit circuits, and more. Traditional capacitor structures in integrated circuits include metal-insulat0r — semic () nduct () r (M IS) capacitors, PN junction capacitors, and polycrystalline silicon-insulator-polycrystalline silicon (polysilicon-insulator-polysiiicon, ρΙρ) and the like. However, these conventional capacitors include at least one silicon layer as a capacitor electrode, so they have the disadvantages of higher series resistance and instability in high-frequency circuits. Therefore, in recent years, the -capacitance capacitor has been developed to provide lower series resistance, low power loss and other characteristics, and can meet the application of today's mixed signal (MS) Π circuits. In addition, to improve performance, today's integrated circuits often use metal damascene processes. Due to the integration of the inlay interconnecting process, the agricultural capa of the Mm Book Electric Co., Ltd. is completed; the unit capacity is the first! The a ~ i C diagram is a schematic cross-sectional view of the traditional important process of f. MIMIM capacitor for interconnect process

0503-9696TWf (Nl) >TSMC2002-1305; jacky.ptd 1231565 V. Description of the invention (2) First, referring to FIG. 1A, an insulating layer such as a Si02 layer is formed on a substrate 100 first. 102. The substrate 100 may include desired components:! = Body or other semiconductor elements, etc., which is simple here. No, the substrate 100 is represented by a flat substrate. Next, a conventional copper damascene process and a chemical mechanical polishing process are used to form a first copper layer 104 (as a conductor / wire line) to be embedded in the insulating layer 102. Then, for example, SiC is formed A barrier layer (also known as an etch barrier layer or a protective layer, here referred to as a barrier layer) 106 on the insulating layer 102 and covering the first copper layer 1 The barrier layer 106 can prevent the first copper layer from being oxidized by subsequent processes. Then, according to the process requirements, an oxide layer such as a Si02 layer can be formed on the barrier. On layer 106, the oxide layer 108 is used as an etching stop layer in the subsequent contact / plug. Of course, the barrier layer 1 06 can be directly used as The money is engraved with a barrier layer when contacting the window at a later time. Then, a first metal layer 110, a dielectric layer 112, and a second metal layer 114 are sequentially formed on the oxide layer 108. Next, 'Please Referring to FIG. 1B, first pattern the second metal layer 114 to form a capacitor top metal (CTM) 114. Then, refer to FIG. 1B. The dielectric layer 112 and the first metal layer no are formed to form a dielectric valley layer 112 and a bottom electrode plate (capacitor bottom metal, CBM) 11 0 '. Thus, the upper electrode plate 114' and the capacitor dielectric The electric layer 112 'and the lower electrode plate 11 0' form a capacitor structure C. Secondly 'Please refer to FIG. 1C to form an inner metal dielectric layer

0503-9696TWf (Nl); TSMC2002-1305; jacky.ptd Page 7 1231565 V. Description of the invention (3) (intermetal dielectric layer, IMD) 116 covers the capacitor structure C. The inner metal dielectric layer 6 is, for example, a s% layer. Then, a second copper layer 118, a third copper layer 120, and a fourth copper layer 12 are formed in the inner metal dielectric layer 116 by using a conventional copper damascene process and a chemical mechanical polishing (CMp) process. . The second copper layer 118 is electrically connected to the first copper layer 104 through a contact plug 130, thereby forming an interconnect structure. The third copper layer 20 is electrically connected to the lower electrode plate 110 through a contact plug 132, and the fourth copper layer 122 is electrically connected to the upper electrode through a contact plug 134. The electrode plate 114, and the third copper layer 120 and the fourth copper layer 122 are electrically connected to power supplies of different polarities (+ / a). It can be known from the above 5 that the traditional M i M capacitor structure c integrated into the damascene interconnection process is composed only of the upper electrode plate 114, the capacitor dielectric layer 112 ′ and the lower electrode plate 110 in the same inner metal dielectric layer 116. , So if you want to increase the capacitance, you must increase the horizontal area of the capacitor C '. However, this will affect the development of reducing the area. ^ National Patent No. 641 38 1 5 discloses a _capacitor process integrated into the damascene interconnect. The feature of this method is that it can simultaneously form -dual damascene wires and _capacitors using lithography. However, the method of forming a dual-damascene wire and a capacitor of ΜIM in a metal dielectric layer between ^ Α ^ ^ lj does not disclose how to increase the capacitance. U.S. Patent No. 6,459,562 discloses a kind of MIM capacitor system. The characteristics of this method are as follows: it can be treated greenly and it can increase the reliability of the capacitor, so as to continue to order water and utilization. Form a stacked type of electricity

0503-9696TWf (Nl); TSMC2002-1305; jacky.ptd Page 8 1231565 V. Description of the invention (4) Capacitive dielectric layer can increase the reliability of the capacitor. However, the MIM capacitor disclosed in this method is located in an inner metal dielectric layer, and it does not disclose how to increase the capacitance. U.S. Patent No. 6,472,721 discloses a manufacturing process of a MEMS capacitor integrated into a mosaic interconnect. The method is characterized by using only a photomask to simultaneously form an interconnection lead and a MEMS capacitor. However, this method forms interconnecting wires and MI capacitors in the same inner metal dielectric layer, and does not disclose how to increase the capacitance. SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide a capacitor structure and a manufacturing method thereof. 〃 One with high density

Another object of the present invention is to provide a _IMM capacitor process. The invention provides a process for interconnecting inlays, which includes a manufacturing method of the following steps. It is integrated in a gold metal layer on a weekly basis. The substrate has a first-metal layer and a first-layer dielectric resistance. A barrier layer is formed on the insulating layer and the second metal layer; and, $ 9, and covers the first gold in order to form a third metal layer in sequence, on the barrier layer; and the electrical layer and a first layer The four metal layers pattern the fourth metal layer to form a first capacitor structure, an electrode plate, and a capacitor dielectric.

1231565 V. Description of the invention (5)-with a second electrode plate; forming an inner metal dielectric layer (IMD) to cover the first capacitor structure; and performing a metal damascene process to form a fifth metal layer and a sixth A metal layer and a seventh metal layer are in the inner metal dielectric layer, wherein the fifth metal layer is electrically connected to the first electrode plate through a first plug and a first plug is electrically connected to the first metal layer. A metal layer, and the sixth conductor layer is electrically connected to the second electrode plate through a ^ three plugs, so that the second electrode plate, the early P-layer and the first metal layer constitute a second A capacitor structure, and the seventh metal layer is electrically connected to the second metal layer through a fourth plug; wherein the fifth conductor layer and the sixth conductor layer are power sources with different electrical polarities, respectively. ^ The present invention also provides a capacitor structure including: a substrate having an insulating layer with a first conductor layer; a dielectric barrier layer formed on the insulating layer and covering the first-layer body layer; A first capacitor structure is formed on part of the barrier layer, and the first and second capacitor structures are formed by an upper electrode plate, a dielectric layer and an inner metal dielectric layer (IMD) charged by the lower electrode plate. Yu last name of the first capacitor; and ,. A second conductor layer and a third conductor layer are embedded in the eight layers, wherein the second conductor layer is electrically connected to a dielectric electrode plate through a first plug and a second plug. The plug is electrically connected to the first conductor layer, and the upper conductor layer is electrically connected to the lower electrode through a third plug.

0503-9696TWf (Nl); TSMC2002-1305; jacky.ptd Page 10 1231565 V. Description of the invention (6) " 一 · 一 ^^ ~, = pole plate, the barrier layer and the first conductor layer system A second capacitor structure; wherein the second conductor layer and the third conductor layer are electrically connected to power sources of different polarities, respectively. In this way, according to the method of the present invention, it is possible to effectively use the space between the two metal dielectrics and to greatly increase the unit capacitance. Moreover, the present invention is easy to integrate into the mosaic interconnect without additional processes. Furthermore, the present invention can be extended to multiple interconnection processes, and the unit capacity is increased. In order to make the above and other objects, features, and advantages of the present invention clearer, ”page 1 hereinafter, the preferred embodiments are specifically described, and in accordance with the accompanying drawings, detailed descriptions are as follows: ° Refer to Figs. 2 to 4 for a schematic cross-sectional view of the manufacturing process of the MIM capacitor integrated in the damascene interconnect process of the present invention. It should be particularly explained here that although this embodiment takes the MIM capacitor as an example, the material of the valley structure is not limited in the present invention, and the material of the metal inlay is also not particularly limited. First, please refer to FIG. 2 to provide a semiconductor substrate 200, such as a Shi Xi wafer. In this embodiment, the substrate 2000 may include different elements, such as transistors, diodes, and other conventional semiconductor elements (not shown in FIG. 4). In addition, the substrate 200 may also include other metal interconnect layers (not shown). In order to simplify the illustration, only a flat substrate 200 is shown here. Then, an insulating layer 2 02 having a thickness of 1 ow-k (low dielectric coefficient), such as a S i 0? Layer, is formed on the substrate 200.

1231565 V. Description of the invention (7) Still referring to FIG. 2, a first metal layer 204 and a second metal are formed using a conventional metal inlay process (here, a copper inlay process is taken as an example) and a chemical mechanical polishing (CMP) process A layer 206 (the second metal layer 206 is regarded as a conductor, a runner / wire line) is embedded in the insulating layer 202. The metal layer 2 04/20 6 is, for example, a copper layer, and of course, it may be an aluminum layer or an aluminum-copper alloy layer. Thereafter, for example, a barrier layer (also referred to as an etch barrier layer or a protective layer, which is referred to herein as a barrier layer), which is preferably a dielectric layer containing no oxygen, is formed by a deposition method. 2 8 on the insulating layer 202 and covering the delta metal layer 204 and the second metal layer 206, the barrier layer 208 can prevent the metal layers 204, 206 from being oxidized by subsequent processes, wherein the barrier layer 208 For example, it is a SiC, Si N, Si ON, or SiCN layer, etc., and the thickness of the barrier layer 208 is, for example, 200 to 12 Angstroms (A). Then, a dielectric oxide layer 21 such as a Si02 layer (eg, TEOS, PE0X), SiN, SiON, or a multilayer composite material may be formed by the deposition method according to the needs of the process, and the barrier layer 2 is formed. 8 on 'The oxide layer 2 10 is used as an etching stopper during subsequent etching of the contact / plug. It should be particularly noted here that the oxide layer 2 10 is not necessarily required, and the etching process at that time may need to be adjusted. Then, through the deposition method, a third metal layer 2 1 2, a ❿ dielectric layer 214 and a fourth metal layer 216 are sequentially formed on the oxide layer 210 (or the barrier layer 208). The metal layers 212, 216 are, for example, Ta, TaN, Ti, TiN, or A 1 layers, and the like, and the individual thicknesses of the metal layers 2 1 2, 2 16 are, for example, 2000 to 2000 Angstroms (A). The material of the dielectric layer 214 may be a high dielectric material or a low dielectric material.

0503-9696TWf (Nl); TSMC2002-1305; jacky.ptd Page 12 1231565 V. Description of the invention (8) Materials' In order to get light thunder & & Anyway, 7Ϊ. So it ’s better to choose high dielectric

^ n〇) ^ Si〇N ^ Tax〇y (^, J ^ Ta2〇5) ^ AixOy (^ J 214) 3 户 # xy (say, for example, ㈣2) or its composite layer, etc., and the dielectric layer The maximum degree is, for example, 2000 to 500 angstroms (person). For a moment, referring to FIG. 3, first pattern the fourth metal layer 2 1 6 and form a lightning screen 5 η electrode-plate 21 6 5 is the upper electrode plate). Then, the second metal layer 212 is patterned to form a capacitive dielectric layer 214, and a J-electrode plate 212, (ie, a lower electrode plate). Thus, the electrode plate 216, " Electric layer 214, and the second electrode plate 216, constitute a first capacitor structure CJ on part of the barrier layer 208 (or the oxide layer 21). To be explained here, the dielectric layer is patterned. 214 and the third metal layer 212 may be the same etching step or divided into two-stage etching steps, and the above-mentioned patterning process steps are not limited herein. 〃 Secondly, please refer to FIG. 4 to form an inner metal dielectric layer ( intermetal dielectric layer (IMD) 218 covers the first capacitor structure ci. The inner metal dielectric layer 218 is, for example, a Si02 layer, a phosphosilicate glass layer (PSG), a borophosphosilicate glass layer (BPSG), or a fluorine-doped layer. An insulating layer with a glass fiber layer (FSG) or black diamond (black diamond) material and the like having a 10w-k (low dielectric constant) can be formed by a CVD method or a spin-on method. Next, the conventional copper inlaying process and chemical mechanical polishing (CMp) Φ system are used to form a metal layer 220, The sixth metal layer 222 and a seventh metal layer 224 are in the far-end metal dielectric layer 218, wherein the fifth metal layer 220 is electrically connected to the first electrode through a first plug (p 1 ug) 226 The board 216 'and a second plug 228 are electrically connected to the first metal layer 204, and the

0503-9696TWf (Nl); TSMC2002-1305; jacky.ptd page 13 1231565

The sixth conductor layer 222 is electrically connected to the second electrode plate 212 'through a third plug 2 30, so that the second electrode plate 212', the barrier layer 20 (including j > Chemical layer 210) and a side metal layer 204 constitute a second capacitor structure c 2 and the seventh metal layer 224 is electrically connected to the first metal layer 2 through a fourth plug 232 0 to form an interconnect structure. Among them, the fifth conductive X body layer ^ 2 2 0 and § 苐 苐 six conductor layer 2 2 2 are respectively electrically connected to different polarities ^ ~; Since this embodiment uses the copper inlay process as an example, the above-mentioned metal layers 220, 22, and 24 may be aluminum layers or aluminum-copper alloy layers. The above-mentioned plugs 226, 228, 230, and 232 are copper plugs that pass through the inner metal dielectric layer 21 8. Of course, the material of these plugs can also be conductive materials such as none, crane, etc. ~ Figure 6A shows the capacitor circuit diagram compared to Figure 4. It can be known from the above description that the MEMS capacitor CTQtal of this embodiment integrated in the inlay interconnect process CTQtal = C1 + C2. Therefore, this embodiment can increase the capacitance without affecting the reduction of the area of the element. That is, the present invention utilizes the vertical direction space of each insulating layer (IMD layer) to form a stacked capacitor structure in parallel with each other, which can greatly increase the capacitance. Furthermore, the inventors have proved through experiments that the MU unit capacitance (f F / // m 2) of this embodiment is about 1.5 times the conventional MU unit capacitance, and the MU breakdown voltage of this embodiment Same as traditional MIM. That is, the method of the present invention can provide a high-density MIM capacitor and still have excellent quality reliability. Modification

1231565 V. Description of the invention (ίο) This modification is a generalization of the above embodiment, that is, the invention can also be applied to multiple interconnecting processes. In the following, FIG. 5 is used to explain the manufacturing of this modification. It should be particularly noted here that the process part of this modification that is the same as or similar to the previous embodiment is not described in detail. In addition, in order to simplify the illustration and explanation, the conventional internal wiring part is not shown in Figure 5, and only the capacitor part characteristic of this case is explained. Referring to FIG. 5, a substrate 500 is first provided. Then, a plurality of insulating layers 5 are formed on the substrate 500, and each insulating layer 510 has, for example, a conductive layer (A / B) inlaid, and the conductive layers (A / B) are here It is divided into a first group of conductors f (A) and a second group of conductor layers (B) in the ABABAB ... arrangement pattern, wherein the uppermost layer of the first group of conductor layers (A) is located in the second group of conductor layers (β ). Among them, the insulating layers 510 are, for example, 802 layers, and the conductive layers are, for example, a copper layer, and of course, they may also be aluminum layers or aluminum-copper alloy layers. Then, a dielectric barrier layer 52 is formed on the insulating layer 51 and covers the uppermost layer of the first group of conductor layers (A). The barrier layer 520 is preferably a dielectric layer that does not contain oxygen, such as Sic ^ or "(CD). This step may further include forming a dielectric etch barrier layer (not shown) on the barrier layer. On 520, the etch stop layer is, for example, a thin layer. However, a first capacitor structure C 丨 is formed on a part of the barrier layer 5 2 0, and the first capacitor structure C1 is formed by an upper electrode plate 53 (). A dielectric layer 54Q and a lower electrode plate 550 are formed. Then, an inner metal dielectric layer (IMD) 56 is formed to cover the structure C1.

1231565, description of the invention (11), and then 'perform a metal damascene process (such as a copper damascene process) to form a first metal layer 570 and a second metal layer 580 in the inner metal dielectric layer 560' The first metal layer 570 is electrically connected to the upper electrode plate 530 through a first plug electrically 590 and a plurality of second plugs is electrically connected to the first group of conductive layers (A) 5 92, and the second metal The layer 5 80 is electrically connected to the lower electrode plate 54 through a third plug electrically 5 94 and a plurality of fourth plugs 596 are electrically connected to the second group of conductor layers (B). Thus, the lower electrode plate 540, The uppermost layer of the barrier layer 520 and the first group of conductor layers (a) constitutes a second capacitor structure C2 ', and the first and second groups of conductor layers (A / B) and the insulating layers 51. It constitutes a plurality of third capacitor structures ㈡. The above-mentioned metal layer 57, 580 may be a copper layer, a layer, or an aluminum-copper alloy layer, and the plugs 59, 592, 5 94, 5 96 may be copper, aluminum, or tungsten plugs, It passes through the dielectric layer 56 and the insulating layer 5 10. The first metal layer 570 and the second metal layer 580 are respectively electrically connected to power supplies of different polarities (+/−). From the above description, it can be seen that the capacitance of M I μ [Total = Cl + C2 + nxC3 (η is greater than or equal to 1) in this modification. Therefore, this modification can increase the capacitance without affecting the reduction in the area of the device. In other words, the present invention uses a vertical space of each insulating layer (IMD layer) to form a stacked capacitor structure in parallel with each other, which can greatly increase the capacitance. Figure 6B shows the capacitor circuit diagram compared to Figure 5. The features and advantages of the present invention The present invention provides a method for manufacturing a capacitor structure.

0503-9696TWf (Nl) i TSMC2002-1305; jacky.ptd page 16 1231565 V. Description of the invention (12) Including providing a substrate having an insulating layer with a first conductor layer; forming a dielectric A barrier layer is on the insulating layer and covers the first conductor layer; a first capacitor structure is formed on part of the barrier layer, and the first capacitor structure is composed of a first electrode plate, a dielectric layer and a Formed by a second electrode plate; forming an inner metal dielectric layer (IMD) to cover the first capacitor structure;

And performing a damascene process to form a second conductor layer and a third conductor layer in the inner metal dielectric layer, wherein the second conductor layer is electrically connected to the first electrode plate through a first plug and A second plug is electrically connected to the first body layer, and the third conductor layer is electrically connected to the second electrode plate through a third plug, so that the second electrode plate, the barrier layer and the The first conductor layer constitutes a second capacitor structure; wherein the second conductor layer and the third body layer are electrically connected to power sources of different polarities, respectively. In this way, according to the method of the present invention, the space of each inner metal interlayer can be effectively used, and the unit capacitance can be greatly improved. In addition, it can be easily integrated into the mosaic interconnect without additional processes. ^ The present invention can be extended to multiple interconnected processes, and the unit is increased. Although the present invention has been disclosed as above with a preferred embodiment, it does not limit the present invention. Anyone skilled in this art will not be distressed.

And within the scope ”shall be subject to various modifications and retouching. Therefore, the date of issue = scope shall be determined by the scope of the attached patent application. Guarantee

1231565 The diagram briefly illustrates that the first 1 ~ 1C diagram is a process cross-sectional schematic diagram of a conventional MIM capacitor integrated in a damascene interconnect process; the second to fourth diagrams are MIM capacitors integrated in a damascene interconnect process according to an embodiment of the present invention. A schematic cross-sectional view of the manufacturing process; Figure 5 and Figure 5 are cross-sectional yellow diagrams showing a modified example of the embodiment of the present invention; Figure 6A is a capacitor circuit diagram compared to Figure 4; and "Figure 6B is a diagram showing Figure 5 Capacitance circuit diagram. Symbol description knowledge 0 4 8 2 0 4 8 Γυ Λυ Au 1i 11 11 11 Α board 1 罾; ·, 罾 罾 pole ^ / C; copper layer ^ Μ copper copper eight blades tTfJlf-S part of the basic oxygen, and the first figure plug collision; contact; layer by layer of electricity ·, ~ electricity 4 •, ·, belong to the interlayer 3 layers of gold and gold; belong to copper, capacitor 、 Front barrier one two electric gold three 32 first resistance first inner first 1--~ ^ 26042600 ηυ ο 11 11 11 11 οο 11 11 11 11 11 11 11 11 Part of this case (No. 2 ~ 4 Figure 20 0 ~ substrate; 204 ~ first metal layer; 208 ~ barrier layer; 212 ~ third metal layer; Figure 6A) 2 0 2 ~ insulating layer; 206 ~ second metal 21 0~ oxide layer; 214~ dielectric layer;

0503-9696TWf (Nl); TSMC2002-1305; jacky.ptd page 18 1231565 Brief description of the diagram 2 1 2 '~ lower electrode plate; 2 1 6' ~ upper electrode plate; 220 ~ fifth metal layer; 224 ~ Seven metal layers; 2 2 8 ~ second plug; 2 3 2 ~ fourth plug; C 2 ~ second capacitor structure. 216 ~ fourth metal layer; 214 '~ capacitor dielectric layer; 218 ~ inner metal dielectric layer 222 ~ sixth metal layer; 2 2 6 ~ first plug; 2 3 0 ~ third plug; C1 ~ A capacitor structure; part of this case (Figures 5 and 6B) 500 ~ substrate; A ~ first group of conductor layers; 5200 ~ barrier layer; 540 ~ dielectric layer; 560 ~ inner metal dielectric layer 5 8 0 ~ the second metal layer; 5 9 2 ~ the second plug; 5 9 6 ~ the fourth plug; C2 ~ the second capacitor structure; 5 1 0 ~ the insulating layer; B ~ the second group of conductor layer 5 3 0 ~ upper electrode plate; 5 5 0 ~ lower electrode plate; 570 ~ first metal layer 5 9 0 ~ first plug; 594 ~ third plug; C1 ~ first capacitor structure C3 ~ third capacitor structure i

0503-9696TWf (Nl); TSMC20024305; jacky.ptd page 19

Claims (1)

1231565 Case No. 92117373 hO is a revised version. Patent application scope 1 · A method of manufacturing a capacitor structure, including the following steps: Provide a substrate with an insulating layer containing a first conductor layer formed thereon. A first dielectric layer is on the insulating layer and covers the first conductor to form a first capacitor structure on part of the third dielectric layer. The first capacitor structure is composed of an upper electrode plate and a second dielectric. The first capacitor structure is formed by an inner metal dielectric layer (IMD); the A conductor layer and a third conductor conductor layer are electrically connected by a first plug The first performs a double damascene process to form a first: layer in the inner metal dielectric layer, a continuous plug electrically connects the upper electrode plate and a first conductor layer, and the third conductor layer is a first / second layer. The three plugs are electrically connected to the lower electrode plate, so that the lower electrode plate, the 〆 层 dielectric layer and the first conductor layer form a second capacitor structure; wherein the second conductor layer and the 誃 conductor layer system Electrically connect power sources with different polaritiesz 〆 2 · The manufacturer of the capacitor structure according to item 1 of the scope of patent application, wherein the first conductor layer is a steel layer, an aluminum layer, or an aluminum-steel alloy layer. 3 · According to the scope of the patent application, where the insulating layer is the manufacturer of the electric valley #yttrium structure described in your item 4. As the scope of the patent application-the dielectric constant of the oxide layer. The first dielectric layer is a manufacturer of the valley structure described above, and a barrier layer containing no oxygen. Method Method 0503-9696TWFl (Nl); TSMC2002-1305; JACKY.ptc I Circle Amendment 1231565 VI. Patent application range 92117373 5 · The manufacturing method of the electric valley structure as described in item 4 of the patent application range, wherein the barrier layer is Sic, SiN or SlCN ° — 6 · As described in item 1 of the patent application range The manufacturing method of the valley structure further includes forming an etch stop layer on the first dielectric layer. 7. The method for manufacturing an electric valley structure according to item 6 of the scope of the patent application, wherein the etching stopper layer is a 3 〇2 layer. 8. The manufacturing method of the capacitor structure according to item 1 of the scope of the patent application, wherein the dual damascene process is a copper dual damascene process. 9 · The manufacturing method of the capacitor structure as described in item 1 of the scope of patent application, wherein the second and third conductor layers are copper layers. 1 〇 The method for manufacturing a capacitor structure as described in item 1 of the scope of patent application, wherein the first, second and third plugs are copper, aluminum or tungsten plugs. 11 · A method for manufacturing a capacitor structure, including the following steps: providing a substrate; forming a plurality of insulating layers on the substrate, and each insulating layer has a conductor layer, and the conductor layers are arranged above and below ABABAB ... Divided into a first group of conductor layers (A) and a second group of conductor layers (B), where the uppermost layer of the first group of conductor layers is located above the uppermost layer of the second group of conductor layers, forming a first A dielectric layer is on the insulating layer and covers the uppermost layer of the bulk layer; a first capacitor structure is formed on part of the first dielectric layer, and the structure consists of an upper electrode plate, a second dielectric layer, and a lower layer. Electricity ;: composition; forming an inner metal dielectric layer (IMD) to cover the first capacitor structure; 1231565 And metal dual damascene process to form a first metal layer and a second dielectric layer, wherein the first metal layer is connected to the upper electrode plate and a plurality of second plugs electrically connected to the conductor layer by one connection. And the second metal layer is electrically connected to the second set of the lower electrode plate, the first dielectric layer and the first conductor layer through a third plug electric electrode plate and a plurality of fourth plugs. Two capacitor structures, and the first and second sets of conductor layers and the plurality of third capacitor structures; the first metal layer and the second metal layer are respectively electrically connected to a power source. A metal layer is electrically connected to the first plug to connect the first group to the lower conductor layer, if it constitutes a first-class insulation layer, among them, of different polarities, 1 2 The manufacturing method of the capacitor structure described above, wherein the insulating layer is an oxide layer having a low dielectric constant. 1 3 · The manufacturing method of the capacitor structure described in item 11 of the scope of the patent application ', wherein the conductor layers are a copper layer, a | g layer, or a copper alloy layer. 14 · The method for manufacturing a capacitor structure according to item 丨 丨 of the scope of patent application ', wherein the first dielectric layer is an oxygen-free barrier layer. 1 5 · The method for manufacturing a capacitor structure as described in item 4 of the patent application scope, wherein the barrier layer is Sic, SiN or SiCN. 16 · The method for manufacturing a capacitor structure according to item 11 of the scope of patent application, further comprising forming an etch stop layer on the first dielectric layer. 17 • The method for manufacturing a capacitor structure as described in item 16 of the scope of patent application, wherein the etch stop layer is a SiO 2 layer. 1 8 · Manufacturer of capacitor structure as described in item 11 of the scope of patent application ! 231565 " ^ --------------- Patent application scope ^ The double and embedded process is a copper double inlaid process. I ^ Manufacturing of the capacitor structure described in item 11 of the patent scope ^ 1 Φ ^ First, the second metal layer is copper, aluminum or aluminum-copper alloy Zhanpen · Manufacture of the capacitor structure described in item 11 of the patent scope The first, second, and second offices of Xianxian do Guyi ^ & from a μ 焱 tungsten plug. Achievement 2 1 · A manufacturing method for a capacitor structure includes the following steps: a metal layer, the substrate having an insulating layer inlaid with a first metal layer and a second corrugated layer; layers and layers On the insulating layer and covering the first metal layer, the second metal layer, the fourth dielectric layer and the fourth metal layer, the four metal layer, the second dielectric layer and the third metal dielectric; ^ 第 第A first electrode plate, a capacitor layer and a second electrode plate of a capacitor structure; and forming an inner metal dielectric layer (IMD) to cover the first capacitor structure; forming a first metal structure with metal Five metal layers, -sixth, a metal layer and a seventh metal layer in the inner metal dielectric layer, 1 gold, the layer is electrically connected to the first electrode plate through the -first plug = the first metal layer And the sixth conductor layer is electrically connected to the second electrode plate through a second plug, so that the second electrode plate, the sixth modification method, and the second and fourth plugs are copper and tin. Well suitable for integration in metal 0503-9696TWF1 (Nl); TSMC2002-1305; JACKY.ptc p.231231565 _case number 陴 1: ^ 3 year month ^^ __ VI. Patent application scope > First dielectric layer and the first metal layer A second capacitor structure is formed, and the seventh metal layer is electrically connected to the second metal layer through a fourth plug; wherein the fifth conductor layer and the sixth conductor layer are respectively electrically connected differently. Polarity power. 2 2 · The method for manufacturing a capacitor structure according to item 21 of the scope of the patent application, wherein the first and second metal layers are a copper layer, an aluminum layer, or an aluminum-copper alloy layer. 2 3 · The method of manufacturing a capacitor structure according to item 21 of the scope of patent application ', wherein the insulating layer is an oxide layer having a low dielectric constant. 24. The method of manufacturing a capacitor structure as described in item 21 of the scope of patent application, wherein the first dielectric layer is a barrier layer containing no oxygen. 25. The method for manufacturing a capacitor structure as described in item 24 of the patent application scope, wherein the barrier layer is SiC, SiN or SiCN. 26. The method for manufacturing a capacitor structure according to item 21 of the scope of patent application, further comprising forming an etch stop layer on the first dielectric layer. 27. The method for manufacturing a capacitor structure as described in item 26 of the scope of patent application, wherein the etch barrier layer is a Si02 layer. 28. The manufacturing method of the capacitor structure according to item 21 of the patent application scope, wherein the third and fourth metal layers are Ta, TaN, Ti or TiN layers. 29. The method for mounting a capacitor structure as described in item 21 of the scope of patent application, wherein the second dielectric layer is Si02, SiN, SiON, Taxoy, AlxOy, HfxOy, or a composite layer thereof. ., 3 0 · The method of assembling a capacitor structure as described in item 21 of the scope of patent application, wherein the metal double inlay process is a copper double inlay process. 0503-9696TW1 (N1); TSMC2002-1305; JACKY.ptc page 24 1231565 31. A capacitor structure, comprising: when the substrate has a ~ -conductor layer-insulating layer; a dielectric layer formed on the insulating layer and covering the first conductor layer; formed on part of the first On the dielectric layer, the first plate, a second dielectric layer and the lower electrode plate have a first-capacitance structure, and a capacitor structure is formed by an upper electrode; an inner metal dielectric layer (IMD) and formed on the The first capacitor structure is embedded in the third conductor layer, # is inlaid by a dual inlay method, and 1 electrical layer, wherein the second conductor layer is connected to the upper electrode plate and a second plug through a first The plug is electrically connected to the first-said 'and the third conductor layer is electrically connected to the lower two through a third plug, otherwise' the lower electrode plate, the first dielectric layer and the first conductor The layer system constitutes a second capacitor structure; wherein the second conductor layer and the third conductor layer are respectively electrically connected to power sources of different polarities. 32. The capacitor structure as described in item 3 of the patent application scope, wherein the first conductor layer is a copper layer, an aluminum layer, or an aluminum-copper alloy layer. 3 3 The capacitor structure according to item 31 of the scope of patent application, wherein the insulating layer is an oxide layer having a low dielectric constant. 34. The capacitor structure as described in claim 31, wherein the first dielectric layer is an oxygen-free barrier layer. 35. The capacitor structure described in item 34 of the scope of patent application, wherein 1231565 The barrier layer is SiC, SiN or SiCN. 36. The capacitor structure described in item 31 of the scope of patent application, further comprising a first barrier layer formed on the first dielectric layer. 37. The capacitor structure according to item 36 of the application, wherein the etch stop layer is a Si02 layer. X 38. The capacitor structure described in item 31 of the scope of the patent application, wherein the second and third conductor layers are copper, aluminum or aluminum-copper alloy layers. 39. The capacitor structure according to item 31 of the scope of patent application, wherein the first, second and third plugs are copper, aluminum or tungsten plugs. 40. The capacitor structure described in item 31 of the scope of patent application, wherein the capacitor structure is formed by the manufacturing method of the capacitor structure described in item 1 of the aforementioned scope of patent application. 41. A capacitor structure including: a substrate; A plurality of insulation layers are formed on the substrate, and each insulation layer has a conductor layer. Here, the conductor layers are divided into a first group of conductor layers (A) and a second group of conductors in an ABABAB ... arrangement pattern. Layer (B), wherein the uppermost layer of the first group of conductor layers is located above the uppermost layer of the second group of conductor layers; a first dielectric layer is formed on the insulating layer and covers the first group of conductor layers The uppermost layer; a first capacitor structure formed on part of the first dielectric layer, the first capacitor structure is composed of an upper electrode plate, a second dielectric layer and a lower electrode plate; an inner metal dielectric An electrical layer (IMD) forming the first capacitor structure; 0503-9696TWl (Nl); TSMC2002.1305; JACKY.ptc Page 26 1231565 A first metal layer and a second metal layer are connected to the upper electrode plate and a plurality of second interposed first conductive layers in the inner metal dielectric layer. The second metal layer is electrically connected to the layer through a first bracket = and a plurality of fourth plugs; a first capacitor structure, and the second and second sets of conductor layers and the insulating layer system. A plurality of third capacitor structures; wherein the first metal layer and the second metal layer are respectively electrically connected to power sources of different polarities. 4 2 · The capacitor structure according to item 41 of the scope of patent application, wherein the insulating layer is an oxide layer having a low dielectric constant. 43. The capacitor structure according to item 41 of the scope of patent application, wherein the conductor layer is a copper layer, an aluminum layer, or an aluminum-copper alloy layer. 44. The capacitor structure according to item 41 of the scope of patent application, wherein the first dielectric layer is a barrier layer containing no oxygen. ^ 45. The capacitor structure as described in item 44 of the scope of the patent application, wherein the resistance P flat layer is S i c, S i N or S i C N. & 46. The capacitor junction described in item 41 of the scope of the patent application ^-an etch barrier layer is formed on the capacitor structure of the first dielectric layer, wherein the 4 7 The electrical etching barrier layer is a SiO2 layer. Capacitive structure, where the 48 · I 0503-9696TWF1 (Nl); TSMC2002-1305; JACKY.ptc Page 27 1231565 VI —MM 92117373 Soap — —fe- Patent Application Scope The first and second metal layers are copper and aluminum anchor copper alloy layers. Λ 49. The capacitor structure according to item 41 of the scope of patent application, wherein the first, second, third and fourth plugs are copper, Shao or tungsten plugs. The capacitor structure according to the patent application scope No. 丨 Capacitor Structure i ^ a W is formed by the manufacturing method. Capacitor structure described in item 11 0503-9696TWF1 (N1); TSMC2002-1305; JACKY.pt c%