CN118175921A - Manufacturing method of trench capacitor and trench capacitor - Google Patents
Manufacturing method of trench capacitor and trench capacitor Download PDFInfo
- Publication number
- CN118175921A CN118175921A CN202211537015.2A CN202211537015A CN118175921A CN 118175921 A CN118175921 A CN 118175921A CN 202211537015 A CN202211537015 A CN 202211537015A CN 118175921 A CN118175921 A CN 118175921A
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive layer
- metal
- dielectric layer
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 67
- 239000002184 metal Substances 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 154
- 239000000463 material Substances 0.000 claims description 14
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 3
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 230000009977 dual effect Effects 0.000 claims description 2
- 238000000227 grinding Methods 0.000 claims description 2
- 238000003384 imaging method Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 19
- 238000000206 photolithography Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a manufacturing method of a trench capacitor and the trench capacitor, wherein the method comprises the following steps: providing a semiconductor substrate, and forming a metal interconnection layer in the semiconductor substrate; depositing a barrier layer and a first dielectric layer which are positioned on a semiconductor substrate; etching the first dielectric layer to form a groove array; patterning is carried out on the groove array, and a first conductive layer, a second dielectric layer and a second conductive layer are formed through deposition in sequence; patterning the second dielectric layer and the second conductive layer of the first conductive layer, and forming a side wall, wherein the side wall is used for preventing the first conductive layer and the second conductive layer from being short-circuited; etching the first dielectric layer to form a through hole so as to expose the first conductive layer; a metal film is deposited on the via hole, and then a metal interconnection line is formed by patterning to connect the first conductive layer with the metal interconnection layer through the metal interconnection line and the via hole. The method is used for increasing the surface area of the capacitor, reducing the process integration difficulty and improving the structural design freedom of the trench capacitor.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for manufacturing a trench capacitor and a trench capacitor.
Background
Capacitors are a conventional passive component that is widely used in integrated circuit design. In some special applications, it is desirable to use capacitors with very large capacitance per unit to improve product performance, such as storing signals, decoupling, etc. Conventional planar capacitors require a large area to achieve large capacitance, which can sacrifice design area. For this reason, trench capacitors are the best choice for large capacitances. Typically, trench capacitors have a metal-dielectric-metal sandwich (MIM) structure, with a lower electrode metal connected to a lower metal interconnect, and an upper electrode metal connected to a trench fill metal, which is then connected to the metal interconnect through a via. However, the trench capacitor with the structure is introduced between metals, the trench needs to be filled with metal, and the upper electrode is connected by adopting a through hole, so that the process integration difficulty is high, and the freedom of the structural design of the trench capacitor is limited.
Therefore, it is necessary to provide a new manufacturing scheme of the trench capacitor, which increases the surface area of the capacitor, reduces the difficulty of process integration, and improves the degree of freedom of structural design of the trench capacitor.
Disclosure of Invention
The invention aims to provide a manufacturing method of a trench capacitor and the trench capacitor, which are used for increasing the surface area of the capacitor, reducing the process integration difficulty and improving the structural design freedom of the trench capacitor.
To achieve the above object, a method for manufacturing a trench capacitor of the present invention includes: providing a semiconductor substrate, and forming a metal interconnection layer in the semiconductor substrate; depositing a barrier layer and a first dielectric layer which are positioned on the semiconductor substrate; etching the first dielectric layer to form a groove array; patterning the groove array, and depositing to form a first conductive layer; depositing a second dielectric layer on the first conductive layer; depositing a second conductive layer on the second dielectric layer; etching the first dielectric layer to form a through hole so as to expose the first conductive layer; and depositing metal on the through hole to form a metal film, and then imaging to form a metal interconnection line so as to connect the first conductive layer with the metal interconnection layer through the metal interconnection line and the through hole.
The storage capacitor provided by the invention has the beneficial effects that: the process of the trench capacitor is arranged before the formation of the metal interconnection line, namely before the aluminum pin (pad) process, and the upper electrode is led out and the aluminum wiring are processed at the same time, so that no additional process step is required; in addition, the capacitor groove does not need to be filled with metal materials, and a cavity is allowed to exist, so that the design size of the groove type capacitor is reduced, the capacitance value of a unit area is increased, the surface area of the capacitor is increased, the process integration difficulty is reduced, and the structural design freedom of the groove type capacitor is improved.
In one possible embodiment, the depositing metal forms a metal film, and the patterning forms a metal interconnect line, including: depositing metal to form a metal film, wherein the metal film covers the through hole and the second conductive layer; and forming a metal interconnection line by adopting a photoetching and etching process.
In another possible implementation manner, the first conductive layer, the second conductive layer and the second dielectric layer are deposited by any one of physical vapor deposition, chemical vapor deposition or atomic layer deposition.
In other possible embodiments, the material of the second dielectric layer is at least one material with a high dielectric constant of SiN and HfO 2、ZrO2、Al2O3、La2O3.
In one possible embodiment, the second dielectric layer is a single layer film or a multilayer film.
In one possible embodiment, the materials of the first conductive layer, the second conductive layer, and the third conductive layer are all copper, aluminum, or tungsten.
In one possible embodiment, the forming a metal interconnection layer in the semiconductor substrate includes: forming a Damascus groove or a dual damascene hole groove in the semiconductor substrate by adopting a photoetching process; depositing a metal interconnect material; and forming a metal interconnection layer through a grinding process.
Drawings
FIG. 1 is a schematic cross-sectional view of a trench capacitor according to the present invention;
FIG. 2 is a flow chart of a method for fabricating a trench capacitor according to the present invention;
fig. 3A to 3J are schematic views of a cross section of a stepwise intermediate structure at each process preparation stage according to the present invention.
The icon illustrates:
a semiconductor substrate 100; a metal interconnect layer 200; a barrier layer 300; a first dielectric layer 400;
a trench array 500; a second dielectric layer 700; a second conductive layer 800; a sidewall 900; a through hole 1000;
A metal thin film 1100; metal interconnect line 1200.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
Fig. 1 shows a cross-sectional structure diagram of a trench capacitor according to the present invention, including: the semiconductor substrate 100, the metal interconnection layer 200 located in the semiconductor substrate, the barrier layer 300 and the first dielectric layer 400 located on the semiconductor substrate in sequence, the first dielectric layer 400 are formed with a groove array 500, the groove array 500 is formed with a first conductive layer 600, a second dielectric layer 700 and a second conductive layer 800, wherein the first conductive layer 600, the second dielectric layer 700 and the second conductive layer 800 form a U-shaped folding zone with a cavity in the groove; the sidewall 900, the second dielectric layer 700 has a via 1000 formed therein, the semiconductor substrate has a metal interconnect 1200 formed thereon, and the first conductive layer 600 is electrically connected to the second conductive layer 800 through the metal interconnect 1200 and the via 1000.
The process of forming the trench capacitor is described below in conjunction with the process of manufacturing the trench capacitor, fig. 2 is a schematic flow diagram of a method of manufacturing the trench capacitor, and fig. 3A to 3J are schematic sectional views of the intermediate structures in stages of the manufacturing process in this example.
Referring to fig. 2, the method for manufacturing a trench capacitor according to an embodiment of the present invention includes the following steps:
S201, providing a semiconductor substrate 100, and forming a metal interconnection layer 200 in the semiconductor substrate 100.
Illustratively, as shown in fig. 3A, the semiconductor substrate 100 may be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium, and the semiconductor substrate 100 may be a silicon semiconductor substrate on an insulator or a germanium semiconductor substrate on an insulator. And forming a copper interconnection layer on the silicon substrate by adopting a Damascus process.
S202, forming a barrier layer 300 and a first dielectric layer 400 on the semiconductor substrate 100.
Illustratively, as shown in fig. 3B, a barrier layer 300 is deposited on the surface of the metal interconnect layer 200, followed by a first dielectric layer 400. Illustratively, the dielectric barrier layer may be SiN or SiCN, and the dielectric layer may be SiO 2 or SiON.
And S203, etching the first dielectric layer 400 to form a groove array 500.
As shown in fig. 3C, a trench is formed on the first dielectric layer 400 by performing a photolithography and etching process on the trench, so as to obtain a trench array 500.
And S204, patterning the groove array to form a first conductive layer 600.
As shown in fig. 3D, photolithography and etching processes are sequentially performed, so as to define a pattern region of the first conductive layer 600, and the first conductive layer 600 is formed by deposition. Illustratively, the first conductive layer 600 may serve as a lower electrode of the capacitor, and the material of the first conductive layer may be Ti, tiN, ta or TaN. Alternatively, the first conductive layer may be a single-layer film or a multi-layer film, and the deposition manner may be physical vapor deposition, chemical vapor deposition or atomic layer deposition.
S205, forming a second dielectric layer 700 on the first conductive layer 600.
Illustratively, as shown in fig. 3E, photolithography and etching processes are sequentially performed on the first conductive layer 600, so as to define a pattern region of the second dielectric layer 700, and the second dielectric layer 700 on the first conductive layer 600 is deposited. The patterned area of the dielectric layer surrounds the patterned area of the first conductive layer 600, which ensures that the first conductive layer 600 is completely covered by the second dielectric layer 700 and thus does not short with the first conductive layer 600. The dielectric layer may be a material with a relatively high dielectric constant, such as SiN, hfO 2、ZrO2、Al2O3、La2O3, etc., and the dielectric layer may be a single-layer film or a multi-layer film, and the deposition manner may be chemical vapor deposition or atomic layer deposition.
S206, forming a second conductive layer 800 on the second dielectric layer 700.
Illustratively, as shown in fig. 3F, photolithography and etching processes of the second conductive layer 800 are sequentially performed, so as to define a pattern region of the second conductive layer 800, and form the second conductive layer 105 on the second dielectric layer 104. For example, the second conductive layer 800 may serve as an upper electrode of the capacitor, the material of the second conductive layer 800 may be Ti, tiN, ta or TaN, and the second conductive layer 800 may be a single-layer film or a multi-layer film, wherein the second conductive layer 800 uniformly covers the second dielectric layer 700 so as not to be shorted with the lower electrode. Alternatively, the second conductive layer 800 may be deposited by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
S207, patterning the first conductive layer 600, the second dielectric layer 700, and the second conductive layer 800.
That is, photolithography and etching processes of the first conductive layer 600, the second dielectric layer 700 and the second conductive layer 800 are sequentially performed, and pattern areas of the first conductive layer 600, the second dielectric layer 700 and the second conductive layer 800 are defined, as shown in fig. 3G.
S208, forming a side wall 900 to prevent the first conductive layer 600 and the second conductive layer 800 from being shorted.
That is, a sidewall 900 is formed at the end of the patterned capacitor multilayer film, as shown in fig. 3H. The material of the side wall 900 may be an insulating medium such as SiO 2, siN, siON, siCN, etc. The side wall can be a single-layer film or a multi-layer film, and the deposition mode can be chemical vapor deposition or atomic layer deposition. Optionally, a protective layer is deposited first, after the protective layer uniformly covers the surface of the semiconductor substrate, the protective layer is etched in a plane to form a sidewall, and the protective layers in other areas are etched away and stopped on the surface of the first conductive layer 600.
S209, etching the first dielectric layer to form a through hole so as to expose the first conductive layer.
As shown in fig. 3I, a via pattern is illustratively defined on the first dielectric layer 400 using a photolithography, etching process, to form a via 1000.
S210, a metal is deposited on the via hole 1000 to form a metal thin film 1100, and then a metal interconnection line 1200 is formed by patterning to connect the first conductive layer 600 with the second conductive layer 800 through the metal interconnection line and the via hole.
For example, as shown in fig. 3J, the metal film may be formed by a standard aluminum wire process, i.e., depositing a plurality of metal films, which are TaN, tiN, ti, al, ti, tiN in order from bottom to top, to form an aluminum film. As shown in fig. 3J, metal interconnect lines, such as aluminum interconnect lines, are formed by photolithography and etching processes, and the upper electrode is connected to the underlying copper interconnect layer through the aluminum interconnect lines and the via holes, and at the same time, aluminum pads (pads) of the peripheral circuits are defined. In this embodiment, the upper electrode of the capacitor is connected to the lower copper interconnect layer while the metal interconnect is completed. Therefore, the metal film uniformly covers the surface of the silicon wafer and fills the through holes to be interconnected with the lower copper interconnection layer; however, the trench of the capacitor is not completely filled, but the upper electrode of the surface of the capacitor is covered, so that a void is formed in the trench of the capacitor.
In a possible embodiment, the material of the first conductive layer 600 and the second conductive layer 800 may be copper, aluminum or tungsten.
It should be noted that, after the second conductive layer 800 is formed and before the first dielectric layer 400 is etched to form the through hole 1000, a greater number of dielectric layers and conductive layers may be deposited in the semiconductor structure, which is not shown in this embodiment.
In this embodiment, the process of the trench capacitor is placed before the formation of the metal interconnection line, that is, before the aluminum pin (pad) process, and the upper electrode is led out and the aluminum wiring is processed at the same time, so that no additional process step is required; in addition, the capacitor grooves do not need to be filled with metal materials, and holes are allowed to exist, so that the design size of the grooves of the groove type capacitor is reduced, and the capacitance value of unit area is increased.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (8)
1.A method of manufacturing a trench capacitor, comprising:
Providing a semiconductor substrate, and forming a metal interconnection layer in the semiconductor substrate;
Depositing a barrier layer and a first dielectric layer which are positioned on the semiconductor substrate;
Etching the first dielectric layer to form a groove array;
Patterning is carried out on the groove array, and a first conductive layer, a second dielectric layer and a second conductive layer are formed through deposition in sequence;
Patterning the first conductive layer, the second dielectric layer and the second conductive layer, and forming a side wall, wherein the side wall is used for preventing the first conductive layer and the second conductive layer from being shorted;
etching the first dielectric layer to form a through hole so as to expose the first conductive layer;
And depositing metal on the through hole to form a metal film, and then imaging to form a metal interconnection line so as to connect the first conductive layer with the metal interconnection layer through the metal interconnection line and the through hole.
2. The method of claim 1, wherein depositing metal to form a metal film and patterning metal interconnect lines comprises:
Depositing metal to form a metal film, wherein the metal film covers the through hole and the second conductive layer;
And forming a metal interconnection line by adopting a photoetching and etching process.
3. The method of claim 1, wherein the first conductive layer, the second conductive layer, and the second dielectric layer are deposited by any one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
4. The method of claim 1, wherein the material of the second dielectric layer is at least one of SiN, hfO 2、ZrO2、Al2O3、La2O3, and a high dielectric constant material.
5. The method of claim 4, wherein the second dielectric layer is a single layer film or a multilayer film.
6. The method of claim 3, wherein the materials of the first, second and third conductive layers are all copper, aluminum or tungsten.
7. The method of claim 1, wherein forming a metal interconnect layer in the semiconductor substrate comprises:
forming a Damascus groove or a dual damascene hole groove in the semiconductor substrate by adopting a photoetching process;
Depositing a metal interconnect material; and forming a metal interconnection layer through a grinding process.
8. A trench capacitor, comprising:
a semiconductor substrate;
a metal interconnect layer in the semiconductor substrate;
The barrier layer and the first dielectric layer are sequentially arranged on the semiconductor substrate; the first dielectric layer is provided with a groove array, the groove array is provided with a first conductive layer, a second dielectric layer and a second conductive layer, the end part of the groove array is provided with a side wall for isolating the first conductive layer and the second conductive layer, and the first conductive layer, the second dielectric layer and the second conductive layer form a U-shaped folding area with a cavity in the groove; and a through hole is formed in the second dielectric layer, a metal interconnection line is formed on the semiconductor substrate, and the first conductive layer is electrically connected with the second conductive layer through the metal interconnection line and the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211537015.2A CN118175921A (en) | 2022-12-02 | 2022-12-02 | Manufacturing method of trench capacitor and trench capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211537015.2A CN118175921A (en) | 2022-12-02 | 2022-12-02 | Manufacturing method of trench capacitor and trench capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118175921A true CN118175921A (en) | 2024-06-11 |
Family
ID=91353633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211537015.2A Pending CN118175921A (en) | 2022-12-02 | 2022-12-02 | Manufacturing method of trench capacitor and trench capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118175921A (en) |
-
2022
- 2022-12-02 CN CN202211537015.2A patent/CN118175921A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9269762B2 (en) | Metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers | |
| US7432151B2 (en) | Semiconductor device and method for fabricating the same | |
| JP4636598B2 (en) | Structure and manufacturing method of MIM capacitor in dual damascene structure | |
| KR100796499B1 (en) | A semiconductor device with capacitor and method for fabricating the same | |
| US9831171B2 (en) | Capacitors with barrier dielectric layers, and methods of formation thereof | |
| US20100164062A1 (en) | Method of manufacturing through-silicon-via and through-silicon-via structure | |
| US12046550B2 (en) | Three dimensional MIM capacitor having a comb structure and methods of making the same | |
| US6492226B1 (en) | Method for forming a metal capacitor in a damascene process | |
| US20210020737A1 (en) | Capacitor and method for producing the same | |
| CN113451511A (en) | Semiconductor device with a plurality of semiconductor chips | |
| US7452804B2 (en) | Single damascene with disposable stencil and method therefore | |
| JP2003282728A (en) | Semiconductor element and its manufacturing method | |
| KR20050071149A (en) | Method of manufacturing semiconductor device with mim capacitor | |
| US6284619B1 (en) | Integration scheme for multilevel metallization structures | |
| US6794702B2 (en) | Semiconductor device and fabrication method thereof | |
| CN118175921A (en) | Manufacturing method of trench capacitor and trench capacitor | |
| CN112259522B (en) | Rear-end structure comprising MIM capacitor and manufacturing method thereof | |
| US10910304B2 (en) | Tight pitch wirings and capacitor(s) | |
| US20200286777A1 (en) | Interconnect structure and method for preparing the same | |
| CN118284326A (en) | Manufacturing method of trench capacitor and trench capacitor | |
| CN115763423A (en) | Manufacturing method of trench capacitor and trench capacitor | |
| US20210384073A1 (en) | Semiconductor device and method for manufacturing the same | |
| US20070145599A1 (en) | Metal-insulator-metal (MIM) capacitor and methods of manufacturing the same | |
| CN112259523B (en) | Forming method of MIM capacitor and back-end structure | |
| US20060089001A1 (en) | Localized use of high-K dielectric for high performance capacitor structures |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication |