TWI229429B - Semiconductor chip package and method for manufacturing the same - Google Patents

Semiconductor chip package and method for manufacturing the same Download PDF

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Publication number
TWI229429B
TWI229429B TW092128865A TW92128865A TWI229429B TW I229429 B TWI229429 B TW I229429B TW 092128865 A TW092128865 A TW 092128865A TW 92128865 A TW92128865 A TW 92128865A TW I229429 B TWI229429 B TW I229429B
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substrate
semiconductor wafer
package structure
patent application
scope
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TW092128865A
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Chinese (zh)
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TW200515554A (en
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Ya-Ling Huang
Tzu-Bin Lin
Hung-Ta Hsu
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Advanced Semiconductor Eng
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Publication of TW200515554A publication Critical patent/TW200515554A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7815—Means for applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

A semiconductor chip package includes a substrate, a semiconductor chip mounted on the substrate, a plurality of bonding wires electrically connecting the semiconductor chip to the substrate and a protection member mounted on the substrate such that the semiconductor chip and the bonding wires are disposed between the protection member and the substrate. Each bonding wire of the semiconductor chip package according to the present invention is covered with an insulating film on the entire surface thereof thereby preventing occurrence of short circuit between the bonding wires within the protection member. The present invention further provides a method for manufacturing the semiconductor chip package.

Description

1229429 五、發明說明（1) 【發明所屬之技術領域】 本t明係有關於一種半導體晶片 法。 τ装構造及其製造方 【先前技術】 積肢電路（或稱半導艚晶片）♦ 高效能之封裝積體電展更 直挣扎於追趕接腳數（pin count)的 =者一 側面接著限制（Drof n r 尺寸限制、低 耕於扭往 mou ng constraint)以及复他 子；2裝以及接者積體電路逐漸發展出的要求。參明 圖所不’目前常用的-種半導體晶片封裝構造，；為、 陣列封裝構造10。，纟包含至少一半導體晶片102設於t 板104上並且以打線連接的方式電性連接於該基板、二 數個陣列排列之錫球銲墊106形成於該基板1〇4上用以與錫 球+108接合以及一封膠體11〇包覆該晶片1〇2以及連接線 (藉由打線連接形成）。該封裝構造丨00可藉由複數個陣列 排列之錫球1 0 8連接於一印刷電路板（未示於圖中）上。該 錫球1 0 8係形成於該封裝構造丨〇 〇或該印刷電路板的錫球鋅 塾上，並且經加熱融化（回銲）該錫球108使得該封裝構 造1 0 0銲接於該印刷電路板。 所有利用錫球將半導體晶片導電性地接合於一個主要印 刷電路板的半導體晶片封裝構造，都容易受到因溫度變動 以及組成該半導體晶片封裝構造之元件（例如晶片、封膠 體以及基板）熱膨脹係數不一致造成的損害（特別是疲勞 損害）之影響。更具體地說，當半導體晶片封裝構造從錫1229429 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor wafer method. τ package structure and its manufacture [prior art] integrated circuit (or semi-conducting chip) ♦ high-performance package integrated circuit more struggling to catch up with the pin count = one side and then limit (Drof nr size limitation, low-plowing and twisting to mou ng constraint) and multiples; requirements for 2 packs and receiver integrated circuit gradually developed. Refer to the figure for reference, a type of semiconductor wafer packaging structure commonly used at the present time; Including, at least one semiconductor wafer 102 is provided on the t-board 104 and is electrically connected to the substrate by wire bonding. Two solder ball pads 106 arranged in an array are formed on the substrate 104 for soldering. The ball +108 joint and a piece of colloid 11 cover the chip 102 and the connection line (formed by wire connection). The package structure 00 can be connected to a printed circuit board (not shown) through a plurality of solder balls 108 arranged in an array. The solder ball 108 is formed on the package structure or the solder ball zinc tin of the printed circuit board, and the solder ball 108 is melted (re-soldered) by heating so that the package structure is soldered to the print. Circuit board. All semiconductor wafer package structures that use solder balls to conductively bond a semiconductor wafer to a main printed circuit board are susceptible to inconsistent thermal expansion coefficients due to temperature fluctuations and components (such as wafers, sealants, and substrates) that make up the semiconductor wafer package structure. The effects of damage (especially fatigue damage). More specifically, when a semiconductor wafer package is constructed from tin

1229429 五、發明說明（2) 球回銲的溫 換，該封裝 之速度膨脹 構造受到壓 此外，在 使得該封裝 熱膨脹以及 循環性或是 力，若沒有 構造產生疲 【發明内容 本發明之 能有效地降 度冷卻或是在使用過程中與室溫進 、 構造的封膠體、晶片以及基板等：二“ 或是收縮因此壓迫或是拉扯該封二曰以不同 迫或拉扯的情況會造成高應力集；構&。封裝 # 11:ί T通過半導體晶片封裝構造時，會 收縮（雖然遠少於回鲜）：這； 週期性的加熱和冷卻所造成的壓迫和 適當方式消除，可能會使得該半導體； 勞損害。 主要目的係提供一種半導體晶片封裝構造，其 低設於該半導體晶片封裝構造因為熱膨脹係數 不一致而產生之應力。 本發明之次要目的係提供一種散熱效率高之半導體晶片 封裝構造’使该半導體曰曰片所產生之熱可輕易分散至外界 環境中，藉此減少該封裝構造之疲勞損害。 根據本發明之半導體晶片封裝構造，其主要包含一基 板、一半導體晶片固接於該基板上、複數個連接線 土 (bonding wires)將該晶片電性連接於該基板以及一保護 件固接於該基板上’使得該半導體晶片以及該連接線係設 於該保護件以及該基板之間。本發明之特徵在於以一保護 件以及一絕緣薄膜取代習用技術中的封膠體，藉此有效地 降低設於該半導體晶片封裝構造因為熱膨脹係數不一致而1229429 V. Description of the invention (2) The temperature change of the ball reflow soldering, the speed expansion structure of the package is under pressure. In addition, the package is subject to thermal expansion and cyclicity or force. If there is no structure, fatigue will occur. [SUMMARY OF THE INVENTION The present invention is effective Ground cooling or sealing and colloids, wafers, and substrates that enter and are constructed at room temperature during use: Two "or shrinking and therefore compressing or pulling the seal. Using different pressure or pulling will cause high stress.构 &. 包装 # 11: ί When shrinking through a semiconductor wafer package, it shrinks (although far less than freshness): this; the periodic heating and cooling of the pressure and the elimination of the appropriate means may cause The semiconductor; labor damage. The main purpose is to provide a semiconductor chip package structure which is low in stress caused by the inconsistent thermal expansion coefficient of the semiconductor chip package structure. A secondary object of the present invention is to provide a semiconductor chip package with high heat dissipation efficiency The structure allows the heat generated by the semiconductor chip to be easily dissipated to the external environment, thereby reducing the Fatigue damage to the mounting structure. The semiconductor wafer package structure according to the present invention mainly includes a substrate, a semiconductor wafer fixed on the substrate, a plurality of bonding wires electrically connecting the wafer to the substrate, and A protective member is fixed on the substrate, so that the semiconductor wafer and the connecting wire are provided between the protective member and the substrate. The invention is characterized in that a protective member and an insulating film are used to replace the sealing compound in the conventional technology. , Thereby effectively reducing the package structure provided on the semiconductor chip due to inconsistent thermal expansion coefficients.

1229429 五、發明說明（3) "一''— ----- f生之應力。λ外，本發明之半導體晶片封裝構造的每一 ，，線的整個表面所覆蓋之絕緣薄膜係使得該保護件中的 V線不致因彼此接觸而發生短路。1229429 V. Description of the invention (3) " 一 ''------ f stress. In addition to λ, each of the semiconductor chip package structures of the present invention is covered with an insulating film over the entire surface of the wire so that the V wires in the protective member are not short-circuited due to contact with each other.

本發明另提供一種製造該半導體晶片封裝構造的方法。 先將該半導體晶片固接於該基板上之後，進行一打線製程 以形成該連接線。根據本發明一實施例，在此打線步驟中 可形成複數個包覆有絕緣薄膜之連接線，其包含以下步 驟·將一絕緣導線（在一金屬線之外表面包覆一絕緣薄膜） 穿過一打線接合工具並加熱之，使該絕緣導線外表絕緣薄 膜Αϊά點受熱破裂而露出該金屬線並燒結成球。然後，該打 線接合工具將該金屬球下壓至該半導體晶片上進行接合。 升起該打線接合工具並引導該絕緣導線至該基板上，以壓 印該絕緣導線使其金屬線露出而與該基板接合藉此形成該 包覆有絕緣薄膜之連接線，隨後截斷該導線。The invention also provides a method for manufacturing the semiconductor chip package structure. After the semiconductor wafer is fixed on the substrate, a wiring process is performed to form the connection line. According to an embodiment of the present invention, a plurality of connection wires covered with an insulating film may be formed in this wire bonding step, which includes the following steps: passing an insulated wire (a surface of a metal wire covered with an insulating film) through A dozen wire bonding tools were heated and the outer surface of the insulated wire insulation film Αϊά was thermally cracked to expose the metal wire and sintered into a ball. The wire bonding tool then presses the metal ball onto the semiconductor wafer for bonding. Raise the wire bonding tool and guide the insulated wire to the substrate to emboss the insulated wire so that its metal wires are exposed to join with the substrate to form the connection wire covered with an insulating film, and then cut the wire.

本發明亦提供另一打線步驟中以形成複數個包覆有絕緣 薄膜之連接線。首先，將一金屬線穿置於一打線接合工具 中’並在該打線接合工具之接合端點環設一注膠口。將該 金屬線燒結成球，使該打線接合工具將該金屬球下壓至該 半導體晶片上進行接合。然後，升起該打線接合工具，同 時進行注膠，使該注膠口流出之絕緣膠包覆該金屬線，並 將其引導至該基板。先停止注膠，再壓印該金屬線，使該 金屬線與該基板接合藉此形成該包覆有絕緣薄膜之連接 線’隨後截斷該金屬線。 此外，本發明亦提供一種方法，先利用習用的打線技術The present invention also provides another wiring step to form a plurality of connection wires covered with an insulating film. First, a metal wire is threaded into a wire bonding tool 'and a glue injection port is provided at a joint end point of the wire bonding tool. The metal wire is sintered into a ball, and the wire bonding tool presses the metal ball onto the semiconductor wafer for bonding. Then, the wire bonding tool is raised, and at the same time, the glue is injected, and the insulating glue flowing out of the glue injection port covers the metal wire and guides it to the substrate. Stop the glue injection first, and then emboss the metal wire so that the metal wire is bonded to the substrate to form the connection line covered with the insulating film 'and then cut off the metal wire. In addition, the present invention also provides a method that first uses conventional wire bonding technology

第8頁 1229429 五、發明說明（4) 形成不具絕緣薄膜之連接線，再以例如喷塗的方式將一 緣材料塗佈於該連接線表面。 、& /在孩晶片與基板之間形成複數個具有絕緣之連接線之 ^，再將該保護件利用黏著劑等材料固接於該基板上， 得該半導體晶片以及該連接線係設於該保護件以及該 之間。 攸 為了讓本發明之上述和其他目#、特徵、和優點能 顯特徵，下文特舉本發明較佳實施例，並配合所附圖示， 作詳細說明如下。 【實施方式】 第2 A圖係圖不根據本發明一實施例之半導體晶片封裝 造2 0 0，纟主要包含一基板2〇2、一半導體晶片2〇4、複數 條連接線2G6以及-保護件2Q8。該半導體晶片m係固接 於孩基板202之上表面。該些連接線2〇6係將該半導體晶片 2 04電性連接於該基板m。更具體地說，參見第3圖，該 半導體晶片2 04之上表面設有複數個晶片銲墊3〇2，該基板 20 2>之上表面設有複數個接墊3〇4，該連接線2〇6即是用以 將该晶片銲墊3 0 2連接於該接墊3 〇 4。 本發明之特徵在於以一保護件20 8以及一絕緣薄膜21 〇 (參見第2A圖）取代習用技術中的封膠體！ 1〇(見於第i圖）。 f白知技術中，3玄封膠體丨i 0係包覆該半導體晶片i 〇 2並 且填滿該些連接線112之間空隙。如此一來，該些連接線 112之間因有該封膠體11〇隔開因此彼此之間不會因接觸而 毛生短路此外，该封膠體11 〇亦保護該半導體晶片1 〇 2以 1229429 五、發明說明（5) 及該些連接線1 1 2以防止因外力施壓而使其變形或破裂， 或是避免水氣以及灰塵進入該半導體封裝構造。然而，由 第1圖可知該封膠體110係包覆該半導體晶片1〇2除了其下 表面之外的整個表面，並且該封膠體1丨〇與該半導體晶片 1 0 2以及該些連接線1 1 2形成一签個塊體固接於該基板1 〇 4 之上表面。因此，輕易可知地，該封膠體丨丨〇分別與該基 板1 0 4以及該半導體晶片1 〇 2有很大的接觸面積。當此種習 用的半導體晶片封裝構造100在回銲步驟中或是使用中受 熱時，該半導體晶片1 〇 2、封膠體1 1 〇與基板丨〇 4之間的熱 膨脹係數不同而且彼此的接觸面積又大，使得該半導體封 裝構造受到很大的應力作用而容易損壞。相對地，參照第 2A圖，本發明係使用一保護件2〇8固接於該基板2〇2上並且 覆蓋於該半導體晶片2 04以及該些連接線2〇6上，提供該該 半導體晶片2 04以及該些連接線2〇6機械性的保護，使得該 半導體晶片2 0 4以及該些連接線2 〇 6不致因外力施壓而變形 或是損壞。本發明所提供之半導體晶片封裝構造2〇〇其保 護件208與該基板20 2形成一空間用以容納該半導體晶片 2 04以及連接線2 0 6，並且該保護件2〇8不與該半導體晶片 204直接接觸，藉此有效減少半導體晶片封裝構造2〇(^所受 因熱膨脹係數不一致所導致的應力。 此外，由於該絕緣薄膜21〇係形成在每一連接線2〇6的整 個表面，因此該些連接線2〇6之間不會因彼此接觸而發生 短路。根據本發明一實施例，該絕緣薄膜2丨〇亦覆蓋^半 導體晶片2 04的晶片銲墊3 0 2以及該基板2〇2的接墊3〇4以防Page 8 1229429 V. Description of the invention (4) Form a connection line without an insulating film, and then apply an edge material to the surface of the connection line by, for example, spraying. 、 &Amp; / A plurality of connecting wires with insulation are formed between the child wafer and the substrate, and then the protection member is fixed to the substrate with an adhesive or the like to obtain the semiconductor wafer and the connecting wires. The protective piece as well as that. In order to make the above and other objects, features, and advantages of the present invention obvious, the following describes in detail the preferred embodiments of the present invention and the accompanying drawings. [Embodiment] FIG. 2A is a diagram of a semiconductor chip package 2000 that is not according to an embodiment of the present invention. It mainly includes a substrate 202, a semiconductor wafer 204, a plurality of connection lines 2G6, and -protection. Piece 2Q8. The semiconductor wafer m is fixed on the upper surface of the substrate 202. The connecting wires 206 electrically connect the semiconductor wafer 204 to the substrate m. More specifically, referring to FIG. 3, a plurality of wafer pads 30 are provided on the upper surface of the semiconductor wafer 204, and a plurality of pads 304 are provided on the upper surface of the substrate 20 2 and the connection line 206 is used to connect the wafer pad 302 to the pad 304. The present invention is characterized in that a protective member 20 8 and an insulating film 21 0 (see FIG. 2A) replace the sealing compound in the conventional technology! 10 (see figure i). In the white-known technique, 3 xenon colloids i 0 cover the semiconductor wafer i 02 and fill the gaps between the connection lines 112. In this way, the connection lines 112 are separated by the sealing compound 11 so that they will not be short-circuited due to contact with each other. In addition, the sealing compound 11 〇 also protects the semiconductor wafer 1 02 to 1229429 5 2. Description of the invention (5) and the connecting wires 1 12 to prevent deformation or cracking due to external force or to prevent moisture and dust from entering the semiconductor package structure. However, it can be seen from FIG. 1 that the sealing compound 110 covers the entire surface of the semiconductor wafer 102 except the lower surface thereof, and the sealing compound 1 and the semiconductor wafer 102 and the connection lines 1 12 forms a block to be fixed on the upper surface of the substrate 104. Therefore, it can be easily known that the sealing compound has a large contact area with the substrate 104 and the semiconductor wafer 102, respectively. When such a conventional semiconductor wafer package structure 100 is heated during a reflow step or during use, the thermal expansion coefficients of the semiconductor wafer 102, the sealing compound 1 10, and the substrate 4 are different and the contact areas are mutually It is also large, so that the semiconductor package structure is easily damaged due to a large stress. In contrast, referring to FIG. 2A, the present invention uses a protective member 208 to be fixed on the substrate 200 and covers the semiconductor wafer 204 and the connecting wires 206 to provide the semiconductor wafer. The mechanical protection of 2004 and the connecting wires 206 prevents the semiconductor wafer 204 and the connecting wires 206 from being deformed or damaged due to external pressure. In the semiconductor wafer package structure 2000 provided by the present invention, the protective member 208 and the substrate 202 form a space for accommodating the semiconductor wafer 204 and the connecting wire 206, and the protective member 208 is not connected with the semiconductor The wafer 204 is in direct contact, thereby effectively reducing the stress caused by the inconsistent thermal expansion coefficient of the semiconductor wafer package structure. In addition, since the insulating film 21 is formed on the entire surface of each connection line 206, Therefore, the connection wires 206 will not be short-circuited due to contact with each other. According to an embodiment of the present invention, the insulating film 2 also covers the wafer pads 3 2 of the semiconductor wafer 2 04 and the substrate 2 〇2 the pads 304 in case

1229429 五、發明說明（6) 止該晶片銲墊3 〇2以及該接墊3 04氧化，或是避免水氣或灰 塵等污染物污染該半導體晶片封裝構造2〇〇而影響其功 月b。根據本發明另一實施例，該絕緣薄膜2 1 〇亦覆蓋該半 導體晶片2 0 4以及該基板2 0 2的整個上表面。該絕緣薄膜 2 1 0可由例如二氧化矽或是環氧樹脂等具有低介電係數的 材料形成。 在本發明中，該保護件20 8係由金屬等具有高機械性強 度之材料製成。當該保護件2 0 8係由金屬或其他導電材料 製成時，可提供屏蔽功效以降低電磁波的干擾。該保護件 208可與該基板20 2形成一密閉空間使得水氣或灰塵等污染 物無法進入該密閉空間。然而，當該晶片銲墊3〇2以及該 接墊304或是該半導體晶片2 04以及該基板202的整個上表 面覆蓋有該絕緣薄膜2 1 0時，儘管污染物進入該保護件2 〇 8 與該基板2 0 2之間也不會影響該半導體封裝構造之功能。 因此如第1 7圖所示，本發明亦提供一種僅具有複數個突出 點1 702與該基板2 0 2連接而非與該基板2 〇2完全密合之保護 件 1 70 0 〇 較佳地，該保護件2 〇 8係為一散熱件，藉此提高該半導 體晶片封裝構造2 0 〇的散熱效率。此外，該半導體晶片2 〇 4 與該保護件2 0 8之間一般需要保留一個空間容納該連接線 2 0 6的彎曲部分。因此，該半導體晶片封裝構造2 〇 〇較佳地 包含一熱導介面物質（thermal interface material， T I Μ ) 2 1 2設於該半導體晶片2 〇 4與該保護件2 0 8之間，使得 該半導體晶片2 0 4在操作中產生的熱順利經由該熱導介面1229429 V. Description of the invention (6) Stop the wafer pad 3 02 and the pad 3 04 from oxidizing, or avoid contamination of the semiconductor wafer package structure 200 with water vapor or dust, etc., and affect its function b. According to another embodiment of the present invention, the insulating film 21 also covers the entire upper surface of the semiconductor wafer 204 and the substrate 202. The insulating film 210 may be formed of a material having a low dielectric constant such as silicon dioxide or epoxy resin. In the present invention, the protective member 20 8 is made of a material having a high mechanical strength such as metal. When the protective member 208 is made of metal or other conductive materials, it can provide shielding effect to reduce electromagnetic wave interference. The protection member 208 can form a closed space with the substrate 202 so that pollutants such as water vapor or dust cannot enter the closed space. However, when the wafer pad 300 and the pad 304 or the semiconductor wafer 204 and the entire upper surface of the substrate 202 are covered with the insulating film 210, the contaminants enter the protective member 208. It does not affect the function of the semiconductor package structure with the substrate 202. Therefore, as shown in FIG. 17, the present invention also provides a protective member 1 70 0 〇 having only a plurality of protruding points 1 702 connected to the substrate 2 0 instead of being completely in close contact with the substrate 2 0 2. The protective member 2008 is a heat sink, thereby improving the heat dissipation efficiency of the semiconductor chip package structure 200. In addition, a space is generally reserved between the semiconductor wafer 204 and the protective member 208 to accommodate the bent portion of the connecting wire 206. Therefore, the semiconductor wafer package structure 2000 preferably includes a thermal interface material (TIM) 2 1 2 provided between the semiconductor wafer 2 04 and the protective member 2 08, so that the The heat generated during the operation of the semiconductor wafer 2 0 4 passes through the thermal conduction interface smoothly.

第11頁 1229429 五、發明說明（7) " " ' " -------- 物質2 1 2傳導至該保護件2 〇 8而散出。 第2B圖係®示根據本發明另_實施例之半導體晶片 構造25 0。除了該半導體晶片封裝構造25〇包含一具有凹^ 2 5 2 a之散熱件2 5 2用以取代該保護件2 〇 8之外，該封裝構 25◦大致係與第2A圖所示之封裝構造2〇〇相同。由於該散熱 片2 52之凹部252a可接觸到晶片2〇4表面沒有設置銲墊之區 域，因此可有效增進封裝構造2 5〇之散熱效能。 本發明另提供數種製造前述半導體晶片封裝構造2〇〇的 方法。首先，將該半導體晶片2 〇 4固接於該基板2 〇 2上之 後，形成該包覆有絕緣薄膜之連接線。 第3 - 7圖係圖示根據本發明一實施例的包覆有絕緣薄暝 之連接線製造方法。首先，提供一絕緣導線3 〇 6，其係由 一金属線3 0 6a及包覆在外表面之絕緣薄膜3〇6b所組成，較 佳地’該金屬線30 6a係為金線，該絕緣薄膜3 0 6b係為環氧 樹脂等絕緣材質；將此絕緣導線3 〇 6穿設置於一打線接合 工具308中並加熱之，請參閱第3圖所示，使絕緣導線3〇6 外表絕緣薄膜3 0 6b端點受熱破裂而露出金屬線3 0 6a，再利 用電子點火或氫焰的方式將露出之金屬線3 0 6a末端燒結成 一金屬球310 ;前述之打線接合工具3〇8係沿用一般打線機 之毛細管狀鋼嘴。 然後如第4圖所示，打線接合工具3〇8將該金屬球310下 壓至3亥晶片204表面之晶片銲塾302上，利用超音波震動或 熱壓接合等方式進行球形接合（bal 1 bond )，使金屬球 310與晶片銲墊302形成緊密接合。完成晶片銲墊302之接Page 11 1229429 V. Description of the invention (7) " " '" -------- The substance 2 1 2 is transmitted to the protective member 2 08 and is emitted. Fig. 2B shows a semiconductor wafer structure 250 according to another embodiment of the present invention. Except that the semiconductor chip package structure 25 includes a heat sink 2 5 2 having a recess ^ 2 5 2 a to replace the protection member 2 08, the package structure 25 is roughly the same as the package shown in FIG. 2A Structure 200 is the same. Since the recessed portion 252a of the heat sink 2 52 can contact the area where the pads are not provided on the surface of the wafer 204, the heat dissipation performance of the package structure 250 can be effectively improved. The present invention also provides several methods for manufacturing the aforementioned semiconductor wafer package structure 200. First, after the semiconductor wafer 204 is fixed on the substrate 200, the connection line covered with an insulating film is formed. 3-7 are diagrams illustrating a method for manufacturing a connection wire covered with an insulation sheet according to an embodiment of the present invention. First, an insulated wire 3 06 is provided, which is composed of a metal wire 3 06a and an insulating film 3006b covering the outer surface. Preferably, the metal wire 30 6a is a gold wire and the insulating film 3 0 6b is an insulating material such as epoxy resin; this insulated wire 3 〇6 is placed in a dozen wire bonding tool 308 and heated, please refer to FIG. 3 to make the insulated wire 3 〇6 insulation film 3 The end of 0 6b is exposed to heat and the metal wire 3 0 6a is exposed, and then the end of the exposed metal wire 3 6 a is sintered into a metal ball 310 by means of electronic ignition or hydrogen flame; the aforementioned wire bonding tool 3 08 is generally used. Capillary steel nozzle for wire drawing machine. Then, as shown in FIG. 4, the wire bonding tool 3008 presses the metal ball 310 onto the wafer bonding pad 302 on the surface of the wafer 30, and performs ball bonding using ultrasonic vibration or thermocompression bonding (bal 1 bond) to form a tight bond between the metal ball 310 and the wafer pad 302. Complete the connection of wafer pad 302

1229429 五、發明說明（8) 合後’請接續參閱第5圖所示，將打線接合工具3〇8升起， 以拉伸該絕緣導線3 0 6並同時引導絕緣導線3 〇 6至該基板 202表面之接墊304上，以壓印該絕緣導線3〇6使其中之金 屬線306a露出而與接墊304形成緊密接合，藉此形成該包 覆有絕緣薄膜2 1 0之連接線2 0 6 ;然後再如第6圖所示將絕 緣導線3 0 6加以截斷。1229429 V. Description of the invention (8) After closing, please refer to Figure 5 below. Raise the wire bonding tool 308 to stretch the insulated wire 3 06 and guide the insulated wire 3 06 to the substrate at the same time. On the pad 304 on the surface of 202, the insulated wire 306 is embossed to expose the metal wire 306a therein to form a tight joint with the pad 304, thereby forming the connecting wire 2 0 covered with the insulating film 2 1 0 6; Then cut the insulated wire 3 06 as shown in FIG. 6.

不斷重複上述之各步驟，直至晶片2 〇 4上之每一晶片銲 墊3 0 2與該基板2 0 2上之每一接墊2 6之間皆形成有具有絕緣 薄膜2 1 0之連接線2 0 6為止，至此，即可完成整個打線製 程。 最後如第了圖所示可以例如噴塗的方式將一絕緣材料塗 佈於該半導體晶片2 0 4的晶片銲墊3 〇 2以及該基板2 〇 2的接 墊304上或是該半導體晶片204以及該基板202的整個上表 面。 本發明除了使用絕緣導線進行打線接合來形成包覆有絕 緣薄膜之連接線之外，亦可直接使用金屬線配合注膠作業 來完成包覆有絕緣薄膜之連接線，.請參考第8圖至第1 3圖 所述之另一實施例。The above steps are repeated continuously until a connection line with an insulating film 2 1 0 is formed between each of the wafer pads 3 2 on the wafer 2 04 and each of the pads 2 6 on the substrate 2 02 Up to 2006, the entire wire bonding process can be completed. Finally, as shown in the figure, an insulating material may be applied, for example, by spray coating on the wafer pads 300 of the semiconductor wafer 204 and the pads 304 of the substrate 200 or the semiconductor wafer 204 and The entire upper surface of the substrate 202. In addition to using insulated wires for wire bonding to form connection wires covered with an insulating film, the present invention can also directly use metal wires in conjunction with glue injection to complete connection wires covered with an insulating film. Please refer to Figures 8 to FIG. 13 shows another embodiment.

首先如第8圖所示，將一金屬線802穿置於一打線接合工 具8 0 4中，在此打線接合工具8 0 4内層設有一用以提供絕緣 膠80 6之注膠管808，且注膠管80 8之注膠口 80 8a係環設於 打線接合工具804之接合端點處；並利用電子點火或氫焰 的方式將金屬線8 0 2末端燒結成一金屬球8 1 〇，此時絕緣膠 8 0 6尚未注入。 1229429 五、發明說明（9)First, as shown in FIG. 8, a metal wire 802 is threaded into a wire bonding tool 804. Here, the wire bonding tool 804 is provided with an injection tube 808 for providing insulating glue 80 6 in the inner layer. The glue injection port 80 8a of the rubber tube 80 8 is set at the joining end of the wire bonding tool 804; and the end of the metal wire 80 2 is sintered into a metal ball 8 1 0 by means of electronic ignition or hydrogen flame. At this time, The insulating glue 8 0 6 has not been injected yet. 1229429 V. Description of the invention (9)

然後如第9圖所示，打線接合工具804將該金屬球810下 壓至s亥晶片204表面之晶片鲜塾302上，使金屬球810與晶 片銲墊302形成緊密接合；完成晶片銲墊3〇2之接合後，參 照第1 0圖，將打線接合工具8 0 4略微升起，並同時利用注 膠管808進行注膠，使自注膠口 8 0 8 a流出之絕緣膠8 0 6包覆 於金屬線8 0 2表面並且較佳地使該絕緣膠8 〇 6流至該半導體 晶片2 0 4之晶片銲墊3 0 2上。請接續參閱第11圖所示，繼續 移動該打線接合工具8 0 4，以拉伸金屬線8 〇 2並同時引導金 屬線8 02至該基板20 2表面之接墊3 0 4上。此時，係同步於 金屬線8 0 2外表面形成一層絕緣膠8 〇 6。接著，接近該接塾 3 0 4上方時，停止注膠。參照第1 2圖，再壓印該金屬線 802，使金屬線802與接墊304緊密接合藉此形成該包覆有 絕緣薄膜2 1 0之連接線2 0 6。較佳地，在此步驟之後再度注 膠使該絕緣膠806流至該基板20 2表面之接墊3 04上。最後 如第1 3圖所示將金屬線8 0 2加以載斷。Then, as shown in FIG. 9, the wire bonding tool 804 presses the metal ball 810 onto the wafer 塾 302 on the surface of the wafer 204 to form a tight bond between the metal ball 810 and the wafer pad 302; the wafer pad 3 is completed After the 〇2 is joined, referring to Fig. 10, raise the wire bonding tool 804 slightly, and use the injection tube 808 to perform the injection at the same time, so that the insulating adhesive 8 0 6 that flows out from the injection port 8 0 8 a Cover the surface of the metal wire 802 and preferably allow the insulating paste 806 to flow onto the wafer pads 302 of the semiconductor wafer 204. Please continue to refer to FIG. 11 and continue to move the wire bonding tool 804 to stretch the metal wire 802 and guide the metal wire 802 to the pad 304 on the surface of the substrate 202 at the same time. At this time, a layer of insulating glue 806 is formed synchronously with the outer surface of the metal wire 802. Then, close to the top of the connector 304, stop the injection. Referring to FIG. 12, the metal wire 802 is embossed again, so that the metal wire 802 and the pad 304 are tightly bonded to form the connecting wire 2 06 covered with the insulating film 2 10. Preferably, the glue is injected again after this step to make the insulating glue 806 flow onto the pads 3 04 on the surface of the substrate 20 2. Finally, the metal wire 8 0 2 is cut off as shown in FIG. 13.

其中’注膠管除了如8圖所不設置於打線接合工具（毛 細管狀鋼嘴）内層之外，亦可設置於打線接合工具之外 層；且在該注膠管上更設有一控制閥，以藉此控制該絕緣 膠之流量，使絕緣膠恰可包覆在金屬線之表面。 第1 4 -1 6圖係圖示根據本發明另一實施例的包覆有絕緣 薄膜之連接線製造方法。該方法係先利用習用的打線技術 形成不具絕緣薄膜之連接線2 0 6，再以如第1 6圖所示可以 例如噴塗的方式將一絕緣材料塗佈於該連接線2〇6表面、 半導體晶片204的晶片銲墊302以及該基板2〇2的接塾304上Among them, in addition to the inner layer of the wire bonding tool (capillary-shaped steel nozzle) as shown in Figure 8, the injection pipe can also be provided outside the wire bonding tool; and a control valve is provided on the glue tube to thereby Control the flow of the insulating glue so that the insulating glue can just cover the surface of the metal wire. Figures 1 4 to 16 are diagrams illustrating a method for manufacturing a connection wire covered with an insulating film according to another embodiment of the present invention. This method first uses conventional wire bonding technology to form a connection wire 206 without an insulating film, and then, as shown in FIG. 16, an insulating material can be applied to the surface of the connection wire 206, such as by spraying. The wafer pad 302 of the wafer 204 and the connection 304 of the substrate 202

第14頁 1229429 五、發明說明（10) 或是該半導體晶片204以及該基板2 0 2的整個上表面。習用 的打線技術包含以下步驟。首先將一金屬線1 4 0 2穿置於一Page 14 1229429 V. Description of the invention (10) or the entire upper surface of the semiconductor wafer 204 and the substrate 202. The conventional wire bonding technique consists of the following steps. First put a metal wire 1 4 0 2 on a

打線接合工具1 4 0 4中；並利用電子點火或氫焰的方式將金 屬線1 4 0 2末端燒結成一金屬球1 4 0 6。然後，打線接合工具 1 404將該金屬球1 40 6下壓至該晶片204表面之晶片銲墊302 上，使金屬球1 40 6與晶片銲墊3 0 2形成緊密接合；完成晶 片銲墊3 0 2之接合後，移動該打線接合工具1 4 〇 4，以拉伸 金屬線1 40 2並同時引導金屬線1 40 2至該基板20 2表面之接 塾304上。再壓印該金屬線1402，使金屬線1402與接墊304 緊密接合藉此形成該連接線20 6。最後如第15圖所示將金 屬線1 4 0 2加以截斷。 一最後，在該晶片204與基板2 0 2之間形成複數個具有絕續 薄膜210之連接線2 0 6之後，再將該保護件2〇8利用黏著劑 等材料固接於該基板20 2上，使得該半導體晶片2〇4以及該 ，接線2 0 6係設於該保護件2 08以及該基板2〇2之間，而製 得如第2圖所示之半導體晶片封裝構造2 〇 〇。 一雖然本發明已以前述較佳實施例揭示，然其並非用以限 =發明，任何熟習此技藝者，在不脫離本發明之精神和The wire bonding tool 1 4 0 4 is used; and the end of the metal wire 1 40 2 is sintered into a metal ball 1 4 6 by means of electronic ignition or hydrogen flame. Then, the wire bonding tool 1 404 presses the metal ball 1 40 6 onto the wafer pad 302 on the surface of the wafer 204, so that the metal ball 1 40 6 and the wafer pad 3 0 2 form a tight joint; the wafer pad 3 is completed After the bonding of 0 2, the wire bonding tool 1 4 04 is moved to stretch the metal wire 1 40 2 and simultaneously guide the metal wire 1 40 2 to the joint 304 on the surface of the substrate 20 2. The metal wire 1402 is embossed, and the metal wire 1402 and the pad 304 are tightly bonded to form the connection wire 20 6. Finally, as shown in Fig. 15, the metal wire 1420 is truncated. Finally, after forming a plurality of connection wires 20 with a discontinuous film 210 between the wafer 204 and the substrate 202, the protection member 208 is fixed to the substrate 20 with an adhesive or the like. Then, the semiconductor wafer 204 and the wiring 206 are provided between the protection member 08 and the substrate 200, and a semiconductor wafer package structure 2 as shown in FIG. 2 is obtained. . First, although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the invention. Any person skilled in the art will not depart from the spirit and scope of the present invention.

當可：ΐ種之更動與修改。因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。When it is possible: to make changes and modifications. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

第15頁 1229429 圖式簡單說明 【圖式簡單說明】 第1圖··一習用之半導體晶片封裝構造之剖視圖； 第2 A圖：根據本發明一實施例之半導艘晶片封裝構& 剖視圖； 第2B圖：根據本發明另一實施例之爭導體晶片封裝構造 之剖視圖； 第3 - 7圖：根據本發明一實施例以剖祝圖圖示形成複數 個包覆有絕緣薄膜之連接線的主要步騍；Page 15 1229429 Brief Description of Drawings [Simplified Illustration of Drawings] Figure 1 ·· A cross-sectional view of a conventional semiconductor chip package structure; Figure 2 A: A semi-conductor chip package structure according to an embodiment of the present invention & Figure 2B: a cross-sectional view of a conductor chip package structure according to another embodiment of the present invention; Figures 3-7: a plurality of connecting wires covered with an insulating film are formed according to a cross-sectional view according to an embodiment of the present invention; The main steps of

第8 -1 3圖：根據本發明另一實施例以别視圖圖示形成複 數個包覆有絕緣薄膜之連接線的主要步*鄉’ 第1 4 - 1 6圖··根據本發明一實施例以别視圖圖示形成一 連接線以及在該連接線上形成一絕緣薄膜的主要步驟；以 及 第1 7圖：根據本發明一實施例之用於爭導體晶片封裝構 造之保護件的背視圖。Fig. 8-1 3: According to another embodiment of the present invention, the main steps of forming a plurality of connecting wires covered with an insulating film are shown in a different view. Fig. 1 4-16 Fig. 1 · Implementation according to the present invention For example, the main steps of forming a connection line and forming an insulating film on the connection line are shown in another view; and FIG. 17 is a rear view of a protective member for a conductor chip package structure according to an embodiment of the present invention.

圖號 說明： 100 半 導 體 晶 片 封 装 構造 102 半 導 體 晶片 104 基 板 106 錫 球 銲 墊 108 錫 球 110 封 膠 體 112 連 接 線 200 半 導 體 晶 片 封 较 構造 202 基 板 204 半 導 體 晶 片 206 連 接 線 208 保 護 件 210 絕 緣 薄 膜Drawing number description: 100 semiconductor wafer packaging structure 102 semiconductor wafer 104 base plate 106 solder ball pad 108 tin ball 110 sealing gel 112 connection line 200 semiconductor wafer sealing structure 202 substrate semiconductor wafer 206 connection connection 210 connection

1229429 圖式簡單說明 212 敎 導 介 面物質 250 半 導 體 晶片封裝 構造 2 5 2 散 敎 件 2 5 2a 凹 部 302 晶 片 銲 墊 304 接 塾 306 絕 緣 導 線 3 0 6a 金 屬 線 3 0 6b 絕 緣 薄 膜 308 打 線 接 合 工 具 310 金 屬 球 802 金 屬 線 804 打 線 接 合 工 具 806 絕 緣 膠 808 注 膠 管 8 0 8a 注 膠 V 810 金 屬 球 1402 金 屬 線 1404 打 線 接 合 工 具 1406 金 屬 球 1700 保 護 件 1702 突 出 點1229429 Brief description of the diagram 212 Conductive interface material 250 Semiconductor chip package structure 2 5 2 Loose parts 2 5 2a Recess 302 Wafer pad 304 Connection 306 Insulated wire 3 0 6a Metal wire 3 0 6b Insulating film 308 Wire bonding tool 310 Metal ball 802 Metal wire 804 Wire bonding tool 806 Insulating adhesive 808 Rubber tube 8 0 8a Plastic injection V 810 Metal ball 1402 Metal wire 1404 Wire bonding tool 1406 Metal ball 1700 Protective member 1702 Protruding point

第17頁Page 17

Claims (1)

1229429 六、申請專利範圍 1、 一種半導體晶片封裝構造，其包含： 一基板； 一半導體晶片固接於該基板上； 複數個連接線（bonding wires)將該晶片電性連接於該 基板； ' ~ 一絕緣薄膜覆蓋每一連接線的整個表面；以及 一保護件固接於該基板上，使得該半導體晶片以及該連 接線係設於該保護件以及該基板之間。 2、 如申請專利範圍第1項所述之半導體晶片封裝構造，其 中該保護件係為一散熱件（h e a t s i n k)。 3、 如申請專利範圍第2項所述之半導體晶片封裝構造，其 中該散熱件係具有一凹部直接接觸該半導體晶片。 4、 如申請專利範圍第2項所述之半導體晶片封裝構造，其 另包含一熱導介面物質（thermal interface material ， T I Μ )設於該半導體晶片與該保護件之間。 5、 如申請專利範圍第1項所述之半導體晶片封裝構造，其 中該保護件係由金屬製成。 6、如申請專利範圍第1項所述之半導體晶片封裝構造，其 中該保護件與該基板結合以形成一密閉空間用以容納該半1229429 VI. Application Patent Scope 1. A semiconductor chip package structure including: a substrate; a semiconductor wafer is fixed on the substrate; a plurality of bonding wires electrically connect the chip to the substrate; An insulating film covers the entire surface of each connection line; and a protection member is fixed on the substrate, so that the semiconductor wafer and the connection line are disposed between the protection member and the substrate. 2. The semiconductor chip package structure described in item 1 of the scope of the patent application, wherein the protective member is a heat sink (h e a t s i n k). 3. The semiconductor wafer package structure described in item 2 of the scope of the patent application, wherein the heat sink has a recessed portion that directly contacts the semiconductor wafer. 4. The semiconductor chip package structure as described in item 2 of the scope of the patent application, further comprising a thermal interface material (TIM) disposed between the semiconductor chip and the protective member. 5. The semiconductor chip package structure described in item 1 of the scope of patent application, wherein the protective member is made of metal. 6. The semiconductor chip package structure according to item 1 of the scope of patent application, wherein the protection member is combined with the substrate to form a closed space for accommodating the half 1229429 六、申請專利範圍 --- 導體晶片以及該連接線。 7、 如申請專利範圍第1項所述之半導體晶片封裝構造，其 中4半V體曰曰片具有複數個晶片銲墊（b〇nding pa(js)，該 基板具有複數個接墊（contact pads)，該連接線係用以將 該晶片銲墊連接於該接墊，並且該絕緣薄膜亦覆蓋於該晶 片銲墊以及該接墊的整個表面。1229429 6. Scope of patent application --- Conductor chip and the connection line. 7. The semiconductor wafer package structure described in item 1 of the scope of the patent application, wherein the four-half V-body chip has a plurality of wafer pads (bonding pa (js), and the substrate has a plurality of contact pads (contact pads) ), The connecting line is used to connect the wafer pad to the pad, and the insulating film also covers the entire surface of the wafer pad and the pad. 8、 如申請專利範圍第1項所述之半導體晶片封裝構造，其 中该基板以及該半導體晶片分別具有相對之上下表面，該 半導體晶片係以其下表面設於該基板之上表面，並且該絕 緣薄膜亦覆蓋該半導體晶片以及該基板的整個上表面。 9、 如申請專利範圍第1項所述之半導體晶片封裝構造，其 中該絕緣薄膜係由環氧樹脂所構成者。8. The semiconductor wafer package structure according to item 1 of the scope of the patent application, wherein the substrate and the semiconductor wafer each have opposite upper and lower surfaces, the semiconductor wafer is provided on the upper surface of the substrate with its lower surface, and the insulation is The film also covers the entire upper surface of the semiconductor wafer and the substrate. 9. The semiconductor chip package structure described in item 1 of the scope of patent application, wherein the insulating film is made of epoxy resin. 第19頁 1 0、一種半導體晶片封裝構造之製造方法，其包含下列步 驟： 將一半導體晶片固接於一基板； 以複數個連接線將該半導體晶片電性連接於該基板； 形成一絕緣薄膜於該連接線的整個表面；以及 將一保護件固接於該基板上，使得該半導體晶片以及該 連接線係設於該保護件以及該基板之間。 1229429 六、申請專利範圍 11、如申請專利範圍第1 〇項所述之半導體晶片封裝構造的 製造方法，其中該絕緣薄膜之形成步驟係由喷塗一絕緣材 料於該連接線之整個表面而達成° 1 2、如申請專利範圍第1 〇項所述之半導體晶片封裝構造的 製造方法，其中該半導體晶片具有複數個晶片銲墊 (bonding pads)，該基板具有複數個接墊（con1:act p a d s )，該連接線係用以將該晶片銲墊連接於該接墊，並 且該絕緣薄膜形成之步驟係由噴塗一絕緣材料於該連接 線、該晶片銲墊以及該接墊之整個表面而達成。 1 3、如申請專利範圍第1 〇項所述之半導體晶片封裝構造的 製造方法，其中該基板以及該爭導體晶片分別具有相對之 上下表面，該半導體晶片係以其下表面設於該基板之上表 面，並且該絕緣薄膜形成之步驟係由喷塗一絕緣材料於該 連接線的整個表面、該半導體晶片以及該基板的整個上表 面而達成。 1 4、如申請專利範圍第丨〇項所述之半導體晶片封裝構造的 製造方法，其中該保護件係為一散熱件（h e a t s i n k)。 1 5、如申請專利範圍第1 4項所述之半導體晶片封裝構造， 其中該散熱件係具有一凹部直接接觸該半導體晶片。10. A method for manufacturing a semiconductor wafer package structure, comprising the following steps: fixing a semiconductor wafer to a substrate; electrically connecting the semiconductor wafer to the substrate with a plurality of connection lines; forming an insulating film On the entire surface of the connection line; and a protection member is fixed on the substrate, so that the semiconductor wafer and the connection line are disposed between the protection member and the substrate. 1229429 VI. Patent application scope 11. The method for manufacturing a semiconductor wafer package structure as described in item 10 of the patent application scope, wherein the step of forming the insulating film is achieved by spraying an insulating material on the entire surface of the connection line ° 1 2. The method for manufacturing a semiconductor wafer package structure as described in Item 10 of the scope of patent application, wherein the semiconductor wafer has a plurality of bonding pads and the substrate has a plurality of con1: act pads ), The connection line is used to connect the wafer pad to the pad, and the step of forming the insulating film is achieved by spraying an insulating material on the entire surface of the connection line, the wafer pad and the pad. . 13 3. The method for manufacturing a semiconductor wafer package structure as described in item 10 of the scope of patent application, wherein the substrate and the conductor wafer each have opposite upper and lower surfaces, and the semiconductor wafer is provided with its lower surface on the substrate. The upper surface, and the step of forming the insulating film is achieved by spraying an insulating material on the entire surface of the connection line, the semiconductor wafer, and the entire upper surface of the substrate. 14. The method for manufacturing a semiconductor chip package structure as described in item No. 0 of the patent application scope, wherein the protection member is a heat sink (h e a t s i n k). 15. The semiconductor chip package structure according to item 14 of the scope of patent application, wherein the heat sink has a recessed portion directly contacting the semiconductor chip. 第20頁 1229429 六、申請專利範圍 1 6、如申請專利範圍第1 4項戶斤述之半導體晶片封裝構造的 製造方法，另包含形成一熱導介面物質（thermal interface material，TIM)於該半導體晶片與該散熱件 之間。 1 7、如申請專利範圍第1 〇項所述之半導體晶片封裝構造之 製造方法，其中該絕緣薄膜係由環氧樹脂所構成者。 18、 驟： 種半導體晶片封裝構造之製造方法’其包含下列步 將一半導體晶片固接於一基板； 形成複數個包覆有絕緣薄膜之連接線將該半導體晶片電 性連接於該基板；以及 將一保護件固接於該基板上，使得該半導體晶片以及該 連接線係設於該保護件以及該基板之間。 1 9、如申請專利範圍第1 8項所述之半導體晶片封裝構造的 製造方法，其中該包覆有絕緣薄膜之連接線之形成步驟係 包含： 提供一絕緣導線，其係在一金屬線之外表面包覆一絕緣 薄膜； 將该絕緣導線穿過一打線接合工具並加熱之，使該絕緣 V線外表絕緣薄膜端點受熱破裂而露出該金屬線並燒結成 球； 儿〇Page 20 1229429 VI. Patent Application Range 16. The manufacturing method of the semiconductor chip package structure described in item 14 of the patent application range, further comprising forming a thermal interface material (TIM) on the semiconductor Between the chip and the heat sink. 17. The method for manufacturing a semiconductor chip package structure according to item 10 of the scope of patent application, wherein the insulating film is made of epoxy resin. 18. Step: A method of manufacturing a semiconductor wafer package structure, which includes the following steps of fixing a semiconductor wafer to a substrate; forming a plurality of connecting wires covered with an insulating film to electrically connect the semiconductor wafer to the substrate; and A protection member is fixed on the substrate, so that the semiconductor wafer and the connection line are disposed between the protection member and the substrate. 19. The method for manufacturing a semiconductor chip package structure as described in item 18 of the scope of the patent application, wherein the step of forming the connecting wire covered with an insulating film includes: providing an insulated wire, which is a metal wire The outer surface is covered with an insulating film; the insulated wire is passed through a wire bonding tool and heated, so that the ends of the insulating V-line external insulating film are thermally cracked to expose the metal wire and sintered into a ball; 第21頁 1229429 六、申請專利範圍 該 打線接合工具將該金屬球卞壓至該半導體晶片上進行 该絕緣導線至該基板上，以 接合；及 升起該打線接合工具並引導 ^ ^ ^ u ± , ^ a省说你甘X μ A霖出而與该基板接合藉此形成 ，隨後截斷該導線 壓印該絕緣導線使其金屬線步 ^ # ^. 該包覆有絕緣薄膜之連接線 20、如申請專利範圍第19項戶斤述之半，體晶片封裝構造的 製造方法，另包含在形成包覆有^緣薄膜之連接線之後以 及將該保護件固接於該基板上之前，佈二絕緣材料於由該 連接線電性連接之該半導體晶片之晶片録塾以及該基板之 接墊之整個表面。 2 1、如申請專利範圍第1 9項所述之半導體晶片封裝構造的 製造方法，另包含在形成包覆有絕緣薄膜之連接線之後以 及將該保護件固接於該基板上之前塗佈一絕緣材料於該基 板以及該半導體晶片的整個上表面。 2 2、如申請專利範圍第1 8項所述之半導體晶片封裝構造的 製造方法，其中該包覆有絕緣薄膜之連接線之形成步驟係 包含： 將一金屬線穿置於一打線接合工具中，並在該打線接合 工具之接合端點環設一注膠口； 將該金屬線燒結成球，使該打線接合工具將該金屬球下 壓至該半導體晶片上進行接合；Page 21 1229429 VI. Application scope The wire bonding tool presses the metal ball onto the semiconductor wafer to perform the insulated wire on the substrate for bonding; and raises the wire bonding tool and guides ^ ^ ^ u ± , ^ a province said you Gan X μ A Lin came out and joined with the substrate to form, and then cut off the wire and embossed the insulated wire to make the metal wire step ^ # ^. The insulated wire 20, For example, the manufacturing method of the body chip package structure described in item 19 of the scope of the patent application includes the following steps: after forming the connection line covered with the edge film and before fixing the protective member on the substrate, The insulating material is recorded on the wafer of the semiconductor wafer electrically connected by the connecting wire and the entire surface of the pad of the substrate. 2 1. The method for manufacturing a semiconductor chip package structure as described in item 19 of the scope of the patent application, further comprising applying a coating after forming a connection line covered with an insulating film and before fixing the protection member on the substrate. The insulating material is on the entire upper surface of the substrate and the semiconductor wafer. 2 2. The method for manufacturing a semiconductor chip package structure as described in item 18 of the scope of the patent application, wherein the step of forming the connection line covered with an insulating film includes: passing a metal wire into a wire bonding tool And a glue injection port is provided at the joint end point of the wire bonding tool; the metal wire is sintered into a ball, and the wire bonding tool presses the metal ball onto the semiconductor wafer for bonding; 1229429 六、申請專利範圍 升起該打線接合工具，同時進行注膠，使該注膠口流出 之絕緣膠包覆該金屬線，並將其引導至該基板；及 停止注膠，再壓印該金屬線，使該金屬線與該基板接合 藉此形成該包覆有絕緣薄膜之連接線，隨後截斷該金屬 線。 2 3、如申請專利範圍第2 2項所述之半導體晶片封裝構造的 製造方法，其中該包覆有絕緣薄膜之連接線之形成步驟另 包含： 將該金屬球下壓至該半導體晶片上進行接合之後進行注 膠，使該注膠口流出之絕緣膠流至該半導體晶片；以及 使該金屬線與該基板接合之後再進行注膠，使該注膠口 流出之絕緣膠流至該基板。 24、如申請專利範圍第22項所述之半導體晶片封裝構造的 製造方法，其中該注膠口係為一設置於該打線接合工具内 層或外層之注膠管的開口，以供該絕緣膠喷出。 2 5、如申請專利範圍第2 2項所述之半導體晶片封裝構造的 製造方法，其中在該注膠管上更設有一控制閥，以控制該 絕緣膠之流量。 2 6、如申請專利範圍第1 9或2 2項所述之半導體晶片封裝構 造的製造方法，其中在該金屬線燒結成球之步驟中，係採1229429 VI. The scope of the patent application is to raise the wire bonding tool and perform glue injection at the same time, so that the insulating glue flowing out of the glue injection port covers the metal wire and guides it to the substrate; A metal wire that joins the metal wire to the substrate to form the connection wire covered with an insulating film, and then cuts the metal wire. 2 3. The method for manufacturing a semiconductor wafer package structure as described in item 22 of the scope of the patent application, wherein the step of forming the connection line covered with the insulating film further comprises: pressing the metal ball onto the semiconductor wafer After bonding, glue injection is performed so that the insulating glue flowing out of the glue injection port flows to the semiconductor wafer; and after the metal wire is bonded to the substrate, glue injection is performed so that the insulating glue flowing out of the glue injection port flows to the substrate. 24. The method for manufacturing a semiconductor chip package structure according to item 22 of the scope of the patent application, wherein the glue injection port is an opening of a glue injection tube provided on the inner layer or the outer layer of the wire bonding tool for the insulating glue to be sprayed out. . 25. The method for manufacturing a semiconductor chip package structure according to item 22 of the scope of the patent application, wherein a control valve is further provided on the glue injection tube to control the flow of the insulating glue. 2 6. The method for manufacturing a semiconductor chip package structure as described in item 19 or 22 of the scope of patent application, wherein in the step of sintering the metal wire into a ball, 第23頁 1229429 申請專利範圍 用電子點火及氫焰其中之一完成燒 2 7、如申請專利範圍第1 9或2 2項所述之半導體晶片封裝構 造的製造方法，其中在進行該金屬球與該半導體晶片之接 合步驟中，係利用超音波震動或熱塵接合方式完成接合。 2 8、如申請專利範圍第1 9或2 2項所述之半導體晶片封裝構 造的製造方法，其中該打線接合工具係為一毛細管狀之鋼 嘴。 2 9、如申請專利範圍第丨8項所述之半導體晶片封裝構造的 製造方法，其中該絕緣薄膜係由環氧樹脂所構成者。 3 0、如申請專利範圍第1 8項所述之半導體晶片封裝構造的 製造方法，其中該保護件係為〆散熱件（heat sink)。 3 1、如申請專利範圍第3 〇項所述之半導體晶片封裝構造的 製造方法，另包含形成一熱導介面物質（thermal interface material，TIM)於該半導體晶片與該散熱件 之間。 3 2、如申請專利範圍第3 0項所述之半導體晶片封裝構造 其中該散熱件係具有一凹部直接接觸該半導體晶片。1229429 on page 23 The scope of the patent application is to complete the burning with one of an electronic ignition and a hydrogen flame. 27. The method for manufacturing a semiconductor wafer package structure described in item 19 or 22 of the scope of patent application, wherein the metal ball and the In the bonding step of the semiconductor wafer, bonding is performed by using ultrasonic vibration or hot dust bonding. 28. The method for manufacturing a semiconductor wafer package structure as described in item 19 or 22 of the scope of the patent application, wherein the wire bonding tool is a capillary-shaped steel mouth. 29. The method for manufacturing a semiconductor chip package structure according to item 8 of the patent application scope, wherein the insulating film is made of epoxy resin. 30. The method for manufacturing a semiconductor chip package structure as described in item 18 of the scope of patent application, wherein the protection member is a heat sink. 3 1. The method for manufacturing a semiconductor wafer package structure as described in item 30 of the scope of patent application, further comprising forming a thermal interface material (TIM) between the semiconductor wafer and the heat sink. 3 2. The semiconductor chip package structure as described in item 30 of the scope of patent application, wherein the heat sink has a recessed portion that directly contacts the semiconductor chip. 第24頁Page 24
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