TWI228805B - Flip-chip bonding process - Google Patents

Flip-chip bonding process Download PDF

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Publication number
TWI228805B
TWI228805B TW092108766A TW92108766A TWI228805B TW I228805 B TWI228805 B TW I228805B TW 092108766 A TW092108766 A TW 092108766A TW 92108766 A TW92108766 A TW 92108766A TW I228805 B TWI228805 B TW I228805B
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Taiwan
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bumps
flip
bonding process
patent application
scope
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TW092108766A
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Chinese (zh)
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TW200423321A (en
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Chaur-Chin Yang
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Advanced Semiconductor Eng
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

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  • Wire Bonding (AREA)

Abstract

A flip-chip bonding process is provided to attach a chip on a substrate. By means of stripping off a part of the oxide on the surface of the bumps and a flux film forms around the stripped portion of the oxide, here the outside surface of the bumps. When the chip attaches to the substrate thereby through the bumps which is under reflow process, the flux film is easy to clear the oxide on the surface of the bump because the oxide is destroyed. It facilitates the bonding well between the chip and the substrate and reduces the contact resistance thereof.

Description

1228805 五、發明說明(1) 【發明所屬之技術領域】 本發明是有關於一種覆晶接合製程,且特別是有關於 一種提昇晶片與基板之接合性的覆晶接合製程。 【先前技術】1228805 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a flip-chip bonding process, and more particularly, to a flip-chip bonding process that improves the bonding between a wafer and a substrate. [Prior art]

覆晶接合技術(F 1 i p C h i p I n t e r c ο η n e c t Technology ,簡稱FC)乃是利用面陣列(area array)的 方式,將多個晶片墊(die pad)配置於晶片(die)之主 動表面(active surface )上,並在晶片墊上形成凸塊 (bump ),接著將晶片翻覆(f 1 i p )之後,再利用這些凸 塊來分別電性及機械性連接晶片之晶片墊至承載器 (carrier )上的接點(c ο n t a c t ),使得晶片可經由凸塊 而電性連接至承載器,並經由承載器之内部線路而電性連 接至外界之電子裝置。值得注意的是,由於覆晶接合技術 (FC)係可適用於高腳數(High Pin Count)之晶片封裝 結構,並同時具有縮小晶片封裝面積及縮短訊號傳輸路徑 等諸多優點,所以覆晶接合技術目前已經廣泛地應用於晶 片封裝領域,常見應用覆晶接合技術之晶片封裝結構例如 有覆晶球格陣列型(Flip Chip Ball Grid Array, FC/BGA)及覆晶針格陣列型(Flip Chip Pin Grid Array,FC/PGA )等型態之晶片封裝結構。。F 1 ip C hip I nterc ο η nect Technology (FC for short) is a method of using area array to place multiple die pads on the active surface of a die. (Active surface), and bumps are formed on the wafer pad, and then the wafer is flipped (f 1 ip), and then these bumps are used to electrically and mechanically connect the wafer pad of the wafer to the carrier, respectively. ) Contact (c ntact), so that the chip can be electrically connected to the carrier through the bump, and electrically connected to the external electronic device through the internal circuit of the carrier. It is worth noting that, because the flip-chip bonding technology (FC) is applicable to high pin count (High Pin Count) chip packaging structure, and has many advantages such as reducing the chip packaging area and shortening the signal transmission path, so the flip-chip bonding The technology has been widely used in the field of chip packaging. Common chip packaging structures using flip-chip bonding technology include Flip Chip Ball Grid Array (FC / BGA) and Flip Chip Array (Flip Chip). Pin Grid Array (FC / PGA) and other types of chip packaging structures. .

請參考第1 A〜1 D圖,其依序繪示習知之覆晶接合製程 的流程示意圖。習知之覆晶接合製程大致包括凸塊製作 (b u m p i n g )、晶圓切割(d i e s a w )、晶片接合 (bonding )及迴銲(reflow)等步驟。如第1A圖所示,Please refer to Figures 1A to 1D, which sequentially show the flow chart of the conventional flip-chip bonding process. The conventional flip-chip bonding process generally includes steps such as bump fabrication (b u m p i n g), wafer dicing (di e s a w), wafer bonding (bonding), and reflow (reflow). As shown in Figure 1A,

10550twf.ptd 第5頁 1228805 五、發明說明(2) 凸塊製程係指以蒸鑛(e v a ρ 〇 r a t i ο η )、印刷(printing )或電鑛(electroplating)的方式形成凸塊120於晶圓 1 1 0之晶片墊1 1 1上,而凸塊1 2 0例如為錫鉛凸塊,其錫鉛 比係為9 5 : 5或6 3 : 3 7。接著如第1 B圖所示,將晶圓1 1 0力口 以切割以形成單顆化之晶片1 1 2。接著如第1 C圖所示,晶 片接合係指將晶片11 2翻覆之後,再以真空吸嘴(v a c u uin c ο 1 1 e t ) 1 0吸附晶片1 1 2之背面,用以移動晶片1 1 2至基板 1 3 0上,使得晶片1 1 2之凸塊1 2 0分別接觸其所對應之基板 1 3 0的凸塊墊1 3 2 ,最後如第1 D圖所示,將藉由凸塊1 2 0接 觸之晶片1 1 2與基板1 3 0送入迴銲爐中進行迴銲,以完成覆 晶封裝之製作。 囉 如第1 C圖所示,值得注意的是,為了提昇晶片1 1 2與 基板1 3 0之間的接合性,習知技術乃在晶片1 1 2接合於基板 1 3 0之前,預先在凸塊1 2 0的表面形成助銲薄膜1 2 2,再將 晶片11 2之晶片墊1 1 1準確地配置於基板1 3 0之凸塊墊1 3 2 上。助銲薄膜1 2 2的作用不僅能暫時固定晶片1 1 2於基板 1 3 0上,且可使錫鉛凸塊1 2 0在進行迴銲時,藉由助銲薄膜 122來去除錫鉛凸塊120之表面的氧化層124。最後凸塊在 迴銲之後,再以清洗的方式將殘留於錫鉛凸塊1 2 0之表面 的助銲薄膜1 2 2加以去除。然而,當錫鉛凸塊1 2 0之表面的 氧化層1 2 4太厚,如此助銲薄膜1 2 2無法將氧化層1 2 4完全 清除時,將影響晶片1 1 2與基板1 3 0之間的接合性,並且增 加晶片1 1 2與基板1 3 0之間的接觸電阻。 【發明内容】10550twf.ptd Page 5 1228805 V. Description of the invention (2) The bump process refers to forming bumps 120 on the wafer by steaming (eva ρ 〇rati ο η), printing or electroplating. 1 1 0 is on the wafer pad 1 1 1, and the bump 1 2 0 is, for example, a tin-lead bump, and the tin-lead ratio is 9 5: 5 or 6 3: 37. Next, as shown in FIG. 1B, the wafer 110 is diced to form a singulated wafer 1 12. Then, as shown in FIG. 1C, the wafer bonding means that after the wafer 11 2 is turned over, a vacuum nozzle (vacuin c ο 1 1 et) 1 0 is used to adsorb the back of the wafer 1 1 2 to move the wafer 1 1 2 to the substrate 1 3 0, so that the bumps 1 2 0 of the wafer 1 12 respectively contact the bump pads 1 3 2 of the corresponding substrate 1 3 0, and finally, as shown in FIG. 1D, the bumps The wafers 12 and 120 in contact with the block 120 are sent to a reflow oven for reflow, so as to complete the fabrication of the flip-chip package.所示 As shown in Figure 1C, it is worth noting that, in order to improve the bonding between the wafer 1 12 and the substrate 1 30, the conventional technique is to pre-bond the wafer 1 12 to the substrate 1 30 in advance. A soldering film 1 2 2 is formed on the surface of the bump 1 2 0, and the wafer pad 1 1 1 of the wafer 11 2 is accurately disposed on the bump pad 1 3 2 of the substrate 1 3 0. The role of the flux film 1 2 2 can not only temporarily fix the wafer 1 12 to the substrate 130, but also enable the tin-lead bump 120 to remove the tin-lead bump by the flux film 122 during reflow. An oxide layer 124 on the surface of the block 120. Finally, after re-soldering, the soldering flux film 12 2 remaining on the surface of the tin-lead bump 120 is removed by cleaning. However, when the oxide layer 1 2 4 on the surface of the tin-lead bump 1 2 0 is too thick, so that the solder film 1 2 2 cannot completely remove the oxide layer 1 2 4, it will affect the wafer 1 1 2 and the substrate 1 3 0 And the contact resistance between the wafer 1 12 and the substrate 130 is increased. [Summary of the Invention]

10550twf.ptd 第6頁 1228805 五、發明說明(3) 因此,本發明的目的就是在提供一種覆晶接合製程, 用以提昇晶片與基板之間的接合性,並且降低晶片與基板 之間的接觸電阻。 為達上述之目的,本發明提出一種一種覆晶接合製 程,適用於將一晶片接合至一基板,其中晶片具有一主動 表面及多個凸塊,而這些凸塊係配置於主動表面,且這些 凸塊分別具有一氧化層,其分別覆蓋於這些凸塊所暴露出 之表面,並且基板更具有一基板表面及多個接合墊,而這 些接合墊係配置於基板表面。此覆晶接合製程至少包括下 列步驟:(a )移除這些凸塊之局部的這些氧化層;(b ) 分別形成一助銲薄膜於這些凸塊之外表面,且助銲薄膜係+ 至少形成於凸塊之已去除氧化層的局部外表面;(c )將 這些凸塊分別接觸至其所對應之這些接合墊之一以及(d )迴銲這些凸塊,使得這些凸塊分別接合至其所對應之這 些接合墊之一,並使得這些助銲薄膜分別清除其所對應包 覆之這些氧化層之一。 依照本發明之較佳實施例所述,上述於步驟(a )之 時,包括以研磨的方式來移除局部之這些氧化層。此外, 於步驟(b )之時,包括以沾附的方式來形成這些助銲薄 膜。另外,基板更具有多個預銲塊,其分別連接至其所對 應之這些接合墊之一,且於步驟(c )之時,這些凸塊係 分別經由其所對應之這些預銲塊之一,而間接地接觸其所 對應之這些接合墊之一,且於步驟(d)之時,這些凸塊 係分別接合至其所對應之這些預銲塊之一。10550twf.ptd Page 6 1228805 V. Description of the invention (3) Therefore, the object of the present invention is to provide a flip-chip bonding process to improve the bonding between the wafer and the substrate and reduce the contact between the wafer and the substrate. resistance. In order to achieve the above object, the present invention provides a flip-chip bonding process suitable for bonding a wafer to a substrate, wherein the wafer has an active surface and a plurality of bumps, and the bumps are arranged on the active surface, and these The bumps each have an oxide layer, which respectively covers the surfaces exposed by the bumps, and the substrate further has a substrate surface and a plurality of bonding pads, and these bonding pads are arranged on the substrate surface. This flip-chip bonding process includes at least the following steps: (a) removing portions of the oxide layers on the bumps; (b) forming a soldering film on the outer surface of the bumps, respectively, and the soldering film system + is formed at least on Localized outer surfaces of the bumps from which the oxide layer has been removed; (c) contacting the bumps to one of their corresponding bonding pads and (d) resoldering the bumps so that the bumps are bonded to their respective locations Corresponds to one of the bonding pads, and causes the soldering films to remove one of the corresponding oxidized layers. According to a preferred embodiment of the present invention, the above-mentioned step (a) includes removing the localized oxide layers by grinding. In addition, at the step (b), it includes forming these soldering films by means of adhesion. In addition, the substrate further has a plurality of pre-solder blocks, which are respectively connected to one of the corresponding bonding pads, and at step (c), the bumps are respectively passed through one of the corresponding pre-solder blocks. And indirectly contact one of the corresponding bonding pads, and at the time of step (d), the bumps are respectively bonded to one of the corresponding pre-soldering blocks.

10550twf.ptd 第7頁 1228805 五、發明說明(4) 本發明之覆晶接合製程乃藉由移除凸塊表面之部份氧 化層,使得助銲薄膜能輕易清除凸塊表面之氧化層,因此 可提昇晶片與基板之間的接合性,並且降低晶片與基板之 間的接觸電阻。 為讓本發明之上述目的、特徵和優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 【實施方式】 第2 A〜2 F圖依序繪示本發明一較佳實施例之一種覆晶 接合製程的流程示意圖。請參考第2 A及2 B圖,首先於一晶 圓2 0 0之表面上進行凸塊製程,並切割晶圓2 0 0以形成單顆4 化之晶片210。晶片210具有一主動表面212及多個凸塊 220,其中凸塊216係配置於晶片210之主動表面212,且凸 塊2 2 0之材質例如為錫鉛合金,其錫鉛比可為5 : 9 5或6 3 : 3 7。此外,凸塊2 2 0分別具有一氧化層2 2 2 ,其分別覆蓋於 凸塊220所暴露出之表面。接著請同時參考第2C及2E圖, 將晶片2 1 0翻覆之後,再以真空吸嘴1 0吸附晶片2 1 0之背面 2 1 4,用以移動晶片2 1 0至一基板2 3 0上,以使晶片2 1 0藉由 凸塊2 2 0而接合於基板2 3 0。 請同時參考第2 C及2 D圖,值得注意的是,為了提昇晶 片2 1 0與基板2 3 0之間的接合性,本發明乃以研磨的方式來 移除位於凸塊2 2 0之較遠離晶片2 1 0之一端的局部之氧化層邋> 2 2 2,以破壞凸塊2 2 0之頂端的局部之氧化層。接著再分別 形成一助銲薄膜2 24於&塊2 2 0之外表面,且助銲薄膜2 2 410550twf.ptd Page 7 1228805 V. Description of the invention (4) The flip-chip bonding process of the present invention removes part of the oxide layer on the surface of the bump, so that the flux film can easily remove the oxide layer on the surface of the bump, so It can improve the bonding between the wafer and the substrate, and reduce the contact resistance between the wafer and the substrate. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to describe in detail as follows: [Embodiment] 2A ~ 2F 图 依A sequence diagram of a flip-chip bonding process according to a preferred embodiment of the present invention is shown in sequence. Please refer to FIGS. 2A and 2B. First, a bump process is performed on the surface of a wafer 200, and the wafer 200 is cut to form a single wafer 210. The wafer 210 has an active surface 212 and a plurality of bumps 220, wherein the bumps 216 are arranged on the active surface 212 of the wafer 210, and the material of the bumps 2 2 0 is, for example, a tin-lead alloy, and its tin-lead ratio can be 5: 9 5 or 6 3: 37. In addition, the bumps 2 2 0 each have an oxide layer 2 2 2, which respectively covers the surfaces exposed by the bumps 220. Please refer to Figures 2C and 2E at the same time. After turning over the wafer 2 1 0, use the vacuum nozzle 10 to suck the back 2 1 4 of the wafer 2 1 0 to move the wafer 2 1 0 to a substrate 2 3 0. So that the wafer 2 10 is bonded to the substrate 2 3 0 through the bump 2 2 0. Please refer to Figures 2C and 2D at the same time. It is worth noting that in order to improve the bonding between the wafer 2 10 and the substrate 2 3 0, the present invention removes the bumps 2 2 0 by grinding. The local oxide layer 远离 > 2 2 2 farther away from one end of the wafer 2 10 to destroy the local oxide layer on the top of the bump 2 2 0. Next, a flux film 2 24 is formed on the outer surface of the & block 2 2 0 respectively, and the flux film 2 2 4

10550twf.ptd 第8頁 1228805 五、發明說明(5) 係分別包覆於其所對應之氧化層2 2 2,重要的是,助銲薄 膜224至少要形成於凸塊220之已去除氧化層222的局部外 表面°助銲薄膜2 2 4係將凸塊2 2 0浸潰於盛有助銲劑3 0之容 器2 0中並取出凸塊2 2 0後所形成的。或者,助銲薄膜2 2 4係 以真空吸嘴吸起晶片2 1 0再下置於助銲劑平台以沾附助銲 劑而形成。 接著請參考第2E圖,提供一基板2 3 0,而基板2 3 0具有 一基板表面232及多個接合墊2 34,且接合墊2 34配置於基 板表面2 3 2。其中,晶片2 1 0藉由凸塊2 2 0而電性與機械性 連接於基板2 3 〇上,且凸塊2 2 0分別接觸至其所對應之接合 墊2 34。接著請參考第2F圖,將此凸塊2 2 0接觸之晶片210 與基板2 3 0送入迴銲爐中進行迴銲,使得凸塊2 2 〇分別接合 至其所對應之接合墊2 3 4,並使得助銲薄膜2 2 4分別清除其 所對應包覆之氧化層2 2 2。此時,由於氧化層2 2 2受到破 壞’因此助銲薄膜2 2 4可輕易地清除凸塊2 2 0之表面的氧化 層2 2 2 ,用以提昇晶片2 1 〇與基板2 3 0之的接合性,並降低 晶片2 1 0與基板2 3 0之間的接觸電阻。此外,如第2 E圖所 示,為使凸塊220能接合於接合墊234,基板230之接合墊 2 3 4上更具有多個預銲塊2 3 6 (pre - solder),而預銲塊236 之材質係為錫錯合金,其錫錯比例如為6 3 : 3 7。如此,凸 塊2 2 0可分別經由其所對應之預銲塊2 3 6,而間接地接觸其 所對應之接合墊234,並在迴銲凸塊220時,凸塊220可分 別接合其所對應之預銲塊2 3 6。最後在凸塊2 2 0迴銲之後, 再以清洗的方式將殘留於凸塊2 2 0之表面的助銲薄膜2 24加10550twf.ptd Page 8 1228805 V. Description of the invention (5) It is respectively coated on the corresponding oxide layer 2 2 2. It is important that the flux film 224 is formed at least on the removed oxide layer 222 of the bump 220 The local outer surface of the flux film 2 2 4 is formed by dipping the bump 2 2 0 in the container 20 containing the flux 30 and taking out the bump 2 2 0. Alternatively, the flux film 2 2 4 is formed by sucking the wafer 2 10 with a vacuum nozzle and then placing it on the flux platform to attach the flux. Referring to FIG. 2E, a substrate 2 3 0 is provided. The substrate 2 3 0 has a substrate surface 232 and a plurality of bonding pads 2 34, and the bonding pads 2 34 are disposed on the substrate surface 2 3 2. The wafer 2 10 is electrically and mechanically connected to the substrate 2 3 0 through the bump 2 2 0, and the bump 2 2 0 is in contact with the corresponding bonding pad 2 34 respectively. Next, referring to FIG. 2F, the wafer 210 and the substrate 2 3 0 in contact with the bump 2 2 0 are sent to a reflow furnace for re-soldering, so that the bumps 2 2 0 are respectively bonded to the corresponding bonding pads 2 3 4, and the flux film 2 2 4 is used to remove the corresponding coated oxide layer 2 2 2 respectively. At this time, since the oxide layer 2 2 2 is damaged, the flux film 2 2 4 can easily remove the oxide layer 2 2 2 on the surface of the bump 2 2 0 to promote the wafer 2 1 0 and the substrate 2 3 0. And reduce the contact resistance between the wafer 210 and the substrate 230. In addition, as shown in FIG. 2E, in order to enable the bump 220 to be bonded to the bonding pad 234, the bonding pad 2 3 4 of the substrate 230 has a plurality of pre-soldering blocks 2 3 6 (pre-solder), and the pre-soldering is performed. The material of the block 236 is a tin-alloy, and the tin-alloy ratio is, for example, 6 3: 3 7. In this way, the bumps 2 2 0 can indirectly contact the corresponding bonding pads 234 through their corresponding pre-soldering bumps 2 3 6, and when the bumps 220 are re-soldered, the bumps 220 can be respectively bonded to their respective pads Corresponding pre-soldering block 2 3 6. Finally, after the bump 2 2 0 is re-soldered, the flux film 2 24 remaining on the surface of the bump 2 2 0 is added in a cleaning manner.

l()550twf.ptd 第9頁 1228805 五、發明說明(6) 以去除。 當然,在上述第2C及2D圖中,亦可先分別形成一助銲 薄膜2 2 4於凸塊2 2 0之外表面,且助銲薄膜2 2 4係分別包覆 於其所對應之氧化層2 2 2,之後再以研磨的方式來移除位 於凸塊2 2 0之較遠離晶片2 1 0之一端的局部之氧化層2 2 2, 以使助銲薄膜2 2 4可輕易地清除凸塊2 2 0之表面的氧化層 2 2 2。 請參考第3A〜3B圖,其依序繪示第2C圖之凸塊於研磨 前與研磨後的放大示意圖。習知凸塊2 2 0表面之氧化層2 2 2 太厚,如此助銲薄膜224無法完全去除氧化層222,而本發 明藉由研磨機來研磨凸塊2 2 0表面之局部的氧化層2 2 2,例 如全面性研磨凸塊2 2 0之頂部。因此,當凸塊2 2 0之表面形 成助銲薄膜2 24時,助銲薄膜224可輕易地清除凸塊2 2 0之 表面的氧化層2 2 2,以提昇晶片2 1 0與基板2 3 0之接合性, 並且降低晶片2 1 0與基板2 3 0之間的接觸電阻。 由上述之說明可知,本發明所揭露之覆晶接合製程乃 藉由去除凸塊表面之局部的氧化層,接著再分別形成一助 銲薄膜於凸塊之外表面,而助銲薄膜係可包覆氧化層。因 此,當晶片藉由凸塊而接觸基板並對凸塊進行迴銲之時, 由於氧化層受到破壞,因此助銲薄膜可輕易地清除凸塊表 面的氧化層,以提昇晶片與基板之接合性,並且降低晶片 與基板之間的接觸電阻。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 11l () 550twf.ptd Page 9 1228805 V. Description of the invention (6) To remove. Of course, in the above 2C and 2D drawings, it is also possible to first form a flux film 2 2 4 on the outer surface of the bump 2 2 0 respectively, and the flux film 2 2 4 is respectively coated on the corresponding oxide layer 2 2 2 and then remove the local oxide layer 2 2 2 located at one end of the bump 2 2 0 farther away from the wafer 2 1 0 by grinding, so that the soldering film 2 2 4 can easily remove the bump The oxide layer 2 2 2 on the surface of the block 2 2 0. Please refer to Figs. 3A to 3B, which sequentially show enlarged diagrams of the bumps of Fig. 2C before and after grinding. It is known that the oxide layer 2 2 2 on the surface of the bump 2 2 0 is too thick, so that the solder film 224 cannot completely remove the oxide layer 222, and the present invention uses a grinder to polish a local oxide layer 2 on the surface of the bump 2 2 0. 22, for example, the top of the comprehensively polished bump 2 2 0. Therefore, when the soldering film 2 24 is formed on the surface of the bump 2 2 0, the soldering film 224 can easily remove the oxide layer 2 2 2 on the surface of the bump 2 2 0 to enhance the wafer 2 1 0 and the substrate 2 3 0, and reduce the contact resistance between the wafer 210 and the substrate 230. It can be known from the above description that the flip-chip bonding process disclosed in the present invention removes a local oxide layer on the surface of the bump, and then forms a soldering film on the outer surface of the bump, respectively. The soldering film can be coated Oxide layer. Therefore, when the wafer contacts the substrate through the bump and re-solders the bump, the oxide layer is easily removed because of the oxide layer being damaged, so as to improve the bonding between the wafer and the substrate And reduce the contact resistance between the wafer and the substrate. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art will not depart from the essence of the present invention. 11

III IH 10550twf.ptd 第10頁 1228805 五、發明說明(7) 神和範圍内,當可作些許之更動與潤飾。例如,移除局部 氧化層的方式不限於研磨方式,也不限定於移除凸塊頂端 之氧化層,移除凸塊上任一部份之氧化層,均可達到本發 明之效果,因此本發明之保護範圍當視後附之申請專利範 圍所界定者為準。III IH 10550twf.ptd Page 10 1228805 V. Description of the invention (7) Within the scope of God and God, there should be some changes and retouching. For example, the method of removing the local oxide layer is not limited to the grinding method, nor is it limited to removing the oxide layer on the top of the bump. Removing the oxide layer on any part of the bump can achieve the effect of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

10550twf.ptd 第11頁 1228805 圖式簡單說明 第1 A〜1 D圖依序繪示習知之覆晶接合製程的流程示意 圖。 第2 A〜2 F圖依序繪示本發明一較佳實施例之一種覆晶 接合製程的流程示意圖。 第3 A〜3 B圖依序繪示研磨前與研磨後之晶片的凸塊放 大示意圖。 【圖式標記說明】 10 : 真空吸嘴 20 ·· 容器 30 : 助銲劑 110 晶 圓 111 晶 片 塾 112 晶 片 120 凸 塊 122 助 銲 薄 膜 124 氧 化 層 130 基 板 132 基 板 表 面 210 晶 片 2 12 主 動 表 面 214 背 面 220 凸 塊 222 氧 化 層 224 助 銲 薄 膜10550twf.ptd Page 11 1228805 Brief Description of Drawings Figures 1 A to 1 D sequentially show the flow chart of the conventional flip-chip bonding process. Figures 2A to 2F sequentially illustrate a flow chart of a flip-chip bonding process according to a preferred embodiment of the present invention. Figures 3A to 3B show the bump enlargement of the wafer before and after polishing in order. [Description of Graphical Symbols] 10: Vacuum Nozzle 20 ·· Container 30: Flux 110 wafer 111 wafer 塾 112 wafer 120 bump 122 flux film 124 oxide layer 130 substrate 132 substrate surface 210 wafer 2 12 active surface 214 back 220 bump 222 oxide layer 224 flux film

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10550twf.ptd 第12頁 122880510550twf.ptd Page 12 1228805

10550twf.ptd 第13頁10550twf.ptd Page 13

Claims (1)

1228805 六、申請專利範圍 1 . 一種覆晶接合製程,適用於將一晶片接合至一基 板,其中該晶片具有一主動表面及複數個凸塊,而該些凸 塊係配置於該主動表面,且該些凸塊分別具有一氧化層’ 其分別覆蓋於該些凸塊所暴露出之表面,並且該基板更具 有一基板表面及複數個接合墊,而該些接合墊係配置於該 基板表面,該覆晶接合製程至少包括下列步驟: (a )移除該些凸塊之局部的該些氧化層; (b )分別形成一助銲薄膜於該些凸塊之外表面,且 該助銲薄膜係至少形成於該凸塊之已去除該氧化層的局部 外表面; (c )將該些凸塊分別接觸至其所對應之該些接合墊 $ 之一;以及 (d )迴銲該些凸塊,使得該些凸塊分別接合至其所 對應之該些接合墊之一,並使得該些助銲薄膜分別清除其 所對應包覆之該些氧化層之一。 2 .如申請專利範圍第1項所述之覆晶接合製程,於步 驟(a )之時,移除之局部的該些氧化層係位於該些凸塊 之遠離該晶片的一端。 3 .如申請專利範圍第1項所述之覆晶接合製程,其中 該些凸塊之材質係為錫鉛合金。 4. 如申請專利範圍第3項所述之覆晶接合製程,其中 該些凸塊之錫鉛比係為5 : 9 5及6 3 : 3 7其中之一。 邐, 5. 如申請專利範圍第1項所述之覆晶接合製程,於步 驟(a )之時,包括以研磨的方式來移除局部之該些氧化1228805 VI. Scope of patent application 1. A flip-chip bonding process suitable for bonding a wafer to a substrate, wherein the wafer has an active surface and a plurality of bumps, and the bumps are arranged on the active surface, and The bumps each have an oxide layer, which respectively covers the surfaces exposed by the bumps, and the substrate further has a substrate surface and a plurality of bonding pads, and the bonding pads are disposed on the substrate surface. The flip-chip bonding process includes at least the following steps: (a) removing portions of the oxide layers of the bumps; (b) forming a soldering film on the outer surfaces of the bumps, respectively, and the soldering film is Formed on at least a portion of the outer surface of the bump from which the oxide layer has been removed; (c) contacting the bumps to one of the corresponding bonding pads $ respectively; and (d) resoldering the bumps , So that the bumps are respectively bonded to one of the bonding pads corresponding to the bumps, and the soldering flux films are respectively used to remove one of the oxide layers corresponding to the coatings. 2. According to the flip-chip bonding process described in item 1 of the scope of patent application, at step (a), the partially removed oxide layers are located at the ends of the bumps away from the wafer. 3. The flip-chip bonding process described in item 1 of the scope of the patent application, wherein the material of the bumps is a tin-lead alloy. 4. The flip-chip bonding process described in item 3 of the scope of patent application, wherein the tin-lead ratio of the bumps is one of 5: 9 5 and 6 3: 3 7.逦, 5. According to the flip-chip bonding process described in item 1 of the scope of patent application, at step (a), it includes grinding to remove the local oxidation. 10550twf.ptd 第14頁 1228805 六、申請專利範圍 層。 6 .如申請專利範圍第1項所述之覆晶接合製程,於步 驟(b )之時,包括以沾附一助銲劑的方式來形成該些助 銲薄膜。 7.如申請專利範圍第1項所述之覆晶接合製程,其中 該基板更具有複數個預銲塊,其分別連接至其所對應之該 些接合墊之一,且於步驟(c )之時,該些凸塊係分別經 由其所對應之該些預銲塊之一,而間接地接觸其所對應之 該些接合墊之一,且於步驟(d )之時,該些凸塊係分別 接合至其所對應之該些預銲塊之一。 8 .如申請專利範圍第7項所述之覆晶接合製程,其中 該些預銲塊之材質係為錫鉛合金,且該些預銲塊之錫鉛比 係為6 3 : 3 7。 9 · 一種覆晶接合製程,適用於將一晶片接合至一基 板,其中該晶片具有一主動表面及複數個凸塊,而該些凸 塊係配置於該主動表面,且該些凸塊分別具有一氧化層, 其分別覆蓋於該些凸塊所暴露出之表面,並且該基板更具 有一基板表面及複數個接合墊,而該些接合墊係配置於該 基板表面,該覆晶接合製程至少包括下列步驟: (a )分別形成一助銲薄膜於該些凸塊之外表面,且 該些助銲薄膜係分別包覆於其所對應之該些氧化層之一; (b )移除該些凸塊之局部的該些氧化層; (c )將該些凸塊分別接觸至其所對應之該些接合墊 之一;以及10550twf.ptd Page 14 1228805 Sixth, the scope of patent application. 6. The flip-chip bonding process described in item 1 of the scope of patent application, in step (b), includes forming the flux films by attaching a flux. 7. The flip-chip bonding process as described in item 1 of the scope of the patent application, wherein the substrate further has a plurality of pre-soldering blocks, which are respectively connected to one of the corresponding bonding pads, and in step (c) The bumps are indirectly in contact with one of the corresponding bonding pads through one of the corresponding pre-soldering blocks respectively, and at the time of step (d), the bumps are They are respectively joined to one of the corresponding pre-solder blocks. 8. The flip-chip bonding process described in item 7 of the scope of the patent application, wherein the material of the pre-solder blocks is a tin-lead alloy, and the tin-lead ratio of the pre-solder blocks is 6 3: 37. 9 · A flip-chip bonding process suitable for bonding a wafer to a substrate, wherein the wafer has an active surface and a plurality of bumps, and the bumps are arranged on the active surface, and the bumps have An oxide layer respectively covers the surfaces exposed by the bumps, and the substrate further has a substrate surface and a plurality of bonding pads, and the bonding pads are disposed on the substrate surface, and the flip-chip bonding process is at least The method includes the following steps: (a) forming a soldering film on the outer surfaces of the bumps, and respectively coating the soldering film on one of the corresponding oxide layers; (b) removing the soldering films; The oxide layers that are part of the bumps; (c) contacting the bumps to one of the corresponding bonding pads respectively; and 10550twf.ptd 第15頁 1228805 六、申請專利範圍 (d )迴銲該些凸塊,使得該些凸塊分別接合至其所 對應之該些接合墊之一,並使得該些助銲薄膜分別清除其 所對應包覆之該些氧化層之一。 I 0 .如申請專利範圍第9項所述之覆晶接合製程,於步 驟(a )之時,移除之局部的該些氧化層係位於該些凸塊 之运離έ亥晶片的一端。 II .如申請專利範圍第9項所述之覆晶接合製程,其中 該些凸塊之材質係為錫鉛合金。 1 2 .如申請專利範圍第1 1項所述之覆晶接合製程,其 中該些凸塊之錫鉛比係為5 : 9 5及6 3 : 3 7其中之一。 1 3 .如申請專利範圍第9項所述之覆晶接合製程,於步 驟(a )之時,包括以沾附一助銲劑的方式來形成該些助 銲薄膜。 1 4 .如申請專利範圍第9項所述之覆晶接合製程,於步 驟(b )之時,包括以研磨的方式來移除局部之該些氧化 層。 1 5 .如申請專利範圍第9項所述之覆晶接合製程,其中 該基板更具有複數個預銲塊,其分別連接至其所對應之該 些接合墊之一,且於步驟(c )之時,該些凸塊係分別經 由其所對應之該些預銲塊之一,而間接地接觸其所對應之 該些接合墊之一,且於步驟(d )之時,該些凸塊係分別 接合至其所對應之該些預銲塊之一。 1 6 .如申請專利範圍第1 5項所述之覆晶接合製程,其 中該些預銲塊之材質係為錫鉛合金,且該些預銲塊之錫鉛10550twf.ptd Page 15 1228805 6. The scope of the patent application (d) The solder bumps are re-soldered, so that the bumps are respectively bonded to one of the corresponding bonding pads, and the flux films are removed separately. One of the oxide layers corresponding to it. I 0. According to the flip-chip bonding process described in item 9 of the scope of patent application, at step (a), the partially removed oxide layers are located at one end of the bumps away from the wafer. II. The flip-chip bonding process according to item 9 of the scope of the patent application, wherein the material of the bumps is a tin-lead alloy. 12. The flip-chip bonding process as described in item 11 of the scope of patent application, wherein the tin-lead ratio of these bumps is one of 5: 9 5 and 6 3: 3 7. 13. The flip-chip bonding process described in item 9 of the scope of patent application, in step (a), includes forming the flux films by attaching a flux. 14. The flip-chip bonding process as described in item 9 of the scope of patent application, at step (b), includes removing the oxide layers locally by grinding. 1 5. The flip-chip bonding process as described in item 9 of the scope of patent application, wherein the substrate further has a plurality of pre-soldering blocks, which are respectively connected to one of the bonding pads corresponding to them, and in step (c) At this time, the bumps are indirectly in contact with one of the corresponding bonding pads respectively through one of the corresponding pre-soldering blocks, and at step (d), the bumps are It is respectively joined to one of the corresponding pre-solder blocks. 16. The flip-chip bonding process described in item 15 of the scope of the patent application, wherein the material of the pre-solder blocks is tin-lead alloy, and the tin-lead of the pre-solder blocks 10550twf.ptd 第16頁 122880510550twf.ptd Page 16 1228805 10550twf.ptd 第17頁10550twf.ptd Page 17
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