TWI228763B - Method of fabricating gate structures having a high-k gate dielectric layer - Google Patents

Abstract

A method of fabricating gate structures having a high-k dielectric layer. A high-k dielectric layer is formed overlying a semiconductor substrate followed by formation of a patterned conductive layer thereon. The high-k gate dielectric layer is etched using a mixture of insert gas, fluoride gas, and chloride gas to form a gate stack structure. After etching the high-k gate dielectric layer, a chemical wet cleaning process is further carried out to remove the organic/inorganic high-k polymer residuals.

Description

1228763

FIELD OF THE INVENTION The present invention relates to a gate structure and a manufacturing method thereof, and more particularly, to a gate structure having a high dielectric constant dielectric layer and a method for manufacturing the same. Important material, that is, the gate electrode on the metal conductive substrate, and the electrical and electrode. The concentration of oxygen formed by a typical dielectric method requires the accumulation degree of fossils to be fine when the gate interlayer is thin. As a result, the current also increases, although the leakage current in the gate layer of the device is a dielectric layer. For the development of miniaturization and effect transistor (Metal-Oxide-Semiconductor

Transistor (MOSFET) is a basic electronic component in the field of integrated circuit technology. It consists of three basic material layers, dielectric layers and semiconductor layers in a semiconductor structure. In addition, it also includes two semiconductor regions located opposite the two semiconductor substrates of the gate structure. The source and drain layers are called SiO2, the dielectric constant is 3.9, and the gate is made of thermal / oxidized silicon. Polar dielectric layer. However, with the advancement of semiconductor technology, the size of components has continued to shrink. If the electrical layer is still used, there will be many adverse effects. For example, when the gate is oxidized to a fixed operating voltage, its electric field strength will increase. The method of tunneling (tunne 1 in ng) generates leaks and thus limits the shrinkage of components. The transistor structure has been widely used for a long time, but when the pole length is less than 1001, if Si% is used as the gate dielectric, it will increase rapidly, so silicon oxide is no longer suitable as a gate for M0S transistors. Technology can meet the needs of component size reduction to increase component accumulation, of which-5 ways to solve

Page 6 1228763 1 1,1-V. Description of Invention (2) II. :: 1 Ϊ * number of dielectric materials instead of the gate dielectric m m composed of Si〇2 increase the dielectric constant, can use low leakage current and thickness than 5, "Check materials to replace the thinner si. 2, and has considerable electrical properties. In general, using a high dielectric constant material as the gate dielectric layer will encounter the remaining problems in the shape. If the wet etching method is used alone == wide: etching Solution's relative to dry and wet etching will produce substrate

Strate recess or substrate damage Πί 1 The above-mentioned substrate recess will affect the electrical performance, and the substrate damage will cause problems in the formation of metal lithotripsy (s 1 1 1 c 1 de). In addition, the method of fabricating a gate structure with a high dielectric constant dielectric layer is known in combination with dry and wet etching methods, and can avoid problems such as substrate recess or substrate damage. However, the disadvantages of the combination of the dry and wet etching processes mentioned above are that the wet etching process causes erosion of the oxide in the shallow trench isolation region (STI), and the manufacturing cost increases due to more complicated processes and the use of an etching solution. Figures 1 to 4 are schematic cross-sectional views showing a conventional process for fabricating a gate structure with a high dielectric constant dielectric layer by combining dry and wet etching methods. Please refer to FIG. 1 'on a semiconductor substrate 10, such as a silicon substrate, a dielectric layer 20 having a high dielectric constant and a gate conductive layer 30 are sequentially formed on the dielectric layer 20. Next, as shown in FIG. 2, a patterned mask (not shown) is formed on the gate conductive layer 30, and the patterned mask is used to etch the conductive layer 30 and a portion having a high dielectric constant by dry etching. Constant dielectric layer 20. Next, referring to FIG. 3, the remaining dielectric layer 20 is etched by a wet etching method to form a gate structure 40 as shown in FIG. However, at 0503-9978tw (nl); tsme2003-0065; Jamngwo.ptd page 7 1228763 V. Description of the invention (3) When the wet etching step is performed, the wet etching process will trigger the gate: the trench isolation region (STl) The i-oxide is invaded with money, and the manufacturing cost is increased due to the more complicated process and the use of the food carving solution. Figures 5 and 6 are schematic cross-sectional views showing the manufacturing process of a gate structure with a high dielectric constant dielectric layer formed by a conventional dry etching method. Please consider ^ 5 1 Figure 'Because the conductive layer 30, the dielectric layer 20, and the semiconductor substrate 10 have a small difference in the etching selectivity ratio, the substrate will be over-etched and the substrate recessed. ) 50. 10 Please refer to Figure 6. Another problem caused by dry etching is substrate damage. Surface damage caused by high-density plasma bombarding semiconductor substrates 60 will cause subsequent formation of metal silicidation. The problem of poor structure caused by material. Furthermore, for organic or inorganic polymers that remain after the step of etching a dielectric layer with a high dielectric constant, there is traditionally no effective removal step. At the same time, gate polycrystalline silicon and shallow trench isolation regions can be avoided (STI) oxide is invaded by I insects. U.S. Patent No. 6 51 1 8 7 discloses that A 12 03 is used as a gate oxide layer, and an interfacial dielectric layer is formed between the gate oxide layer and a semiconductor substrate to form a gate structure. The remaining engraving steps are traditional dry money engraving steps, such as reactive ion money engraving, plasma engraving, ion, beam etching, and laser stripping. U.S. Patent No. 6 5 1 8 7 2 discloses a low-pressure, high-density helical resonator (low-pressure, high-density helical resonator) using a halogen gas plasma to etch high dielectric constant materials. U.S. Patent No. 65 03845 discloses high-density plasma etching of TaN layers to

1228763 1 ^: Moon ⑷ formation-gate structure. However, the conventional techniques disclosed above still cause the problems described above when etching the gate dielectric layer. U.S. Patent Nos. 653 1 368, 652 8858, 6504042, and 6495473 are all due to the difficulty of re-etching high dielectric constant materials. 'All are formed first |' Subsequently, the metal layer is partially Oxidation or nitridation to form a high dielectric constant material. The goal is to avoid difficult metal oxide etching processes. Wu Guo Patent No. 645 1 647 discloses a method of forming a gate structure having a high dielectric constant dielectric layer by a two-stage dry etching method. It is first carved with a high-density dielectric layer with a high density, and then uses a low-power plasma to etch unwanted residues of the south-dielectric constant dielectric layer. SUMMARY OF THE INVENTION In view of this, the gate structure of the dielectric layer and the etching method of the present invention have problems such as high dielectric and no substrate damage. Another object of the present invention is the gate structure of the layer and the fabrication thereof for etching inorganic polymers having a high dielectric constant. According to the above purpose, the purpose of the manufacturer of the gate structure of the electric layer is to provide a method for making the gate that the gate of the constant dielectric layer is recessed or the substrate is damaged. The method is to provide a wet dielectric layer. After the step, the invention also provides a method, which includes the following steps: a dry structure with a high dielectric constant and a low power, which can avoid damage (substrate high dielectric constant dielectric electrochemical cleaning, removing the remaining organic or high dielectric) Constant medium: provide a base,

1228763 5. Description of the invention (5) A dielectric layer having a high dielectric constant is formed on the substrate. A patterned gate conductive layer is formed on the dielectric layer. A mixture of a gaseous gas, a fluorine-based gas, and an inert gas is used to etch the dielectric layer having a high dielectric constant to form a gate structure. Furthermore, an interlayer dielectric layer is further included between the substrate and the dielectric layer having a high dielectric constant, preferably a thin oxide layer. Furthermore, a spacer is formed on the sidewall of the patterned gate conductive layer, and the material of the spacer is silicon oxide, silicon nitride, or silicon oxynitride. According to a preferred embodiment of the present invention, the inert gas includes He,

Ne, Xe, or Ar. The fluorine-based gas includes CF4, CHF3, CH2F2, CH3F, or C2HF5. The chlorine-based gas includes BC13. Among them, the mixing ratio of fluorine-based gas: chlorine-based: inert gas is approximately 1: 1 to 5: 2 to 5. According to a preferred embodiment of the present invention, after the step of etching the dielectric layer having a high dielectric constant, a wet chemical cleaning step is further included, wherein the wet chemical cleaning step is removed by etching the high dielectric constant. Organic or inorganic polymers remaining after a constant dielectric layer step. Therefore, the present invention provides a wet chemical cleaning step including an HF solution cleaning, an H20 cleaning, an NΗ40Η / Η2 02 (ΑPM) solution washing, and a 1120 washing step. The present invention provides another wet chemical cleaning step including an HF solution cleaning, an h2o / o3 (di-o3) cleaning, an nh4oh / h2o2 (apm) solution cleaning, and an H2 0 cleaning step. The present invention provides another wet chemical cleaning step including an HF solution cleaning, an h2o cleaning, an nh4oh / h2o2 (apm) solution cleaning, and an h2o cleaning.

0503-9978tw (η 1); tsmc2003-0065; Jamngwo. Ptd page 10 1228763 V. Description of the invention (6) Washing, a H C 1 / H 2 0 2 (Η P Μ) solution washing, and a Η 20 washing step. The present invention provides yet another wet chemical cleaning step including an HF solution cleaning, an h2o / o3 (di-〇3) cleaning, a νη4οη / η2ο2 (αρμ) solution cleaning, a one to zero cleaning, and a HC1 / H2 02 (HPM ) Solution cleaning and 20 cleaning steps. The present invention provides yet another wet chemical cleaning step including a νη4οη / η2ο2 (αρμ) solution cleaning, a Η20 cleaning, a HC1 / H2 02 (HPM) solution cleaning, and an h2 0 cleaning step. According to the above object, the present invention also provides a method for manufacturing a gate structure with a high dielectric constant dielectric layer, including the following steps: providing a semiconductor substrate 'to form a dielectric layer having a high dielectric constant on the semiconductor substrate. A patterned gate conductive layer is formed on the dielectric layer, and the gate conductive layer is defined to form a gate. And using the gate electrode as a mask, the dielectric layer with a high dielectric constant is engraved with a low power to form a gate dielectric layer. According to a preferred embodiment of the present invention, the low power includes the use of a chlorine-based gas, a fluorine-based gas, and an inert gas, θ person -7 / dagger crossing peak. Among them, low-power electric engraving; low-power electric range is 10 ~ 5. —. Use power < π " for pressure, and inert gases include He, Ne, and γ. ^^^ I, CHF3, CHA, CHJ, or CJF5. This gas system includes. Medium 'ι-series gas: the current ratio of chlorine-based unisex gas is about 3 2 ~ 5. 0 · type, which has a high-dielectric wet-chemical cleaning step in the rest, wherein the step of the dielectric layer according to a preferred embodiment of the present invention further includes a step

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= The step is to remove the organic or inorganic polymer remaining after the step of engraving the dielectric layer with a high dielectric constant. Therefore, according to the present invention, the subject '', a wet chemical cleaning step includes an HF solution / month '2' monthly cleaning, -NH4OH / H2 02 (APM) solution cleaning, and an h20 cleaning step. The present invention provides another wet chemical cleaning step including an HF solution cleaning, an H2O / 〇3 (DI- 03) cleaning, an NΗ40Η / Η2 02 (APM) solution washing, and an H2 0 washing step. The present invention provides yet another wet chemical cleaning step including an HF solution cleaning, an H20 cleaning, an nh4〇h / h2o2 (apm) solution cleaning, an H20 cleaning solution, an HC1 / H2 02 (HPM) solution cleaning, and a 4〇 Washing step. The present invention provides yet another wet chemical cleaning step including an HF solution cleaning, an H20 / 03 (DI-〇3) cleaning, an NH4OH / H2O2 (ApM) solution cleaning, a 1120 cleaning, and an HC1 / H2 02 (HPM) solution cleaning and 40 cleaning steps 0 The present invention provides yet another wet chemical cleaning step including an Ν 一 40Η / Η2 02 (ΑPM) solution cleaning, an h20 cleaning, and a hc1 / h2〇2 (hpm) solution. Cleaning and a h2 0 cleaning step. According to the above object, the present invention provides a gate structure having a high dielectric constant dielectric layer, including: a substrate, the substrate being substantially free of recesses or damage caused by ions. A gate dielectric layer having a high dielectric constant is formed on the surface of the substrate. A gate is formed on the surface of the gate dielectric layer. And the gate dielectric layer having a high dielectric constant is used to etch the gate dielectric having a high dielectric constant by a low-power plasma etching method.

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Layer 0 In summary, the main advantage of the present invention is to provide a low-power dry etching method for fabricating a gate structure with a high dielectric constant dielectric layer, which can avoid substrate recess or substrate damage. problem. And after the step of etching the dielectric layer having a high dielectric constant, a wet chemical cleaning step is further included, wherein the wet chemical cleaning step is removed after the step of etching the dielectric layer having a high dielectric constant. Organic or inorganic polymers. The following diagrams and preferred examples are used to explain the implementation example 1 in more detail. Figures 7 to 9 are schematic cross-sectional views of a process with a high dielectric layer structure of the present invention, and are used to Explanation of the present invention: There is a manufacturing method of a gate structure having a dielectric constant of a south dielectric constant. x /, Please refer to FIG. 7. First, a semiconductor substrate 100 is provided. A semiconductor substrate 100 is sequentially formed on the semiconductor substrate 100 with a high dielectric constant Q octadium 200 and a gate conductive layer 3 00. " Electrical layer The above-mentioned dielectric layer 200 having a high dielectric constant refers to a material of dielectric 10, preferably erbium oxide, hafnium oxide, oxidized oxide, " less than alumina, hafnium silicate, or silicic acid zirconium. Formation of the dielectric layer = chemical button, chemical vapor deposition (M0CVD) or atomic layer deposition (AL is 5 and metal is 2 to 40 nm. Thickness range

V. Description of the invention (9) According to a preferred embodiment of the present invention, an interlayer dielectric layer (not shown) is included between the substrate 100 and the dielectric layer 2000 having a dielectric constant. (Illustrated) A thin oxide layer is preferred. The electrical layer 300 is a polycrystalline silicon layer formed by a conventional chemical vapor deposition (CVD) method or a low-pressure CVD (LPCVD) method, and has a thickness in the range of 500 00 2000 A. . In addition, the gate conductive layer 30 () may also be a metal layer, for example, butadiene / TiN, Tiw, TaN, Ta, W, Mo, etc., which are formed by a hafnium plating method or a reactive sputter method. Ni, MoN, and WN. . Referring to FIG. 8 ', a patterned mask (not shown), such as a patterned photoresist layer, is formed on the conductive layer 300, and the conductive layer 300 is etched by a first dry etching. The above-mentioned etching step is a traditional dry etching step, such as reactive ion plasma etching or ion beam etching, preferably a reactive ion etching gas (U ° GF4, GHF3n, Liao or ㈣), lazy lice t Such as He, Ne or Ar) and oxygen% are mixed as an etching gas. Moreover, see FIG. 9A, and etch it with a low-power second dry etching method. Second: Hang the dielectric layer 200 to form a gate structure 4. . . On the J-engraving method, the traditional dry-engraving step 'such as reactive ionization, ionization, or ion beam' is preferably a reactive ion ㈣ ^ with chaotic gas (such as CF4, CHF3 body "U〇bci3 ^ m; One of the preferred embodiments of the present invention, wherein the mixing ratio of the fluorine-based gas: gas radon. Inert rolling body is probably !: Bu 5: 2 ~ 5 milk power range 10 ~ 5 "T0rr, and the use power <1〇 &quot; . Officials used as pressure

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2. Description of the invention 〇〇) In the low-power second dry-remnant method, a high-pass 200 step is performed: ϊ: 上 i :: The remaining organic or inorganic residue after the engraving: the sublayer is called P) Chemicals, subject to erosion during the removal step. ~ Madison Please refer to FIG. 9B. According to one preferred embodiment of the present invention, the fabrication of an open electrode structure with a high dielectric constant dielectric layer is as follows: Two: tfa 02 plasma plasma ashing process. Utilizing the above-mentioned plasmon ashing f extension-the substrate after etching is used for cleaning, meaning engraving; = 25 or more organic or inorganic polymer remaining from the ions. According to a preferred embodiment of the present invention, after the step, the wet-chemical step is further included after the dielectric layer step of the etching constant; to: the wet chemical cleaning step is removed from the charged electrode. Constant: Organic or inorganic polymer 250 remaining after the electrical layer step. 1; here are five methods to choose you # 步骤 方法: # Zuo Guan, explain the above wet chemical cleaning steps: sequentially perform an HF solution cleaning, an NMH / H202um solution cleaning and an M cleaning engraving The dielectric material M ^ * having a high dielectric constant is in an etch polymer 25. . Organic or none remaining after the electric layer step (2) Sequential lambda HF solution cleaning, ΝΗ, ΟΗ ^ Η 02 (ΑΡΜ) ^ ^ „, ^ ^ 2〇 ^ ^ #:? == Electric hanging number Organic &amp; organic polymer 2 5 0 remaining after the dielectric layer step. Ew 4 None

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(3) sequentially perform a HF solution cleaning, _H〇, NH40H ^ H2 02 (APM) .: iHCl / H2 02 (HPM): liquid second washing and -h20 cleaning steps, remove the etching with high dielectric As a constant, the organic or inorganic polymer 250 remaining after one step of the electrical layer. (4) sequential application of a HF solution cleaning, -h2o / o3 (di-o3) cleaning, an n, oh / h2o2 (apm) solution cleaning, a M cleaning, a HCl / H2O2 (HpM) (5 ) Sequentially performing a nh4oh / h2o2 (apm) solution cleaning, a H2O cleaning, a HC1 / H2O2 (HPM) solution cleaning and a H2O cleaning step in order to remove the dielectric layer with a high dielectric constant in etching The organic or inorganic polymer 250 remaining after the step. &gt; Valley cleaning and an H2O cleaning step to remove the organic or inorganic polymer 250 remaining after the step of etching the dielectric layer having a high dielectric constant. In the above five operation examples, the concentration range of the HF solution is HF 0.05 to 30% by volume. The concentration range of the NH4OH / H2O2 (apm) solution is from NH4OH to 0.05 to 30 volume percent and from 402 to 0.05 to 30 volume percent. The concentration range of the HC1 / H2 02 (HPM) solution is from HC1 to 0.05 to 30% by volume and H2 to 0.05 to 30% by volume. H20 / 〇3 (DI-03) means that the content of O3 in H20 is greater than or equal to 20 ppm. In the above five operation examples, the temperature range of each wet chemical cleaning step is between 15 ° C and 90 ° C. The time range of the washing step is between 10 seconds and 5 minutes. In the above five operation examples, each of the wet chemical cleaning steps also includes a physical megasonic shock, which increases the efficiency of removing residual organic or inorganic polymers 2 50.

0503 -99781 w (η1); t smc2003-0065; J amngwo.ptd Page 16 1228763 V. Description of the invention (12) Example 2 Figures 10 to 14 show the dielectric layer in combination with the interlayer electrode The structure of the structure = Yes: the dielectric constant illustrates another aspect of the present invention—the preferred embodiment is not intended. Please refer to FIG. 10 for details. It also hurts on the semiconductor substrate 100: a dagger body substrate. 100, such as silicon substrate, and conductive layer 300. The traditional j has the same meaning; the dielectric layer 200 with a constant electric constant is formed by a gate-conducting process, and the conductive layer 300 is defined by the electric charge, as shown in the figure. The material of the above-mentioned dielectric layer 10 having a high dielectric constant is preferably hafnium oxide, hafnium oxide, titanium oxide: aluminum oxide, hafnium silicate, or silicic acid button, m, ^, I layer The formation method is organic metallization milk phase deposition method (MOCVD) or atomic reed deposition, this r ΔΤ ηλ, and the genus is 2 to 4G nm. U atomic layer deposition (ALD), a preferred embodiment of the thickness range You Guming, is between the substrate 100 and the dielectric layer 200 with ΓΛ ^ Λ and further includes an interlayer dielectric layer (not shown) ) A thin oxide layer is preferred. The cathodic electrode layer MO is formed by a conventional chemical vapor deposition method (CVD) or a low-pressure chemical emulsion deposition method (LPCVD) to form a polycrystalline silicon layer with a thickness ranging from 0 to 2000 A. In addition, the gate conductive layer 300 can also be a metal layer, such as formed by a sputtering method or a reactive sputtering method.

Ti / TiN, TiW, TaN, Ta, W, Mo, Ni, MoN / and WN. The gate conductive layer 3 0 is defined by using a lithography process and a conventional dry contact step, such as reactive ion etching, plasma etching, or ion beam etching.

0503 -99781w (η1); t smc2003-0065; J amngwo.ptd page 17 1228763 V. Description of the invention (13) Interrogation layer 3. 〇, the preferred one is the reactive ion residue. If the above metal layer is used as the gate electrode, “20 ° is made of :: two gas ^: zi ㈣ ′, the remaining gas system uses HBr, cl2 and 02: =; flavor conductive layer Dielectric layer 2 with 3 °° and high dielectric constant. There is also the dielectric side as: engraved ... Dielectric ΐϊ 丄 iill12 'to form a dielectric layer 400 covering the high-K ΛΛ gate conductive Layer 300. The above dielectric layer _ is based on ^ fossil κ fossil or oxynitride, it can also be a group of two materials and then 'please refer to Figure 13 to non-tower &amp; formation-gap wall 4 The gap wall is 400 °, the dielectric layer is 4 °, and the degree is 500, which is called GGA. The visibility of _ ″ _ is _, GA, and the thickness is a cover: see = 4Α 图 LOW'Λ 300 layer and gap frequency Ma'mao Qin 'also uses a low-power dry surname to engrave method layer 2 {) (). Touching / removing the surface with the high dielectric constant dielectric of the above-mentioned low-power dry money engraving method is the traditional age; the sticky f will do 々 々 7 7 7 + L ♦ worming steps' such as reactive ion engraving, Plasma etching or ion beam etching. Etching is based on gaseous gases (such as CF4, CHF, ΓΗ \ 佳 者 as reactive ion gaseous gases (such as BC13)), and inert gases (two 22, ^ 31? Or 〇), money carved gas. According to one of the present invention is better; Ne4Ar) mixed as a body: gas system: the mixing ratio of the inert gas is large Π formula, where the system gas αxi 1 :: 1 ~ 5: 2 ~ 5, use

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V. Description of the invention (14) Working force range 10 ~ 50 mTorr, and using power &lt; i〇〇 ^ In the second low-power dry, 1 丨, 1 μ female · 丨 Dielectric layer 200 Newton A small dielectric material with a high dielectric constant will be removed from the coin, and after that, there will be organic or inorganic polymers left after etching. Silicon Λ: there is no effective removal step, and the gate electrode can be avoided. The oxide 'sti' in the isolation zone (sti) is extremely formed during the removal step; the invented method on the 4BΛ 'side is called electropolymerization L = including-〇2 the electropolymerization ashing process 1 using the above ○ to remove the second The substrate after the engraving is used for cleaning 2,250. &quot; Organic or inorganic polymer constants remaining after the generated steps are widely engraved with high dielectrics, and the wet chemical cleaning step is to remove the organic or inorganic high-dielectric steps left there: A kind of operation example 'illustrates that the above wet chemical cleaning step (1) sequentially performs an HF solution cleaning,-NH4OH / H2 02 (APM) solution cleaning, H2 () / monthly cleaning, and the second dielectric with high dielectric constant. And cattle-; 0 washing step 'removed in Yuji polymer 250. The organic or non-residue (2) remaining after the electricity 4 step is sequentially performed an F solution slag, a soil nh4oh / h2o2 (apm) solution cleaning, and &quot; ^ 2〇 / 〇3 (D 卜 〇3) cleaning, a moment The Dielectric Wafer with a high dielectric constant; a cleaning step to remove organic or non-residual residues remaining after the remaining 7 layer steps

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Machine polymer 250. (3) sequentially perform a HF solution cleaning, -h a f ^ 40H ^ H2 02 UPM) solution cleaning, a H2O cleaning, a Hci / H2O2 (HpM) Γ solution 2 3 and a 1 0 cleaning steps. Except for the organic or inorganic polymer that remains after the 71 layer process with high dielectric constant.实施 Sequentially perform a HF solution cleaning, a νη4 · Η2202 (αρμ) solution cleaning, a M cleaning Λη (: ι / η2〇2 (ηρμ) / mix solution m washing, and a cleaning step, remove the The dielectric layer having a high dielectric constant is etched, and then the remaining organic or inorganic polymer is 25. (5) Sequentially Λ application of νη4〇η / Η2 02 (ΑPM) solution cleaning, η2〇 clean_ Wash the HCl / H2O2 (HPM) solution and the __Η20 cleaning step to remove ΐ = it remaining organic or inorganic molecules after the dielectric layer step with a high dielectric constant 250. 〇η 二 ii In this operation example, the concentration range of the HF solution is hf 〇 human 05 to 30 volume percent. NH4 0 h / h 2 0 2 (apm containing NH 4 0 H 0 05 to 30 volume percent and dry system ⑽ ... Concentration range includes HC &quot;. = Volume percentage and 0.05 to 30 volume percentage. H2o / o3 (d 〇3) is the amount of 〇3 in M is greater than or equal to 2〇 Qing. R 你 ΐ ΐ ί i In the example, the value of each wet chemical cleaning step is equal to between 15 and 9 (t). The cleaning step is between 10 seconds and 5 minutes. Based on the above-mentioned five kinds of four working examples Φ J &. Ή -4- '/ 1 + ^, the door # $ Α In the present column, the mother and a wet chemical cleaning step are too private, and a physical stem is also included. Giant Super Theta Wave ("Jiu &amp; 3011 丨 (:) Zhenying Zuo

1228763 V. Description of the invention (16) Use ’to increase the efficiency of removing the remaining organic or inorganic polymer 250. As shown in FIG. 14, the present invention provides a gate structure 'having a high dielectric constant dielectric layer, including: a semiconductor substrate 100 that is substantially free of recesses or damage caused by ions. A high-dielectric constant dielectric layer 200 is formed on the surface of the semiconductor substrate 100. A gate electrode 300 is formed on the surface of the gate dielectric layer 200. And a spacer 400a is formed on the side wall of the gate 3000. The gate dielectric layer 2000 with a high dielectric constant is a gate dielectric layer with a high dielectric constant etched by a low-power dry-etching method. 6 Features and effects of the present case Features and effects of the present invention Making a dielectric recess temple problem with a high dielectric constant. In addition, the method includes a wet chemical cleaning step in addition to etching the high dielectric constant or inorganic polymer. Therefore, the low leakage current S i 02 results in a high dielectric constant electrical property. High dielectric constant (thickness), but with high oxide thickness (EOT), Φ is to provide a gate structure of low-power dry etching layer, which can avoid the damage of the base or substrate (sub coffee tedama; ^ 介 介The dielectric constant of the dielectric layer step is even more * wherein the wet chemical cleaning step is a shift of the dielectric layer ^ The remaining thinner layer after the step has a c 'equivalent equivalent oxide. ;; Thickness (PhySiCal 3 ㈢ ^^ degrees (equivalent

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0503-9978tw (nl); tsmc2003-0065; Janrngwo.ptd page 22 1228763_ Brief description of the diagram Figure 4 shows the conventional combination of dry and wet etching to produce a gate structure with a high dielectric constant dielectric layer Figures 5 and 6 are schematic cross-sectional views showing the process of a gate structure with a dielectric constant dielectric layer formed by a conventional dry etching method. The first step in Figure &gt; ^ Figure 1 shows the substrate recess. Figure 6 shows problems such as substrate damage; Figures 7, 8, 9A, and 9B are schematic cross-sectional views showing a process of a gate structure with a high dielectric constant dielectric layer according to the first embodiment of the present invention; And FIGS. 10 to 13 and FIGS. 14A and 14B are schematic cross-sectional views illustrating a manufacturing process of a gate structure having a high dielectric constant dielectric layer combined with a spacer wall according to a second embodiment of the present invention. Explanation of symbols Conventions (Figures 1 to 6) 10 to semiconductor substrate; 20 to high dielectric constant dielectric layer; 30 to gate conductive layer; 40 to gate structure; 50 to substrate recess ) 60 ~ substrate damage Part of this case (Figures 7 to 14) 100 ~ semiconductor substrate; 200 ~ high dielectric constant dielectric layer

0503-9978tw (nl); tsmc2003-0065; Jamngwo.ptd Page 23 1228763 Brief description of the diagram 2 50 ~ Residual organic or inorganic polymer; 3 0 ~ Gate conductive layer; 4 0 ~ Dielectric layer 4 0 0 a ~ gap wall; 5 0 0 ~ gate structure. ί ΙΙΙΙ 0503-9978tw (nl); tsmc2003-0065; Jamngwo.ptd Page 24

Claims (1)

1228763 VI. Scope of patent application 1. A method for manufacturing a gate structure with a high dielectric constant dielectric layer, comprising the following steps: providing a substrate on which a dielectric layer having a high dielectric constant is formed; forming A patterned gate conductive layer is formed on the dielectric layer; and a mixture of a chlorine-based gas, a fluorine-based gas, and an inert gas is selected to etch the dielectric layer having a high dielectric constant to form a gate structure. 2. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 1 of the scope of the patent application, further comprising a layer between the substrate and the dielectric layer with high dielectric constant. Dielectric layer. 3. The method for manufacturing a gate structure having a high dielectric constant dielectric layer as described in the second item of the patent application, wherein the interlayer dielectric layer is a thin oxide layer 4. As described in the first item of the patent application A method for manufacturing a gate structure having a high-k dielectric layer, wherein the material of the gate conductive layer includes a polycrystalline silicon layer. 5. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 1 of the scope of the patent application, wherein the material of the gate conductive layer further includes TiN, TiW, TaN, Ta, W, Mo, Ni MoN or WN ° 6. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 1 of the patent application scope, further comprising forming a gap wall on the sidewall of the patterned gate conductive layer. 7. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 6 of the scope of patent application, wherein the material of the spacer is oxidized 0503-9978tw (nl); tsmc2003-0065; Jamngwo.ptd Page 25 1228763 6. Scope of patent application Silicon, silicon nitride, or silicon oxynitride. 8. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 1 of the scope of patent application, wherein the dielectric constant of the dielectric layer is greater than 10 ° 9. The method for manufacturing a gate structure with a high dielectric constant dielectric layer is described, wherein the material of the dielectric layer is oxide junction, oxide, titanium oxide, oxide group, oxide oxide, tritium sulphate or zirconium sulphate. 10. The method for manufacturing a gate structure having a high dielectric constant dielectric layer as described in item 1 of the scope of the patent application, wherein the dielectric layer is formed by a chemical metal chemical vapor deposition method (M 0 CVD) or atomic layer deposition (ALD). 11. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 1 of the scope of patent application, wherein the inert gas system He, Ne, Xe or Ar 〇1. The method for manufacturing a gate structure having a high dielectric constant dielectric layer according to the item, wherein the chlorine-based gas system BC 13 is used. 1 3. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 1 of the scope of the patent application, wherein the fluorine-based gas system CF4, CHF3, CH2F2, CH3F 4C2HF5. 1 4. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 1 of the scope of the patent application, wherein the mixing ratio of the fluorine-based gas: gas-based: inert gas is approximately 1: 1 ~ 5: 2 ~ 5. 1 5. The method for manufacturing a gate structure having a high dielectric constant dielectric layer as described in item 1 of the scope of the patent application, wherein the high dielectric constant dielectric layer is etched. 0503-9978tw (nl); tsmc2003-0065; Jamngwo.ptd Page 26 1228763 6. Scope of patent application The dielectric layer step is a low-power plasma etching method. 16 · The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 5 of the scope of the patent application, wherein the low-power plasma etching method uses a power &lt; 1000 watts. 17 · The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 5 of the patent application scope, wherein the low-power plasma etching method uses a pressure range of 10 to 50 mTori '. '1 8 · The method for manufacturing a gate structure having a high dielectric constant dielectric layer as described in item 1 of the scope of the patent application, wherein after the step of etching the dielectric layer having a high dielectric constant, an &amp; Plasma ashing process. 19 · The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 1 of the scope of patent application, further comprising a wet chemistry after the step of etching the dielectric layer with high dielectric constant. A cleaning step, wherein the wet chemical cleaning step is to remove the organic or inorganic polymer remaining after the step of etching the dielectric layer with a high dielectric constant. 20 · The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 19 of the scope of patent application, wherein the wet chemical cleaning step includes the following steps in order: an HF solution cleaning, a H20 cleaning, N &amp; 0 Η /% 02 (AP M) solution cleaning and 〆h2 0 washing steps. 2 1 · The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 9 of the scope of the patent application, wherein the wet chemical cleaning step includes the following steps in order: a HF solution cleaning, a M / 〇3 (DI—〇3) washing, a NH4OH / H2 02 (APM) solution washing and a 40 washing step. 2 2 · Dielectric material with high dielectric constant as described in item 19 of the scope of patent application 1228763 VI. Method for manufacturing a gate structure of a patented electric layer, wherein the wet chemical cleaning step includes the following steps in sequence:-HF solution cleaning,-H20 cleaning,-nh4oh / h2o2 (apm) solution cleaning,- H20 cleaning, one HC1 / H2 02 (HPM) solution cleaning and one H2 0 cleaning step. 2 3. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 19 of the scope of patent application, wherein the wet chemical cleaning step includes the following steps in order: a HF solution cleaning, a H2 0/03 (DI-03) cleaning, one NΗ40Η / Η2 02 (ΑPM) solution cleaning, one H20 cleaning, one HC1 / H2 02 (HPM) solution cleaning, and one H20 cleaning step. 24. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 19 of the scope of patent application, wherein the wet chemical cleaning step includes the following steps in sequence: a display 4〇11 / 112〇2 (eight? ^ 1) solution cleaning, 40 cleaning, HC1 / H2 02 (HPM) solution cleaning and 1120 cleaning steps. 2 5. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 19 of the scope of the patent application, wherein the wet chemical cleaning step further includes a physical megasonic oscillation . 2 6. —A method for manufacturing a gate structure having a high dielectric constant dielectric layer, comprising the following steps: providing a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the semiconductor substrate; forming a pattern The gate conductive layer is formed on the dielectric layer; and the gate layer is masked, and the high-k dielectric layer is engraved with low-power dry money to form a gate dielectric layer. 27. Dielectric material with high dielectric constant as described in item 26 of the scope of patent application 0503-99781w (η 1); t smc2003-0065; J amngwo.ptd page 28 1228763 VI. Method for manufacturing a gate structure of an electric layer with a patent application, which is between the substrate and the dielectric having a high dielectric constant The interlayers further include an interlayer dielectric layer. 2 8. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 27 of the scope of the patent application, wherein the interlayer dielectric layer is a thin oxygen layer 4 9. The method for manufacturing a gate structure with a high dielectric constant dielectric layer according to item 26, wherein the dielectric constant of the dielectric layer is greater than 10. 30. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 26 of the scope of the patent application, wherein the material of the dielectric layer is oxidized φ, oxidized, titanium oxide, and oxidized group. , Oxidation, Oxidation, or Acidity. 3 1. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 26 of the scope of patent application, wherein the dielectric layer is formed by an organometallic chemical vapor deposition method (M 0 CVD ) Or atomic layer deposition (ALD). 3 2. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 26 of the scope of patent application, wherein the material of the conductive layer includes a polycrystalline silicon layer. 3 3. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 26 of the scope of the patent application, wherein the material of the conductive layer further includes TiN, TiW, TaN, Ta, W, Mo , Ni, MoN or WN ° 3 4. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 26 of the scope of patent application, further comprising forming a side wall of the patterned gate conductive layer with a Gap wall. 0503-99781w (η 1); tsmc2003-0065; Jamngwo.ptd Page 29 1228763 6. Application for patent scope 3 5. The gate structure with high dielectric constant dielectric layer as described in item 34 of the scope of patent application The manufacturing method, wherein the material of the spacer is silicon oxide, silicon nitride, or silicon oxynitride. 3 6. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 26 of the scope of the patent application, wherein the low-power plasma etching method uses a gaseous gas, a fluorine i-type gas, and an inert gas. Mixing of gases. 37. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 36 of the scope of patent application, wherein the inert gas system He, Ne, Xe or Ar 〇3. The method for manufacturing a gate structure with a high dielectric constant dielectric layer according to item 6, wherein the chlorine-based gas system BC 13 is used. 3 9. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 36 of the scope of the patent application, wherein the fluorine-based gas system CF4, CHF3, CH2F2, CH3F or. With. 4 〇. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 36 of the scope of the patent application, wherein the mixing ratio of the fluorine-based gas: chlorine-based: inert gas is approximately 1 ··: 1 to 5: 2 to 5. 4 1. The method for manufacturing a gate structure having a high dielectric constant dielectric layer as described in item 26 of the scope of the patent application, wherein the low-power plasma etching method uses a power of <100 W. 0 4 2. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 26 of the scope of the patent application, wherein the low-power plasma etching method uses a pressure range of 10 to 50 mTorr. 4 3. The dielectric with high dielectric constant as described in item 26 of the scope of patent application 0503-9978tw (nl); tsmc2003-0065; Jamngwo.ptd Page 30 1228763 6. Method for manufacturing a gate structure for a patented electric layer, wherein a plasma ash is further included after the low-power plasma etching.化 process. 4 4. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 26 of the scope of the patent application, further comprising a wet chemistry after the step of etching the dielectric layer with high dielectric constant. The cleaning step, wherein the wet cleaning step is to remove the organic or inorganic polymer remaining after the step of etching the dielectric layer having a high dielectric constant. 4 5. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 44 of the scope of the patent application, wherein the wet chemical cleaning step includes the following steps in order: a HF solution cleaning, a H20 cleaning , A NΗ40Η / Η2 02 (APM) solution cleaning and a 1120 cleaning step. 4 6. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 44 of the scope of the patent application, wherein the wet chemical cleaning step includes the following steps in order: a solution cleaning, a 1 12 0 / 03 (01-03) cleaning, a NΗ40Η / Η2 02 (APM) solution washing, and a H20 washing step. 4 7. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 44 of the scope of patent application, wherein the wet chemical cleaning step includes the following steps in order: a HF solution cleaning, a H20 cleaning , One NΗ40Η / Η2 02 (ΑPM) solution cleaning, one H20 cleaning, one HC1 / H2 02 (HPM) solution cleaning, and one H2 0 cleaning step. 4 8. The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 44 of the scope of the patent application, wherein the wet chemical cleaning step includes the following steps in sequence: a 1 ^ solution cleaning, a 112 0/03 (01-03) cleaning, one NΗ40Η / Η2 02 (ΑPM) solution cleaning, one H20 cleaning, one 0503-9978tw (nl); tsmc2003-0065; Jamngwo.ptd page 31 1228763 6. Application scope of patent H C 1 / Η 〇 2 (Η P Μ) solution cleaning and 〆fj2 〇 cleaning steps. 4 9 · The method for manufacturing a gate structure with a high dielectric constant dielectric layer as described in item 4 of the scope of the patent application, wherein the wet chemical cleaning step includes the following steps in sequence:-Ν Η 4 0 H / H2 〇2 (AP Μ), valley cleaning, H 2 0 cleaning, 1 11 (: 1/112 0 2 ([1 1 10 solution cleaning and 1 2 0 cleaning steps. 5 0 as the scope of patent application 44th The method for manufacturing a gate structure with a high dielectric constant dielectric layer according to the item, wherein the wet chemical cleaning step further includes a physical Megasonic oscillation effect. 5 1 ·-A species having a high The gate structure of the dielectric constant dielectric layer includes: a substrate, which is substantially free of recesses or dams caused by ions; a gate dielectric layer having a high dielectric constant is formed on the side Substrate surface; a gate formed on the surface of the gate dielectric layer, and wherein the gate dielectric layer having a high dielectric constant is etched by a low-power plasma etching method to the electrode having the high dielectric constant Dielectric layer 52. As described in item 51 of the scope of patent application, Gate structure of a dielectric constant dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than 10 ° 53. The gate structure having a dielectric constant beta dielectric layer as described in item 51 of the scope of patent application In #, the material of the gate dielectric layer: 2 hammers, milk cutting capsules, or silicates. Chemical compounds, titanium oxide, tantalum oxide, aluminum oxide, and stone ^ ^ Ganba a soil 〆 2 high Dielectric constant 5 4. As described in item 51 of the scope of application for patent, Qiyi Yi pole plaque 'an endless area, the gate structure of the electrical layer, where the substrate has you and somewhere in between Passage area. 0503-99781w (η1); tsmc2003-0065; Jamngwo.ptd Page 32 1228763 6. Application for patent scope 5 5. The gate structure with high dielectric constant dielectric layer as described in item 51 of the scope of patent application, The material of the gate includes a polycrystalline silicon layer. 5 6. The gate structure with a high dielectric constant dielectric layer as described in item 51 of the scope of patent application, wherein the material of the gate electrode further includes T i N, T i W, TaN, Ta, W, Mo , Ni, MoN or WN ° 5 7. The gate structure with a high dielectric constant dielectric layer as described in item 51 of the patent application scope, wherein a side wall of the gate has a gap wall. 5 8. The gate structure with a high dielectric constant dielectric layer as described in item 57 of the scope of the patent application, wherein the material of the spacer is silicon oxide, nitride nitride, or oxynitride. 0503-9978tw (nl); tsmc2003-0065; Jamngwo.ptd page 33