TWI228302B - Composite stack package - Google Patents
Composite stack package Download PDFInfo
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- TWI228302B TWI228302B TW92123842A TW92123842A TWI228302B TW I228302 B TWI228302 B TW I228302B TW 92123842 A TW92123842 A TW 92123842A TW 92123842 A TW92123842 A TW 92123842A TW I228302 B TWI228302 B TW I228302B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
1228302 五、發明說明(1) 【發明所屬之技術領域] 本發明是有關於一種複合式堆疊封裝件,且特別是有 關於一種晶粒堆疊的封裝結構。 【先前技術】 請參照第5圖,其所繪示乃傳統之封裝件之側視圖。 傳統封裝件5 0 0係包括有一互連式基板5〇6、一晶粒(Die) 502、一散熱片(Heat Sink) 5 04、一膠體(Molding1228302 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a composite stacked package, and more particularly to a die stack packaging structure. [Prior art] Please refer to FIG. 5, which shows a side view of a conventional package. The conventional package 500 includes an interconnect substrate 506, a die 502, a heat sink 5 04, and a gel (Molding).
Compound)51 2以及多個錫球514。互連式基板506上具有一 508,用以容置晶粒5〇2。晶粒502係透過多條金線5 10與互 連式基板5 0 6電性連接。膠體5 1 2係用以包覆晶粒5 〇 2盘金 線510。 〆、 傳統之封裝件5 〇 〇的缺點是,在可供配置錫球5丨4的表 面積固定的情況下,互連式基板5 0 6上的錫球(s〇lder B a 11 ) 5 1 4數目受到侷限。 由於晶粒的功能日益強大,使得對封裝件之輸入/輸 ^(Inpiit/Oiitput, I/O)密度需求有日漸增加的趨勢。同 時,封裝件本身的尺寸卻有微小化趨勢。如何增加封裝件 之I/O密度,縮小封裝件之尺寸,減少膠體的曰产,乃是 現今業界所致力之目標。 又 【發明内容】 方有鑑於此,本發明的主要目的就是在提供一種複合式 堆疊封裝件,此封裝件能於不增加封裝件之整體厚度的條Compound) 51 2 and a plurality of solder balls 514. The interconnected substrate 506 has a 508 for accommodating the die 502. The die 502 is electrically connected to the interconnection substrate 506 through a plurality of gold wires 510. The colloid 5 1 2 is used to coat the 502 disks of gold wire 510. 〆 The disadvantage of the traditional package 500 is that the solder ball (solder B a 11) 5 1 on the interconnected substrate 5 06 is fixed under the condition that the surface area available for the solder ball 5 4 is fixed. The number of 4 is limited. As the functions of the die become more and more powerful, the input / output (I / O) density requirements for the package have a growing trend. At the same time, the size of the package itself is trending toward miniaturization. How to increase the I / O density of the package, reduce the size of the package, and reduce the production of colloids is the goal that the industry is committed to today. [Summary of the Invention] In view of this, the main object of the present invention is to provide a composite stacked package, which can be used without increasing the overall thickness of the package.
第5頁 1228302 五、發明說明(2) 件之下,增加I / 〇密度。 根據本發明的目的,提出一種複合式堆疊封裝件,包 括一基板、一第一晶粒 第 晶粒/CSP封裝件以及一封 膠(Encapsulation)。基板上具有一晶穴。第一晶粒係位 於晶穴中並利用多數條金線與基板電性連接。第二晶 粒/CSP封裝件具有多數個凸塊且配置於第一晶粒之上。封 膠係將第一晶粒、第二晶粒/CSP封裝件、及此些金線包覆 其内,但路出該等凸塊。藉由將第二晶粒/CSP封裝件疊置 於第一晶粒上,可以使封裝之單位面積輸出/輸入(1/0)密 度提南。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下: 【實施方式】 實施例一 、請參照第第1圖,其繪示乃本發明第一實施例之複合 式堆疊封裝件之侧視圖。封裝件〗〇 〇包括一基板i 〇 2、一第 一晶粒106、多條金線108、一第二晶粒11()、一封膠112、 及一散熱片120。基板1〇2上具有一晶穴;! 〇4,此晶穴丨04由 上表面102A貫通至下表面ι〇2Β,且晶穴1〇4之深度大於第 一晶粒110之厚度。散熱片12〇藉由一黏著層122配置於此 基板102之下表面1 〇2B上,以加強封裝件的整體散熱效 果〇Page 5 1228302 V. Description of the invention (2) Increase I / 〇 density. According to the purpose of the present invention, a composite stacked package is provided, which includes a substrate, a first die / CSP package, and an encapsulation. There is a cavity on the substrate. The first grain is located in the crystal cavity and is electrically connected to the substrate by using a plurality of gold wires. The second crystal / CSP package has a plurality of bumps and is disposed on the first crystal. The sealant covers the first die, the second die / CSP package, and these gold wires, but the bumps are exited. By stacking the second die / CSP package on the first die, the output / input (1/0) density per unit area of the package can be increased. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, a detailed description is as follows: FIG. 1 is a side view of a composite stacked package according to the first embodiment of the present invention. The package includes a substrate i 02, a first die 106, a plurality of gold wires 108, a second die 11 (), an adhesive 112, and a heat sink 120. There is a crystal cavity on the substrate 102; this cavity is penetrated from the upper surface 102A to the lower surface 102B, and the depth of the cavity 104 is greater than the thickness of the first crystal grain 110. The heat sink 12 is disposed on the lower surface 102B of the substrate 102 through an adhesive layer 122 to enhance the overall heat dissipation effect of the package.
第6頁 1228302 五、發明說明(3) 第一晶粒106具有一第一面10 6A與一第二面106B,第 一晶粒1 0 6係配置於晶穴1 〇 4中,且第一晶粒1 〇 6之第一面 106A藉由第一銀膠層118A貼附於散熱片120上。多條金線 108,係用以將第一晶粒1〇6之第二面1 〇6B與基板102電性 連接。第二晶粒11 〇係配置於第一晶粒丨〇 6之第二面1 〇 6 b 上,且第二晶粒11 〇具有一主動面i丨i,其上具有多個凸塊 (Bump) 1 14。第二晶粒11 〇係利用其上的外露之凸塊114與 其他基板(未繪示)電性連接並進行訊號的傳遞。同樣地, 基板上表面102A上具有多個锡球116,藉由此些锡球116與 其他基板(未繪示)電性連接並傳遞第一晶粒1 〇 6所產生的 訊號。封膠1 1 2係包覆第一晶粒1 〇 6、第二晶粒1 1 〇及多條 金線108,以隔絕外界空氣,達到保護此些精密元件的功 效。 如圖中所示,多個凸塊114部分裸露於封膠層112之 上,且此些凸塊11 4頂端與基板1 〇2上之多個錫球11 6頂端 約位於同一條水平面ΙΑ-1A,上。 茲將第一實施例之封裝件的製造步驟簡述如下。 請參照第2A至2C圖,其繪示乃依照本發明第一實施例 之複合式堆疊封裝件的製造流程圖。首先,藉由第一銀膠 層118A將第一晶粒1〇6之第一面106A黏附於散熱片120上且 位於晶穴1 0 4之中。接著,進行打線,使金線丨〇 8電性連接 第一晶粒1 0 6與基板1 〇 2。 之後,如第2B圖所示,藉由一第二銀膠層Π8Β,將第 一晶粒110堆疊於第一晶粒的第二面1〇⑽上,並形成多Page 6 1228302 V. Description of the invention (3) The first crystal grain 106 has a first surface 106A and a second surface 106B. The first crystal grain 106 is arranged in the crystal cavity 104, and The first surface 106A of the die 106 is attached to the heat sink 120 through the first silver glue layer 118A. A plurality of gold wires 108 are used to electrically connect the second surface 106B of the first die 106 to the substrate 102. The second die 11 〇 is arranged on the second face 1 06 b of the first die 1 06, and the second die 11 0 has an active face i 1 and a plurality of bumps (Bump ) 1 14. The second die 110 is electrically connected to other substrates (not shown) by using the exposed bumps 114 thereon to transmit signals. Similarly, there are a plurality of solder balls 116 on the upper surface 102A of the substrate, through which the solder balls 116 are electrically connected to other substrates (not shown) and transmit signals generated by the first die 106. The sealant 1 12 covers the first die 106, the second die 110, and a plurality of gold wires 108 to isolate the outside air and protect the precision components. As shown in the figure, the plurality of bumps 114 are partially exposed on the sealant layer 112, and the tops of the bumps 11 4 and the tops of the plurality of solder balls 11 6 on the substrate 102 are located on the same horizontal plane ΙΑ- 1A, up. The manufacturing steps of the package of the first embodiment are briefly described below. Please refer to FIGS. 2A to 2C, which show a manufacturing flow chart of the composite stacked package according to the first embodiment of the present invention. First, the first surface 106A of the first die 106 is adhered to the heat sink 120 through the first silver glue layer 118A and is located in the crystal cavity 104. Next, wire bonding is performed to electrically connect the gold wire 108 to the first die 106 and the substrate 102. After that, as shown in FIG. 2B, the first die 110 is stacked on the second side 10⑽ of the first die through a second silver glue layer Π8B, and a plurality of
第7頁 1228302 五、發明說明(4) 個凸塊1 1 4於第二晶片11 0之主動面1 11上。 接著,如第2C圖所示,進行灌膠以形成封膠丨丨2,封 膠係覆蓋第一晶粒1 〇 6、第二晶粒11 〇及金線1 〇 8。其中, 第二晶粒11 0之凸塊11 4係部分裸露於封膠1丨2之外。然 後,形成多個錫球116於基板上表面ι〇2Α上。 本發明之第一實施例之複合式堆疊封裝件藉由具多個 凸塊11 4之晶粒1 1 0配合連接金線1 0 8之晶粒1 0 6,可有效利 用第一晶粒1 0 6上方之空間。封裝件1 〇 〇之整體I / 〇密度得 以提高。Page 7 1228302 V. Description of the invention (4) The bumps 1 1 4 are on the active surface 1 11 of the second wafer 110. Next, as shown in FIG. 2C, a potting is performed to form a sealant. The sealant covers the first crystal grain 106, the second crystal grain 110, and the gold wire 108. Among them, the bumps 11 4 of the second die 110 are partially exposed outside the sealant 1 丨 2. Then, a plurality of solder balls 116 are formed on the upper surface of the substrate 102A. The composite stacked package of the first embodiment of the present invention can effectively utilize the first die 1 by using a die 1 1 0 having a plurality of bumps 11 4 and a die 1 0 6 connected to a gold wire 108. 0 above the space. The overall I / O density of the package 1000 has been improved.
實施例二 請參照第3 A圖,其繪示乃依照本發明第二實施例之複 合式堆疊封裝件的側視圖。封裝件3 0 0包括一基板3 0 2、一 第一晶粒3 0 6、多條金線3 0 8、一第二晶粒31 0、一封膠 312、及一散熱片320。基板3 02有一晶穴304、一上表面 30 2A、以及一下表面302 B。散熱片320藉由一黏著層324Embodiment 2 Please refer to FIG. 3A, which shows a side view of a composite stacked package according to a second embodiment of the present invention. The package 300 includes a substrate 300, a first die 306, a plurality of gold wires 308, a second die 308, an adhesive 312, and a heat sink 320. The substrate 302 has a cavity 304, an upper surface 302A, and a lower surface 302B. The heat sink 320 has an adhesive layer 324
配置於此基板30 2之整個下表面1 02B上。第二晶粒3 10之主 動面31 1上具有多數凸塊314,且此第二晶粒310同樣堆疊 於第一晶粒3 06上。不同於第一實施例的是,此第二實施 例之基板上表面30 2A上多了攔壩322的設置,此攔壩32 0於 晶穴3 0 4外圍圍成一檔牆,使得封膠3 1 2塗佈範圍被限制於 此攔壩322之内,且覆蓋住第一晶粒306、第二晶粒310及 金線3 0 8。相較於第一實施例,金線高度可以打得更低, 以致於膠體高度較低並使凸塊全部外露。如圖中所示,多 1228302______ 五、發明說明(5) 數凸塊3 14完全裸露於封膠層312之上,且此些凸塊31 4之 頂端與基板3 0 2上多錫球3 1 6之頂端約位於同一水平面3 A 一 3A,上。 請參照第3B圖,其繪示乃第3A圖之攔壩結構上視圖。 攔壩320設置於基板3〇2上,且於晶穴304外圍形成一檔 牆,以作為限制封膠塗佈範圍。此攔壩3 2 0的設置可較精 準控制封膠層3 1 2的範圍與高度。 實施例三It is disposed on the entire lower surface 102B of the substrate 302. The active surface 31 1 of the second die 3 10 has a plurality of bumps 314, and the second die 310 is also stacked on the first die 3 06. The difference from the first embodiment is that a dam 322 is provided on the upper surface 30 2A of the substrate in this second embodiment. The dam 32 0 surrounds a cavity around the cavity 3 0 4 to make a sealant. The coating range of 3 1 2 is limited to the dam 322, and covers the first die 306, the second die 310, and the gold wire 308. Compared with the first embodiment, the height of the gold wire can be lowered, so that the height of the colloid is lower and the bumps are all exposed. As shown in the figure, more than 1228302______ 5. Description of the invention (5) The number of bumps 3 14 are completely exposed on the sealing layer 312, and the tops of these bumps 31 4 and the multi-ball 3 3 on the substrate 3 0 2 The top of 6 is about 3 A to 3A on the same horizontal plane. Please refer to Figure 3B, which shows the top view of the dam structure in Figure 3A. The dam 320 is disposed on the substrate 302, and a barrier wall is formed on the periphery of the cavity 304 to limit the coating range of the sealant. The setting of the dam 3 2 0 can precisely control the range and height of the sealing layer 3 1 2. Example three
請參照第4圖,其繪示乃依照本發明第三實施例的結 構示意圖。封裝件400包括一基板40 2、一第一晶粒406、 多條金線408、一第二晶粒410、一封膠412、及一散熱片 420。散熱片402藉由一黏著層424配置於此基板402上。基 板402有一晶穴4 04,此晶穴404内配置有第一晶粒406,且 第一晶粒406之第一面40 6A藉由一第一銀膠層41 8A貼附於 散熱片420上。一具有有多個凸塊422之一 CSP封裝件(ChipPlease refer to FIG. 4, which shows a schematic diagram of the structure according to the third embodiment of the present invention. The package 400 includes a substrate 40 2, a first die 406, a plurality of gold wires 408, a second die 410, an adhesive 412, and a heat sink 420. The heat sink 402 is disposed on the substrate 402 through an adhesive layer 424. The substrate 402 has a cavity 4 04. A first die 406 is arranged in the cavity 404, and a first surface 40 6A of the first die 406 is attached to the heat sink 420 through a first silver glue layer 4 1 8A. . A CSP package having a plurality of bumps 422 (Chip
Scale Package) 41 0藉由一第二銀膠層4i 8B黏著於第一晶Scale Package) 41 0 is adhered to the first crystal by a second silver glue layer 4i 8B
粒406的下表面4 06 B上。一層封膠412覆蓋住第一晶粒 40 6、CSP封裝件410及金線4 08。CSP封裝件41〇之多個凸塊 422部分外露於封膠層412,且可直接與其他基板作電性連 接並進行訊號的傳遞,不用再透過基板4〇2。基板4〇2上之 多個錫球416可與其他基板作電性連接,以傳遞第一晶粒 本發明上述實施例所揭露之複合式堆疊封裝件,其特 1228302 五、發明說明(6) 色是藉由一具多數凸塊之晶粒或CSP封裳件組合—~咏曰曰 粒’有效利用第一晶粒上方之空間。此外,由於呈多數凸 塊之晶粒或CSP封裝件可直接與其他相耦接的基y'進^行訊 號傳遞,不需要再透過基板’因此不會額外佔用基板空 或增加連接元件,可在不增加原基板尺寸下使封 =曰 體I/O密度得以增加。 便封衣件之整 露如上, 在不脫離 飾,因此 定者為Granule 406 is on the lower surface 4 06 B. A layer of sealant 412 covers the first die 406, the CSP package 410, and the gold wire 408. Parts of the plurality of bumps 422 of the CSP package 41 are exposed on the sealant layer 412, and can be directly connected to other substrates for signal transmission without transmitting through the substrate 402. The plurality of solder balls 416 on the substrate 40 can be electrically connected to other substrates to transfer the first die. The composite stacked package disclosed in the above embodiment of the present invention has the characteristics of 1228302. 5. Description of the invention (6) The color is a combination of a grain with a large number of bumps or a CSP seal --- Yong Yue Yue grain 'effectively uses the space above the first grain. In addition, since most of the bumps of the die or CSP package can be directly transmitted to other bases y 'for signal transmission, there is no need to pass through the substrate', so it will not occupy additional substrate space or increase connection components. The bulk I / O density can be increased without increasing the size of the original substrate. The whole piece of the casual clothes is exposed as above, and it will not leave the decoration, so the
細上所述,雖然本發明已以一較佳實施例揭 然其並非用以限定本發明,任何熟習此技藝者, ί發明之精神和範圍β,當可作各種之更動與潤 發明之保護範圍當視後附之申請專利範圍所界As mentioned above, although the present invention has been disclosed in a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art, ί the spirit and scope β of the invention, can be used for various modifications and protection of the invention The scope should be determined by the scope of the patent application attached
第10頁 1228302 圖式簡單說明 【圖式簡單說明】 第1圖繪示本發明第一實施例的複合式堆疊封裝件之 側視圖。 第2A至2C圖繪示依照本發明第一實施例的複合式堆疊 封裝件之製造流程圖。 第3 A圖繪示依照本發明第二實施例的複合式堆疊封裝 件之側視圖。 第3B圖繪示乃第3A圖之欄壩結構上視圖。 第4圖繪示依照本發明第三實施例的複合式堆疊封裝 件之側視圖。 第5圖繪示乃傳統封裝件之側視圖。 圖式標號說明 100、30 0、40 0、50 0 :封裝件 102 > 30 2 > 40 2 :基板 102A、302A :基板上表面 102B、3 02B :基板下表面 104、30 4、40 4、510 ··晶穴 106、30 6、40 6 :第一晶粒 108、30 8 ' 40 8、510 ··金線 10 6A、4 06A ··第一晶粒之第一面 10 6B、4 06B :第一晶粒之第二面 11 0、31 0、41 0 :第二晶粒 111、31 1、41 1 :主動面Page 10 1228302 Brief description of the drawings [Simplified description of the drawings] FIG. 1 shows a side view of the composite stacked package according to the first embodiment of the present invention. Figures 2A to 2C show a manufacturing flow chart of the composite stacked package according to the first embodiment of the present invention. FIG. 3A illustrates a side view of a composite stacked package according to a second embodiment of the present invention. Figure 3B is a top view of the dam structure of Figure 3A. FIG. 4 is a side view of a composite stacked package according to a third embodiment of the present invention. Figure 5 shows a side view of a conventional package. Explanation of reference numerals 100, 30 0, 40 0, 50 0: package 102 > 30 2 > 40 2: substrate 102A, 302A: substrate upper surface 102B, 3 02B: substrate lower surface 104, 30 4, 40 4 , 510 ·· Crystal cavity 106, 30 6, 40 6: First grain 108, 30 8 '40 8, 510 · Gold wire 10 6A, 4 06A · · First face of first grain 10 6B, 4 06B: the second face of the first grain 11 0, 31 0, 41 0: the second grain 111, 31 1, 41 1: the active face
第11頁 1228302 圖式簡單說明 11 2 ' 3 1 2、41 2 ··封膠 114、314、42 2 :凸塊 116、316、416、514:錫球 118A、418A ··第一銀膠層 118B、418B :第二銀膠層 120、32 0、42 0 ' 50 4 :散熱片 122、32 4、424 :黏著層 3 2 2 :攔壩 410 : CSP封裝件 1A-1 A’、3A-3A’、:水平線 5 0 2 ·晶粒 5 0 6 :互連式基板 5 1 2 :膠體Page 11 1228302 Brief description of the drawings 11 2 '3 1 2, 41 2 · Sealant 114, 314, 42 2: Bump 116, 316, 416, 514: Tin ball 118A, 418A · First silver glue layer 118B, 418B: second silver glue layer 120, 32 0, 42 0 '50 4: heat sink 122, 32 4, 424: adhesive layer 3 2 2: dam 410: CSP package 1A-1 A', 3A- 3A ',: horizontal line 5 0 2 · grain 5 0 6: interconnect substrate 5 1 2: colloid
第12頁Page 12
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TW92123842A TWI228302B (en) | 2003-08-28 | 2003-08-28 | Composite stack package |
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TW92123842A TWI228302B (en) | 2003-08-28 | 2003-08-28 | Composite stack package |
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TWI228302B true TWI228302B (en) | 2005-02-21 |
TW200509328A TW200509328A (en) | 2005-03-01 |
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TW92123842A TWI228302B (en) | 2003-08-28 | 2003-08-28 | Composite stack package |
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