TWI228302B - Composite stack package - Google Patents

Abstract

A composite stack package including a substrate, a first die, a second die, and an encapsulation layer is disclosed. A cavity is configured within the substrate. The first die is disposed in the cavity and is electrically connected to the substrate by a number of gold wires. The second die with a number of bumps is disposed over the first die. The encapsulation layer encapsulates the first die, the second die, and the gold wires and exposes the bumps of the second die. The density of output/input can be increased by means of stacking the second die over the first die.

Description

1228302 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a composite stacked package, and more particularly to a die stack packaging structure. [Prior art] Please refer to FIG. 5, which shows a side view of a conventional package. The conventional package 500 includes an interconnect substrate 506, a die 502, a heat sink 5 04, and a gel (Molding).

Compound) 51 2 and a plurality of solder balls 514. The interconnected substrate 506 has a 508 for accommodating the die 502. The die 502 is electrically connected to the interconnection substrate 506 through a plurality of gold wires 510. The colloid 5 1 2 is used to coat the 502 disks of gold wire 510. 〆 The disadvantage of the traditional package 500 is that the solder ball (solder B a 11) 5 1 on the interconnected substrate 5 06 is fixed under the condition that the surface area available for the solder ball 5 4 is fixed. The number of 4 is limited. As the functions of the die become more and more powerful, the input / output (I / O) density requirements for the package have a growing trend. At the same time, the size of the package itself is trending toward miniaturization. How to increase the I / O density of the package, reduce the size of the package, and reduce the production of colloids is the goal that the industry is committed to today. [Summary of the Invention] In view of this, the main object of the present invention is to provide a composite stacked package, which can be used without increasing the overall thickness of the package.

Page 5 1228302 V. Description of the invention (2) Increase I / 〇 density. According to the purpose of the present invention, a composite stacked package is provided, which includes a substrate, a first die / CSP package, and an encapsulation. There is a cavity on the substrate. The first grain is located in the crystal cavity and is electrically connected to the substrate by using a plurality of gold wires. The second crystal / CSP package has a plurality of bumps and is disposed on the first crystal. The sealant covers the first die, the second die / CSP package, and these gold wires, but the bumps are exited. By stacking the second die / CSP package on the first die, the output / input (1/0) density per unit area of the package can be increased. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, a detailed description is as follows: FIG. 1 is a side view of a composite stacked package according to the first embodiment of the present invention. The package includes a substrate i 02, a first die 106, a plurality of gold wires 108, a second die 11 (), an adhesive 112, and a heat sink 120. There is a crystal cavity on the substrate 102; this cavity is penetrated from the upper surface 102A to the lower surface 102B, and the depth of the cavity 104 is greater than the thickness of the first crystal grain 110. The heat sink 12 is disposed on the lower surface 102B of the substrate 102 through an adhesive layer 122 to enhance the overall heat dissipation effect of the package.

Page 6 1228302 V. Description of the invention (3) The first crystal grain 106 has a first surface 106A and a second surface 106B. The first crystal grain 106 is arranged in the crystal cavity 104, and The first surface 106A of the die 106 is attached to the heat sink 120 through the first silver glue layer 118A. A plurality of gold wires 108 are used to electrically connect the second surface 106B of the first die 106 to the substrate 102. The second die 11 〇 is arranged on the second face 1 06 b of the first die 1 06, and the second die 11 0 has an active face i 1 and a plurality of bumps (Bump ) 1 14. The second die 110 is electrically connected to other substrates (not shown) by using the exposed bumps 114 thereon to transmit signals. Similarly, there are a plurality of solder balls 116 on the upper surface 102A of the substrate, through which the solder balls 116 are electrically connected to other substrates (not shown) and transmit signals generated by the first die 106. The sealant 1 12 covers the first die 106, the second die 110, and a plurality of gold wires 108 to isolate the outside air and protect the precision components. As shown in the figure, the plurality of bumps 114 are partially exposed on the sealant layer 112, and the tops of the bumps 11 4 and the tops of the plurality of solder balls 11 6 on the substrate 102 are located on the same horizontal plane ΙΑ- 1A, up. The manufacturing steps of the package of the first embodiment are briefly described below. Please refer to FIGS. 2A to 2C, which show a manufacturing flow chart of the composite stacked package according to the first embodiment of the present invention. First, the first surface 106A of the first die 106 is adhered to the heat sink 120 through the first silver glue layer 118A and is located in the crystal cavity 104. Next, wire bonding is performed to electrically connect the gold wire 108 to the first die 106 and the substrate 102. After that, as shown in FIG. 2B, the first die 110 is stacked on the second side 10⑽ of the first die through a second silver glue layer Π8B, and a plurality of

Page 7 1228302 V. Description of the invention (4) The bumps 1 1 4 are on the active surface 1 11 of the second wafer 110. Next, as shown in FIG. 2C, a potting is performed to form a sealant. The sealant covers the first crystal grain 106, the second crystal grain 110, and the gold wire 108. Among them, the bumps 11 4 of the second die 110 are partially exposed outside the sealant 1 丨 2. Then, a plurality of solder balls 116 are formed on the upper surface of the substrate 102A. The composite stacked package of the first embodiment of the present invention can effectively utilize the first die 1 by using a die 1 1 0 having a plurality of bumps 11 4 and a die 1 0 6 connected to a gold wire 108. 0 above the space. The overall I / O density of the package 1000 has been improved.

Embodiment 2 Please refer to FIG. 3A, which shows a side view of a composite stacked package according to a second embodiment of the present invention. The package 300 includes a substrate 300, a first die 306, a plurality of gold wires 308, a second die 308, an adhesive 312, and a heat sink 320. The substrate 302 has a cavity 304, an upper surface 302A, and a lower surface 302B. The heat sink 320 has an adhesive layer 324

It is disposed on the entire lower surface 102B of the substrate 302. The active surface 31 1 of the second die 3 10 has a plurality of bumps 314, and the second die 310 is also stacked on the first die 3 06. The difference from the first embodiment is that a dam 322 is provided on the upper surface 30 2A of the substrate in this second embodiment. The dam 32 0 surrounds a cavity around the cavity 3 0 4 to make a sealant. The coating range of 3 1 2 is limited to the dam 322, and covers the first die 306, the second die 310, and the gold wire 308. Compared with the first embodiment, the height of the gold wire can be lowered, so that the height of the colloid is lower and the bumps are all exposed. As shown in the figure, more than 1228302______ 5. Description of the invention (5) The number of bumps 3 14 are completely exposed on the sealing layer 312, and the tops of these bumps 31 4 and the multi-ball 3 3 on the substrate 3 0 2 The top of 6 is about 3 A to 3A on the same horizontal plane. Please refer to Figure 3B, which shows the top view of the dam structure in Figure 3A. The dam 320 is disposed on the substrate 302, and a barrier wall is formed on the periphery of the cavity 304 to limit the coating range of the sealant. The setting of the dam 3 2 0 can precisely control the range and height of the sealing layer 3 1 2. Example three

Please refer to FIG. 4, which shows a schematic diagram of the structure according to the third embodiment of the present invention. The package 400 includes a substrate 40 2, a first die 406, a plurality of gold wires 408, a second die 410, an adhesive 412, and a heat sink 420. The heat sink 402 is disposed on the substrate 402 through an adhesive layer 424. The substrate 402 has a cavity 4 04. A first die 406 is arranged in the cavity 404, and a first surface 40 6A of the first die 406 is attached to the heat sink 420 through a first silver glue layer 4 1 8A. . A CSP package having a plurality of bumps 422 (Chip

Scale Package) 41 0 is adhered to the first crystal by a second silver glue layer 4i 8B

Granule 406 is on the lower surface 4 06 B. A layer of sealant 412 covers the first die 406, the CSP package 410, and the gold wire 408. Parts of the plurality of bumps 422 of the CSP package 41 are exposed on the sealant layer 412, and can be directly connected to other substrates for signal transmission without transmitting through the substrate 402. The plurality of solder balls 416 on the substrate 40 can be electrically connected to other substrates to transfer the first die. The composite stacked package disclosed in the above embodiment of the present invention has the characteristics of 1228302. 5. Description of the invention (6) The color is a combination of a grain with a large number of bumps or a CSP seal --- Yong Yue Yue grain 'effectively uses the space above the first grain. In addition, since most of the bumps of the die or CSP package can be directly transmitted to other bases y 'for signal transmission, there is no need to pass through the substrate', so it will not occupy additional substrate space or increase connection components. The bulk I / O density can be increased without increasing the size of the original substrate. The whole piece of the casual clothes is exposed as above, and it will not leave the decoration, so the

As mentioned above, although the present invention has been disclosed in a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art, ί the spirit and scope β of the invention, can be used for various modifications and protection of the invention The scope should be determined by the scope of the patent application attached

Page 10 1228302 Brief description of the drawings [Simplified description of the drawings] FIG. 1 shows a side view of the composite stacked package according to the first embodiment of the present invention. Figures 2A to 2C show a manufacturing flow chart of the composite stacked package according to the first embodiment of the present invention. FIG. 3A illustrates a side view of a composite stacked package according to a second embodiment of the present invention. Figure 3B is a top view of the dam structure of Figure 3A. FIG. 4 is a side view of a composite stacked package according to a third embodiment of the present invention. Figure 5 shows a side view of a conventional package. Explanation of reference numerals 100, 30 0, 40 0, 50 0: package 102 > 30 2 > 40 2: substrate 102A, 302A: substrate upper surface 102B, 3 02B: substrate lower surface 104, 30 4, 40 4 , 510 ·· Crystal cavity 106, 30 6, 40 6: First grain 108, 30 8 '40 8, 510 · Gold wire 10 6A, 4 06A · · First face of first grain 10 6B, 4 06B: the second face of the first grain 11 0, 31 0, 41 0: the second grain 111, 31 1, 41 1: the active face

Page 11 1228302 Brief description of the drawings 11 2 '3 1 2, 41 2 · Sealant 114, 314, 42 2: Bump 116, 316, 416, 514: Tin ball 118A, 418A · First silver glue layer 118B, 418B: second silver glue layer 120, 32 0, 42 0 '50 4: heat sink 122, 32 4, 424: adhesive layer 3 2 2: dam 410: CSP package 1A-1 A', 3A- 3A ',: horizontal line 5 0 2 · grain 5 0 6: interconnect substrate 5 1 2: colloid

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Claims (1)

1228302____ VI. Patent application scope 1. A composite stacked package, comprising: a substrate having a Cavity, the substrate having an upper surface and / or a lower surface, the lower surface being opposite to the upper surface; The heat sink is disposed on the lower surface of the substrate; a first die has a first surface and a second surface, and the second surface is opposite to the first surface, and the first crystal The grain system is located in the crystal cavity, and the first surface of the first crystal grain is adhered to the heat sink; a plurality of gold wires are used to electrically connect the second surface of the first crystal grain with the US board. Connected; / / a second grain, is disposed on the second surface of the first grain, and the second grain has an active surface, the active surface has a plurality of bumps (Bump); And 'a piece of glue (£ 11〇 & 03111 & 1 ^ 〇11) is used to cover the first die, the second die, and the gold wires, and the convex The block is exposed to the sealant. . 2, 2nd if the scope of patent application! The package according to the item, further comprising a first silver glue layer and a second silver glue layer, the first die is fixed on the heat sink through the first silver glue layer, and the second crystal The granules are fixed on the first crystal grains through the second silver glue layer. 3. The package according to item 1 of the scope of the patent application, wherein the substrate has an upper surface 'the gold wires are electrically connected to the upper surface of the substrate' and a plurality is disposed on the upper surface of the substrate Solder balls, and the top ends of the solder balls are approximately on the same horizontal plane as the top ends of the bumps. 4. The package as described in item 丨 of the patent application scope, wherein the projections Page 13 1228302 VI. Scope of patent application The block is completely exposed outside the sealant. Taxi 5 · The package as described in item 1 of the scope of patent application, wherein the shooting device further has a stopper, which is located near the cavity to limit the coating range of the sealant. 6. The package as described in item 1 of the scope of patent application, wherein the depth of the wafer is greater than the thickness of the first wafer. 7. A composite stacked package comprising: a substrate 'having a cavity, the substrate having an upper surface and a lower surface', the lower surface being opposite to the upper surface; First, the thermal sheet is disposed on the lower surface of the substrate; a first die has a first surface and a second surface, and the second surface is opposite to the first surface, and the first surface is Located in the crystal cavity, and the first side of the first die is adhered to the heat sink; a plurality of gold wires are used to electrically connect the second side of the first die with the substrate; A chip size package (CSP) is stacked on the second surface of the first die, the chip size package has an active surface, the active surface M has a plurality of bumps; and cuts 163 " The sealant is used to cover the first die, the wafer size seal and the gold wires, and the wafer size package 2 is exposed outside the sealant. 0 piece system 48. The package as described in item 7 of the scope of the patent application, wherein the wire system is electrically connected to the upper surface of the substrate, and the upper surface of the substrate is provided with a plurality of solder balls, and The tops of the solder balls are connected to this 1228302_ VI. Scope of patent application The top ends are about the same horizontal plane. 9. The package according to item 7 of the scope of patent application, wherein the bumps are completely exposed outside the sealant. 10. The package according to item 7 of the scope of the patent application, wherein the package further has a stopper, and the stopper is arranged near the crystal cavity to limit the coating range of the sealant. 11. The package according to item 7 of the scope of patent application, wherein the depth of the cavity is greater than the thickness of the first wafer. _ Page 15