TWI227629B - Method and related processing circuits for reducing memory accessing while performing de/compressing of multimedia files - Google Patents

Abstract

Method and related apparatus for reducing memory accessing while de/compressing multimedia files, especially video or image files. While de/compressing multimedia files, an image picture is split into blocks, and a frequency data array corresponding to a frequency transformed and quantized block is stored in a memory for later de/compression. The method of the invention including: registering a bit plane containing a plurality of bits in a register module, wherein each bit represents whether a corresponding element of the data array equals zero. While accessing the memory for the data array, if a bit of the bit plane shows that its corresponding element of the data array is zero, the element is not actually accessing from the memory. Also, checking bits corresponding to elements not yet accessed; if these bits show that elements not accessed are all zero, accessing for the data array can be terminated without actually accessing them. Thus, memory accessing and memory bandwidth requirements can be reduced.

Description

1.… 一 -2_ 号 92134163 车 q 〇 修 ίΕ V. Description of the invention ^ " ------ 丄 " [Technical Field] $ ^ month provides a way to reduce memory, compress and decompress multimedia files, : Sub-fetching method and related device, especially a method and related device for reducing memory access by avoiding access to zero-value frequency-domain data. [Previous technology] As a result, the development and progress of signal sensing and processing technology, regardless of still images or dynamic video and audio information, can be stored and processed in the form of electronic (especially digital) signals with low distortion. , Pass. However, generally speaking, multimedia files containing various audio and video information have a fairly large file size, and they must be appropriately compressed to be easily saved and transmitted. Correspondingly, compressed multimedia files can only be played after being decompressed. Among them, because the image data in multimedia files is rich in high-dimensional data (including 2D images and / or changes on the time axis), the process of compressing / decompressing them also consumes system resources. Therefore, how to compress / decompress the image data in multimedia files with high performance and low cost has become the focus of research and development by modern information manufacturers. Please refer to Figure 1. Figure 1 shows the outline of a typical image compression process (such as the compression process under the MPPE specification, MPPE is M o t i ο η p i c t u r e E xp e r t G roup). As known to those skilled in the art, image compression can be regarded as a process of encoding image data, and decompression accordingly corresponds to—

^ 1211629 Λ_Κ. V. Description of the invention (2) Process of solution. As shown in Figure 1, a dynamic image data M (such as,, and moving day) can be regarded as a combination of multiple static day surfaces Ab A2, A3, A4, A, etc .; showing different daylight with time On the other hand, the moving image data M can be presented as a moving image. In order to effectively improve the compression ratio, when compressing and encoding the image data M, a day-to-day difference detection / encoding (intra-c 0 ding) can be performed in the process 10 to analyze the difference between the day-to-day differences; For the result of the process 10, further encoding (ie, inter-coding) is performed in the same day, that is, process 12. As is known to those skilled in the art, in a section of moving image showing a continuous action, in fact, the difference between the day and the day is not large. For example, in Figure 1, this dynamic image composed of frames Al, A2, and A3 is to show the dynamics of an object 0 j moving in the same background Bk; except that the position of object 0j will be between different frames. Beyond the changes, the background Bk image does not change much. In the process 10, a motion detection (mo t i on detection) can be performed to compare the same and different parts between the pictures. Taking the example in Figure 1, for example, by performing dynamic detection on the day surface A and A2, it can be roughly analyzed that the image of the object 0 j is moving, and the image of the background B j is stationary; in addition, it can also be calculated A vector V1 2 is generated to represent the direction and distance of the image of the object 0j moving on the screen. In other words, by moving the image of the object 0 j in the picture A1 along the vector V1 2 (called motion compensation), roughly the picture A2 can be obtained. The image formed by moving the image of the object 0j • in the diurnal plane A1 along the vector V 1 2 can be called a prediction picture P2 (not shown in Figure 1), which is regarded as the result of the estimation of the diurnal plane A 2 . Of course ’this predicted picture P2 may not exactly match the actual daytime face A2 (such as objects

Page 8 "I22f _: Case No. 134163_ Years and Months Amendment ___ V. Description of the invention (3) The reflection of the body 0j may have slight changes between the day and day A and A2, etc.), but both The difference between them should be small, so this predicted picture P2 can be subtracted from the actual daytime plane P2 to get a difference daytime plane D 1 2. In other words, add the difference screen after dynamic compensation of the day surface A1! ) 1 2 can obtain the daytime plane A2 °, which means that all the image information of the pictures Al, A 2 can be covered by the daytime plane A1, the vector VI 2 and the difference daytime plane D1 2; and because the predicted daytime plane P2 and daytime The difference between faces A2 is not big, the difference is day and night! ) 12 contains a small amount of image information ', so it can be compressed to a large degree, which is equivalent to compressing Al and A2 in the daytime. ~ Picture A2 and corresponding A1 A2, A3 This is correct by the daytime surface A1, the difference is of course, the image data is like the picture A4, the moving picture in the scene does not need to perform dynamic detection clips outside the daytime surface According to the same reason, the picture A3 in Figure 1 can also be obtained by the vector V23, the difference day surface]) 23, and the dynamic image segment composed of a series of images on the picture can be the day surface D12, D2 3 and The vectors vi2 and V2 3 represent the first and the second image compression. Material M may include many different irrelevant segments. A5 may be completely different objects in completely different back segments. Therefore, the difference between daytime surface A4 and daytime surface A3 is very large. This A3 and A4 are used for dynamic detection and can be For A4 and A5, another test is performed to compress the series of dynamic images A4 and A5 in the daytime. m In the process 10, for the day to process 12, for the difference between the day and the surface, as shown in Figure 1, press the screen or the difference between the day and the day, Al, A4, and the difference screen are reduced / encoded, then it can be distinguished. Compression / encoding. Dl2, D23 and D45 all

Page 9 122 ▼ Touch "Shame 92134163 Month _Θ_ Correction

5. Description of the invention (4) Compression is performed to increase the compression ratio. As for the steps to be performed in the process 12, please continue to refer to FIG. Figure 2 is a schematic diagram of the compression / encoding process in Process 12. To further compress the diurnal plane A (can be the diurnal plane A1 or A4 or the strange pictures D 1 2, D 2 3, etc.), first divide the picture A into a plurality of small blocks B, each block B ( b 1 ck) is a combination of a plurality of pixels B i. For each block B, the output data obtained by performing a two-dimensional frequency domain transformation (such as discrete cosine transform (DCT)) is a frequency data array C including a plurality of data elements C i j. In other words, each data element C i j represents the component of block B in the frequency domain. The data element Q i j obtained by quantizing each data element C i j can form a quantized frequency domain data array Q (that is, a frequency domain array). Each data element Qj in the two-dimensional data array Q is arranged into a one-dimensional one-dimensional data array S in a specific order, which is a streaming scan. The data array s can obtain another one-dimensional data array R after running length coding. The data array = R is then Hoffman coding (Hoffman coding), we can get a data 2 L combined with each block _ different corresponding data array H, and can complete the coding of the picture A. In the process performed by the process i2, since each block 雎 is a small pixel Bij of the daytime plane A, the value of the pixel Bij should also be dragged from time to time. After conversion and quantization, it represents the data element ci in the ancient frequency-frequency domain and Q represents the minimum value of T), that is, an array of frequency-domain data 2020; Increasingly, the data array Q is arrayed as &

Page 10 mmm '. Corrections

Take the data elements in m :: array, "(each equals-floating long-term code protection, and many of them are zero. When performing value data on the data array S, the number: For example, in Ping Yi's compressed data array s length. There are π) LC primes s 1 and i a non-zero data element over-floating length encoding, to two tables i fS: two, 70 The prime sj can be bundled with zero number 921341. Fifth, the description of the invention (5) R, the bit length is VLt: JJ length encoding, the bit length of the data array material R obtained by f is 1 H, After Huffman coding, the data H. Compress each block t by one / press f to become the data array after the day surface A is compressed ^ \ 所 ^ \ 资 / 斗 阵 / 阵 合When you get up, you can% < ,, ..., and become a compressed multimedia file. "行 ί" ΐ: J f 〇 Assets: It is static image data, so it does not flow i2 (such as JPEG specifications) When decompressing a file, compressing i !; = shrinking ", the reverse process of the media file. Compressed multi-body two-soil 2 shrinking process (t, ,, s anti-scan) After knowing the data array Q ^ ^ ^ ^ know that you can get the frequency domain data array ^^ = j deqUantlzation) transformation (such as inverse discrete cosine & then = material array / JC inverse frequency domain transform, TΠΓΤ, "Wu ^ nverse d 1 screte c〇sine 'can get block B; combine different block b countries

Page 11 1 Reduction 9 Revision ^ 1 ^ 92134163 V. Description of the Invention (6) 1 Especially ^ to 丨 丨 | Available $: ^ 面 A. If the original image data is dynamic image data, the corresponding dynamic compensation (ie, the process in Figure 1) is performed on the two planes, f, and f, to combine the original motion image data to achieve decompression (decoding). the goal of. Please refer to the figure; the processing is the image processing unit, a frequency domain conversion and an internal unit 14 to achieve direct performance, so that the process in the external memory is being used to implement the inverse quantization model to restore the surface. The resources required for 20 itself are also two. Figure 3 is a schematic diagram of the functional block of a conventional processing circuit 20, and the channel 20 is used to process the compression / decompression of the image data (also the data encoding / decoding). The processing circuit 2 is provided with a central 14, a memory access module i 6, a dynamic estimation module i 8, a conversion / quantization module 22, an inverse frequency domain conversion / inverse quantization module 24, and a memory 2 8 (Like random access memory). The central processing is used to control the operation of the processing circuit 20, and the memory access module 6 can be used for direct memory access (DMA). The power circuit 2 0 can directly access an external memory 2 6 (such as by The image data to be compressed is loaded into the body 26). When performing FIG. 10, the dynamic estimation module 18 can be used to perform dynamic estimation. When the stream f 1 in FIG. 1 is used, the frequency domain conversion / quantization module 22 can perform frequency domain conversion, conversion, and other processes. In contrast, the inverse frequency domain conversion / group 24 can decompress (decode) the one-dimensional data corresponding to the one-dimensional data in the compressed multimedia file to obtain each module in the support processing circuit 20: There is an internal memory body 2 8 outside the j pieces, and a processing circuit with ten operations is used. The body 28 is used to temporarily store the operating time of each module. (Edit For example, the circuit 20 performs image data compression in the cellphone office.:·1 {-'一' ν · * ί V ¥ .- ·: -V j 1 92134163: ί2 · guan

V. Description of the invention (7) When the code is ^, the frequency domain conversion / quantization module 22 will convert / quantize the block β (refer to Figure 2) of each picture into a two-dimensional data array Q, and this data Each data element Q ij of the array Q will be written into (stored in) the internal memory 28. When a streaming scan is to be performed, each data element of the data array will be sequentially read out from the internal memory 28 to form a one-dimensional data array S, and then the subsequent encoding process is performed. As can be seen from the above description, in the conventional processing circuit 20, frequent access to the internal memory 28 is required. It can be known from Figures 1 and 2 that an image data M may include many diurnal planes a, and a diurnal plane a may have many blocks B. Each block B has its corresponding frequency domain data array Q. When the conventional processing circuit 20 performs image compression, each data element Ql j in each data array Q is stored in the internal memory 28 one by one, and when streaming = scanning, it is necessary to Read each data element Qi sequentially one by one. In fact, as discussed earlier, in fact, the frequency domain data array Q is very likely ^ 2 = sparse matrix, most of the data elements Qi are zero, which is ^ ^, the degree encoding can shorten the array S The reason is that because the floating length is edited, the number of zero-valued data elements needs to be recorded. It is not necessary to display these zero-valued data elements one by one in the two-dimensional array R. However, there is no good way to take advantage of the characteristics of this sparse matrix when the data array Q is accessed in the internal memory 2 8 by the circuit 2 0. It is still only possible to-^ Q ij. This also makes the conventional processing circuit 20 need to perform frequent data on its internal memory 28 during the encoding / decoding process. Taking 1 as its memory resource occupied cannot be effectively reduced. In order to achieve the function of speed compression / decompression, the conventional processing circuit 20 needs to use high frequency

Page 13 92134163 _η Name Amendment V. Description of the invention (8) The internal memory with a wide width (that is, more data can be accessed per unit time) makes it impossible to reduce the cost of circuit design and manufacturing. Therefore, the main object of the present invention is to propose a method and related device that can reduce the number of accesses to internal memory during the compression / decompression of image data by utilizing the characteristics of the frequency domain data array being a sparse matrix. The memory resources required during the compression / decompression process overcome the shortcomings of the conventional technology. In a preferred embodiment of the present invention, a two-dimensional bit plane (bit ρ 1 ane) is temporarily stored as a two-dimensional reference array by a temporary storage module implemented by a translation register. Each bit of the meta-plane corresponds to a data element of the frequency domain data array, and is used to represent whether the value of the data element is zero. In the process of compressing image data in the present invention, when each data element of the frequency domain array data is quantized one by one and is to be stored in the internal memory, the state of whether it is zero or not can be recorded in the bit plane together. ; Only non-zero-valued quantized frequency-domain data elements are actually stored in the internal memory, and zero-valued quantized frequency-domain data elements do not have to be actually stored in the internal memory. Accordingly, when streaming scanning is to be performed, the technology of the present invention can be

Page 14 " 12-year-old P9; 丨 Number 92134163 V. Description of the invention (9)

According to the bit plane, a certain data is read out. If a data element is in place, the actual element is not necessary. On the other hand, when it is based on the bit of the string plane, it can be checked to be zero. If all the unread data ends the streaming scan, it is also possible that as long as the quantized frequency domain data array is performed to a certain extent, the element is read out. The present invention can facilitate the access of the streaming scan memory of the frequency domain array data. Whether the element should be represented by the bit corresponding to the meta plane in the internal memory. The data is read by the internal memory. The sequence of the data stream scan is checked one by one whether the unread data elements are all zero. Can directly access the internal memory. From the sparse matrix, streaming scans have already used all non-zero values of this feature to quickly complete the mapping, which can also greatly reduce the concurrency of the internal data matrix.枓: When column: you can create a bit array data array to actually write "judge whether you want to check whether the two-dimensional cheek is a bit in the bit plane; All are zero 'to simplify the inverse frequency domain conversion operation.' In other words, Α 士 α

In the case of dimensional / X zero-valued data element distribution, understand the frequency domain array 1 access to reduce pairs = Qiu, shape, and thus avoid occupying ^ 5 memory during decompression of zero-valued data i Access, reducing memory resources occupied by image resources and internal memory

Page 15 1227 ^ 629 gi No. 92134163 Rev. V. The requirement of invention description (10) enables the compression / decompression processing circuit to have better performance, lower cost and power consumption. [Implementation method] Refer to Figure 4 for words. FIG. 4 is a functional block diagram of a processing circuit 300 according to an embodiment of the present invention. The processing circuit 3 can be used to compress the image data (that is, to encode the image feed into smaller files). Processing circuit 3 〇 set = a central processing unit 32, a memory access module 36, a dynamic estimation result 3 8, an internal memory 5 2, a frequency domain conversion / quantization module 4 〇; == only In the technology of the present invention, the processing circuit 3 is additionally provided with a data generator 46, a judgment module 48A, an inspection module 48B, a temporary storage module $ 50, and a translation control module 54. . The central processing unit 32 is used to control the operation of the control unit. The memory access module 36 is used to directly access an external body 7 and the motion estimation module 38 is used to perform motion estimation. Frequency domain conversion ί = i; t0: then? There are frequency-domain conversion modules ^ Perform frequency-domain conversion (^ Xiang Zhengquan Quanzai 42c 'of which 42 people use the frequency-domain conversion module — and refer to Figure 2) Ϊ 疋 cosine conversion from the political party) to convert a block B (Please use the frequency domain number # to be a frequency domain data array C, the quantization module 4 2 Β into the correction module 4 2 d '/ # ^^ 2 is the quantized frequency domain data array 0. 量 Prediction ) 3 current and 2 f-stream / DC prediction (AC / DC result. In general, the% frequency-domain correction quantization module 42B quantizes the block B to perform frequency-domain speckles-and the digitization module 40 is to place the image in the picture. In addition, the internal memory 52 uses t as the normalized frequency domain data array and supports the operations of the above modules.

^ 109: \ Said to amend MM 92134163 __ ^ V. Description of the invention (11) Temporarily store the data required for the operation of the above modules. It is taken as a packet element Γ Λ. The dual-control quantized frequency-domain data array Q is stored in the internal memory 52 as: group :: can be used to temporarily store a one-bit plane. Right: ί plane N is a two-dimensional reference array. There are several one-bit reference elements Ni] in the 2 and each bit 2 2, & j corresponds to a data element Qi in the data array Q. Represents whether the value of the data element Qi j is zero. Since each multi-test element N ij is only one-bit data, the temporary storage module and shift register are used to implement the translation control; the .Γ mode unit Then, the bit shift in the temporary storage module 50 can be controlled to access the value of each bit. The judgment module 48A and the check module 48B can control the data array Q according to each bit Mj of the bit ^. In the internal memory 52, regarding the temporary storage configuration of the median plane N of the temporary storage module 50, FIG. 5 (refer to FIG. 4 together). FIG. 5 is the median position D of the present invention.

It is a schematic diagram of an embodiment. Compression is commonly used in current image compression. Medium (like the MPEG specification), there are 8 * 8 pixels in a block b. In the case, there are also 8 * 8 data elements in the quantized frequency domain data array Q. There should also be 8 * 8 in the plane of the element. Bits. In the comparative example of the present invention, eight 8-bit unit cell shift registers (8 " = hift regist: r with bit shifter) can be used to implement ^ group 50. As shown in Figure 5, the quantized frequency-domain data array 昉 昉 料 凡 primes Q00-Q07, Q10-Q17, etc. to q7〇_Q77. Accordingly,

There are also 8 * 8 bits N00_N07, N10_N17, and so on in plane N to N701. The eight bits H_N〇7 are combined into row (r0W) R0, and bits N10-N17 are combined into row R1. analogy. y Yu Benming technology in the process of image data compression (encoding): the second discussion. First, the frequency domain transforms two daggers; i i tv:: J f, ^ ^) # ^ ^ q i ^ ^ ^ ^ 5 ^ ^ f ^ ^ ^

Whether Qu · should be actually written to = ^ = (and-and refer to Figures 4 and 5); _ in the reference figure, quantized frequency domain data array · stored in V /, without thinking that the present invention The 48 spine control data elements are written in the f-body, J f judgment mode, and the material array Q is mostly a sparse matrix. 7 ′ right 〇 = no, discussed, zero. Assume the frequency domain conversion / quantization module: 0 in. J :: 资 :: Straight 0〇ί 'bQ〇 ^ ΪΠ' ^ 2! ^ ^ ^ ^ ^ Ϊ ί ^ ^ Zero. As shown in step 62 of FIG. 6: before the rest of the data elements are in the memory 52, the corresponding bit Q is stored in the internal bit, and it can be reset to 0 digits, ten faces, not yet established. Each within

"Ί; ί:; ΐ: Each bit Nlj is represented by a digital". "Corresponding to a #zero value data element i · zero and represented by a digital" 1 "

Or the conversion / quantization module 40 quantizes the first data element Q00 of the data array Q. Because the quantized value is non-zero, the corresponding bit on the bit plane should be a digital Γ 丨 ", In step 62B in FIG. 6, this one-digit “丨” bit can be temporarily shifted to the rightmost bit in row R0 by bit-shifting; at the same time, the judgment module 48A will use this to A digital "1" bit knows that the value of the data element Q0 0 is non-zero, so that the data element Q00 is actually written into the internal memory 52. In step 62C, 'the frequency domain conversion / liquidation module 4 0 continues to complete the quantization of the next data element chapter and generates a data element Q 〇1', because its value is also non-zero, it is necessary to use Another digital "1" bit is used to represent, and the digital "1" bit can continue to use the bit shifting method to be stored in the rightmost bit of the line; The digital "1" bit of data element Q 00 is shifted to the left (in the direction of arrow 64) by one bit. At the same time, the judgment module 4 8 A will also cause the non-zero data element Q 0 1 to be actually written into the internal memory 52 0 due to the digital "1" bit corresponding to the data element Q 〇1. In step 62D, the frequency domain The conversion / quantization module 40 generates a third quantized tributary element Q02 'because of its quantized value is zero'. At the far right of row R0, a digital "0" is also recorded in a bit-shifting manner. Bits; the two digital "1" bits that originally corresponded to the data elements Q 〇〇, Q 〇1 will continue to be shifted to the left by one bit. The judgment module 48A will not actually write the data element Q 02 to the internal memory 52 according to the digital "0" bit corresponding to the data element Q0 2 and reduce the number of accesses to the internal memory 52.

\ Ίί ^ Γ-: 土 ",

It2i2ffei9 ^ \ >! _ No. 92134163 Revision V. Description of the Invention (14) | According to similar steps, when the frequency domain conversion / quantization module 4 0 sequentially outputs the quantized data elements Q 0 3 to Q 〇7 , The bit corresponding to each data element on the bit plane n will also be recorded in the row r 0 one by one in a bit-shifting manner, and the judgment module 48A can judge the asset according to the bit corresponding to each data element | The material element should not be actually written into the internal memory 5 2. At step | step 6 2 E, the frequency domain conversion / quantization module 4 0 generates a quantized data element Q 0 7 whose corresponding bit is a digital "0", and it is also recorded to row R in bit shifting manner 1 0; and the judgment module 4 8 A does not cause the data element Q 〇7 to be actually written into the internal memory 52. At this step, the frequency domain conversion / quantization mode! Group 40 has output all data elements Q00 to Q07 in the first row of the data array q, and the row R0 with the status element plane n is also completed. Next, the frequency domain conversion / quantization module 40 will continue to output the data elements Q 1 0 to Q1 7 of the second row of the data array Q, and the row R1 of the bit plane N will also be bit-shifted. The bits of the data elements enable the judgment module 48A to control the internal memory 52 to access these data elements. By analogy, after the frequency domain conversion / quantization module 40 outputs all the data elements of the quantized frequency domain data array Q, the status element plane N will be established. Please refer to Figure 7 (also refer to Figures 4 to 6). Continuing the example in FIG. 6, FIG. 7 is a schematic diagram after the bit plane N is set up; each element N i j corresponds to a data element Q i j of the data array Q. In the examples of the present invention in FIGS. 6 and 7, since the data array q has only five non-zero data elements, when the data array Q is completely stored in the internal memory 5 2, only actual access is actually needed. (Write) Internal memory 5 2 5 I times. In contrast, because the processing circuit of the conventional technology is not stored in

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92134163 V. Description of the invention (15) The zero / non-zero judgment is performed when the data array Q is modified. Even if the data element Q ij is zero, it must be actually written into the internal memory, occupying a large amount of memory resources. . Please note that even if the value of the data element Q ij is zero, it does not mean that this data element Q ij is only a single bit of data with a number "0", because the data element Q ij should all be in several bits. Recording its value 'also means that the conventional technology's access to the zero-valued data element Q ij consumes considerable memory resources. In some cases (such as when performing AC / DC prediction), the quantization correction module 4 2 C will correct the values of certain quantized data elements Q ij (such as changing non-zero values to zero under reasonable circumstances), At this time, corresponding bits on the bit plane N may also be corrected according to the correction result of the quantization correction module 42C. Please refer to Figure 8. FIG. 8 is a schematic diagram of the modified bit plane N of the temporary storage module 50f according to the present invention. When making such corrections, usually only the data elements Q00 to Q07 and Q00 to Q70 are combined. At this time, the data elements can be modified in the same way as bit shifting as shown in Figure 8 To the deer. After the non-zero data elements of the data array Q are stored in the internal memory 52, and the corresponding bit plane N is established, next, when the data array Q is to be read out, the present invention can also N to control the reading of data array Q. As discussed in Figure 2 and related descriptions, the quantized frequency-domain data array Q will be read from the internal memory for streaming scanning, and the two-dimensional data array 歹 4 Q =: data element basis The specific arrangement is a one-dimensional data array. Please refer to Figure 9 to Figure 11 (and together

Zhuanhu 921341 rib _ bismuth_. V. Description of the invention (16) Reference ί ί There are two types of string "dragging" order in the compression / decompression specifications of the video data, which are deformed vertical scanning alterna ^ vertical scan), deformation horizontal scan (aiternate horizontal scan), and the 7 treasure curtains from j to χ from ρ such as seven buckets, λα pine w sigh Zzizag scan; the order of the three descriptions That is, they are shown in Figs. 9 to 11. In Fig. 9 and Fig. 10, each data element QU of data array Q has a label, that is, 2 indicates the order in which the lean element is scanned; Smaller, it means that it is arranged (scanned) into the one-dimensional array first. For example, in Figure 9, each data element Q i] • will be based on the data elements Q〇〇, 10, Q20, Q30, Q01, QU, Q〇2, Q12, Q21, Q31, 40, Q50, Q60, Q70, Q7, Q61, etc. up to Q47, Q57,) 7 γ. Q 7 7 is arranged in a one-dimensional array. In Figure 10, The order in which each data element Qi j is arranged as a one-dimensional array is Q〇〇, Q〇1, Q02, Q03, Q10, etc. to Q74 'Q75, Q76, Q77. In general, in the quantized frequency domain data array 卩, the data element Q〇〇 represents the DC component of the corresponding block B in the frequency domain (hence it can be called DC, Wusu) \ Relatively, other The data element is the AC component in the frequency domain (so it can be called the AC frequency domain element). In the data array Q, the data element farther from the element Q 0 0 (such as the data element in the lower corner of the array) 'The corresponding frequency is higher, and its value is likely to be zero. Therefore, when the data elements of the data array Q are arranged in a one-dimensional array, the scanning methods in Figures 9 to 12 will preferentially scan the data in the upper left corner. Element (data element near the stomach near the data element Q 0 0) to facilitate subsequent floating length editing. Μ

In the present invention, when the data elements are to be stored in the internal memory 5 times, and the column Q is read out in the scanning order, the bit plane N can also be accessed in the order of the matrix. Each corresponding bit of ^, and ^ interpolate the value to determine whether to actually read the corresponding data element from the internal ^ jikang bit. In addition, the present invention can also read the frequency domain data and consider whether the remaining (unread) data elements are all cross-primary data elements when they are all zero. The second $ 3 read of the material array reduces the number of accesses to the internal memory 5 2. In order to embody the above-mentioned inspection steps, the inspection module 48β in the present invention (see Fig. 4 is true to perform an OR operation on the bits in the bit plane N to obtain two =). STP (that is, STP =! ( R0 | Rll R2I R3I R4 | R5 | R6 | and determine whether scanning can be finished according to the flag STP. In order to specifically explain the implementation of the present invention when performing streaming scanning, please refer to FIGS. 12 and 13 ( Refer to Figure 4, Figure 7 and ^ 7 '9). Continuing the example in Figure 7, suppose the data array Q and its corresponding element plane N are as shown in Figure 7, and in the order shown in Figure 9 Source data = Stream scan is performed by array Q. As shown in step 6 A in Figure 12, when the stream scan is not started, the bit plane N is the same as shown in Figure 7. When the stream After the fluidization scan is started, because the flag STP is a digital "0" in the digital plane N), the inspection module 48B judges two scanning. According to the scanning order (see Figure 9), it is necessary to First obtain the data and the value of the element Q00. At this time, the judgment module 48A can Whether element) to be actually determined by the internal memory 52

P.23 £ [22 翁 面) #_ 号 92134] YYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYIIIIII Three Days of the Year_Amendment 5. Read the data element Q 0 0 in the description of the invention (18). Because the first bit of the row r 0 is a digital "1", which indicates that the data element Q00 is non-zero, the judgment module 48A will cause the data element Q0 0 to be actually read from the internal memory 52. After reading the data element Q 0 0, the translation control module 5 4 (Figure 4) will also shift each bit of the row R 0 to the left by one bit, and the rightmost bit will record a digital "0" (also Is the bit labeled "X" in Figure 12), as shown in step 66B. This bit shift means that the bit corresponding to data element Q00 in row R0 has been processed. In step 66B, the inspection module 48B will not abort the streaming scan because the flag STP is still a digital "0" (where the mark "X" is a digital "0"). According to the sequence shown in Figure 9, at this step The value of the data element Q10 should be obtained, so the judgment module 48A will determine whether to read the value of the data element Q10 according to the leftmost bit of the row ri (corresponding to the bit of the data element Q1 0). Since this bit is a digital r 0 ", the judgment module 48a will not actually read the value of the data element q 1 〇 from the internal memory 5 2 (in fact, it is not necessary to store zero in the internal memory 5 2 Data element Q1 0), and the data generator 46 can be used to process the value of data element Q1 0 to reduce access to the internal memory 52. After the reading judgment of the data element Q1 〇 is processed, the row R1 in the bit plane N will also be shifted to the left by one bit and a bit “0” (labeled “χ”) will be entered at the far right. The bit corresponding to the data element Q10 in the representative row R i has been processed. The bit plane N of the bit is as shown in step 6 C. In step 66C, the "check module 48B" is caused by the flag STp of the digital "0" ^^ 92134163 5th, invention description (19) Streaming scanning continues (the two marks on the bit plane N " X "are all numbers" 〇 "). According to the sequence in Figure 9, this step is to read and judge the data element Q20, and the judgment module 48B will because the first bit of the row (corresponding to the bit of the data element Q2 0) is the number r 0. " It is not necessary to actually read the data Q20. After processing the reading & breaking of the data element Q20, the row R2 of the bit ^ plane N will also be shifted to the left by one bit and recorded-a digit "0" (marked "X"), which will become what it was in step 66D. Similarly, at step 66D, the flag STP is still a digital "0". The streaming scan will continue to process the data element Q 3 0, and the judgment module 4 8 A will be because the first bit of row R3 is a digital "〇" without actually reading data element Q30. After processing the data element Q30, the row R3 will also be shifted to the left by one bit, and a single bit “0” (marked with “X”) will be entered, and it will become as in step 66E. At step 66E, the flag STP is a digital "0", and the streaming scan continues to process the data element Q0 1 (as shown in Figure 9). Because the first bit of row R0 (after the bit translation of step 6 6 A, the bit is the bit corresponding to the data element Q0 1) is the digital "1", the judgment module 48A will make the data Element Q 0 1 is actually read from internal memory 5 2. After processing the data element Q01, the row R0 also records a digit "0" (symbol "X") by shifting one bit to the left, which becomes the state in step 66F. As streaming scanning continues, the number of processed data elements increases, and there should be more and more digital "0" bits in bit plane N, because

Page 25 Correction

The bits corresponding to the processed data elements are all recorded as a digital "0" (ie, marked "X"). As shown in steps 6 6 F to 6 6 J (from Fig. 12 to Fig. 13), each time a data element is processed in the streaming scan, the bit plane N will be bitwise in the row where the corresponding bit belongs. The method of meta-translation is recorded in a bit "0" (ie, the symbol "X"), so that the inspection module 48B can judge whether the radonization scan should continue according to the bit-plane N after the bit-translation. As shown in FIG. 13, at step 66 K, the streaming scan proceeds to the data element Q40, and the judgment module 48B causes the data element Q4 0 to be deleted from the internal memory 52 according to the first bit of the row R4. It is actually read out, and the row R4 of the bit plane N is also recorded with a bit “0” (marked with an “X”) in a bit-shifting manner to the left, which becomes the state in step 66L. In step 6 6 L, 'Because all the bits on the bit plane N are digits 10', which means that the unprocessed data elements are all zero. At this time, the flagpole STP becomes a digital "1", and the check module 48B According to the flag ST, the streaming scan can be ended directly, and the entire streaming scan can be completed. In other words, the present invention has two mechanisms for reading one by one when performing streaming scanning and processing one by one. One is the operation of the judgment module 48A and the access of the internal σ 卩 memory. The other mechanism is to check the zero data element STP of the module to determine that the unprocessed data element is the operation of β, so that the stream and scan can be completed directly and quickly according to the flag. If they are all zero, then access the zero-valued data element. Borrow: temporary = 5 2 plane N of internal memory, the present invention can actually access the internal memory in the temporary storage module 50

PD No. 921341 Five, Invention Description (21), quickly determine whether each data element is zero. Compared with the conventional technology, the above-mentioned mechanism is lacking to judge 'Figure 3 is zero. Therefore, J must read out the data elements of WKJ one by one when performing the streaming scan, regardless of whether the data elements are earlier.歹] Therefore, the knowledge technology will consume a large number of memorizing styles. Is it zero? In the thirteen examples, the present invention 3 彳 v η — M aa τ 处理 has processed every square 151 which has been translated to the left with the same time interval 151 — # 4 plus one percent water renewal position. Behind the element, on the one hand, the next bit of the same line (the first bit of the line), so that the judgment module _ is the ^ data element for access judgment, the same as the _ Renyi Bit to determine if it is zero. For example, in the data pair, the left-most line 66A, 66E and step 66G, step 66A Jiangci; the thirteenth step element is translated to the left-most line R0, so that when the corresponding bit 66E of the == f prime element is determined, according to the line The bit on the far left of R0] is broken, and if 48A can be in the same row as the element Q00, is it Wen J, and the element Q01 (the bit corresponding to the element Q02 is shifted again; in step 66E, the data At step 66G, the judgment module 48 takes the left again. Wait until the step is performed to determine the data element Q02 (the leftmost bit of the data according to row R0 is zero. Observe Figure 9, Figure 10, and 2 of Beizhongyi _, Q〇i same-line) whether the data element is 4 data elements: 2 sequence can be known, the data element of the same-line takes precedence, so the order of the sequence in Figure 12 will be more complete than its right-hand form It is applicable to the scanning sequence in Figure 9 and Fang Huiyi, which is shifted to the left in the middle of & 丄 1. 2. In contrast, when you want to use the scan in Figure 10 to avoid the stream scanning, each

Page 27 p Tiger 9213416 $

V. Description of the invention (22) The order of the data elements is not necessarily the first. As shown in Fig. 10, like the elements Q14, Q15, Q16, and Q17 in the second row, they are 1, 7, 16, 15, and 14. Similarly, the priority order in Q 2 3 is 19 and 18 respectively. The method of shifting and accessing can be applied to the temporary storage module of FIG. 10. The 0 can be used as shown in FIG. 14 for the row of bit plane N. The multiplexer 68, which is closed by R 1, and the control bit shift switch realize different translation control, so that the switch supports all the shift control modules 5 4 in FIG. 9 to FIG. 11, which can use a one-bit bit shift method. In the data element that is superior to the right, the data arranged from left to right has the order of precedence in the third row, respectively. The data elements Q22 and 3 are for the scanning order of the bit plane N bit plane. The present invention Circuit. As shown in FIG. 14 k R 2 ′, the present invention specifically sets a phase direction translation controller 70, so that the temporary storage module of the present invention can be sorted in sequence. For the control signal Cb of the present invention for switching control, please refer to Figs. 15 and 16 (also refer to Fig. 14 together). Figures 15 and 16 are the situations where the temporary storage module 50 in Figure 14 performs the panning # system in different situations. As shown in Figure 15, when the control signal Cb is a digital "丨" guard, the direction of its bit translation is to the left (the un-enabled bit " yuan translation direction has been omitted). The scan sequence in FIG. 11 is used to perform the memory access control in the streaming scan of the present invention. $ On the other hand, when the control signal Cb is a digital "0", the direction of the enabled bit shift is as shown in Fig.16, so as to perform streaming scanning in the scanning sequence in Fig.10. Update of bit plane N. In accordance with the arrangement order of the data elements Q 1 4 to Q 1 7 in the first row, the bits n 1 4 to N 1 ¥ are bit-shifted in the manner of —to the right shift of ^; in other words, for bit N丨 j to

Page 28 _ No. 92134163 Revised

V. Description of the invention (23) For N1 7, the bit of bit N 1 7 is first shifted to the leftmost edge of row R 1, and the bits of bits N16, N15, and N14 are next. Similarly, bits N22 and N2 3 in row R2 are also matched with data elements Q2 2 and Q2 3 by shifting to the right. In other words, when streaming scanning is performed in accordance with the sequence in FIG. 10, the present invention can still use simple bit shifting to sequentially access the bits corresponding to each data element, and perform data element internalization accordingly. Access control in memory 52. 'Please refer to Figure X =. FIG. 17 is a functional block diagram of a processing circuit according to another embodiment 80 of the present invention. The processing circuit 80 can be used for decompressing (ie, decoding) the compressed video material. The processing circuit 8 is provided with a central unit f 82, a memory access module 86, an internal memory 102, a dynamic compensation module 8 8, an anti-scanning module 9 2 A, and a data generation module. Cry :: Yue Ke's Realization Chang Guang Ma / Code Module 92C, and a Conversion Module 9 ;. In conjunction with the implementation of the present invention, the processing circuit 80 is also provided with a temporary storage module, a translation control module 1 Q 4 and a judgment module 98. The main control processing circuit 80 operates in China, and the sixty-sixth * π z early 70 82 uses the generator 92B and the anti-scan module 9 cores: ^:; = 2. , Data production and refer to Figure 2), the inverse scan is the 枓 if 枓 array solution R (please click the data array Q after inverse quantization / transformation, and the frequency domain data array Q. transform (like inverse discrete cosine transposition , And the dynamic complementer Mo group 88 is ^ repeated block pixel array, etc., to complete the compressed image data, two, two. Dynamic compensation is used to support the operation of the above modules 2 " 卩 g Memory resources required by the memory 1 〇2 inch.

_ No. 921341M V. Description of the invention (24)

When the variable-length code decoding module 92C and the data generation group 92A are operating, after variable-length coding, Huo & @ 编 ^^ 模 ~ the material array R will be decoded into a one-dimensional data array & two "' '，' 一 ^ 资 f 资 = Element QU; After inverse scanning, the two-dimensional array Λ will be rearranged into a two-dimensional data array Q; and this data array Q is to be stored in internal memory In the body 102, each bit in the corresponding bit plane bit plane N can be established in the temporary storage module 100 by measuring the car = stored in the internal hidden body m months to determine this two ^ 1 If the QQ is zero, do you want to actually store (write) it in the body \ 〇2. When the variable-length code decoding module 92C, 'data theft 92B, and anti-scanning module 92A Qi 'decoded 2 can determine whether the data element Qij is zero; the corresponding bit 70 N ij can be determined together with mj and r, and can be temporarily shifted in a bit-shifting manner. @ 时, judging module 98 also Can be based on whether the body 1 ϊ ί 素. Qi j is actually stored in the internal memory.. Right shell material 70 卩 "value is zero, you do not need to actually save Chu body takes m 'is an object of the present invention with, designed to reduce the internal array of Q-lean material is saved to the internal memory of i 2 billion, which corresponds to the bit plane Wu = N is also established. When the data array Q is read out and inverted, the judgment module 98 of the present invention can also judge whether to use the internal memory based on the bits N i j in the bit / plane N.

Page 30

5. The data element Qij of the description of the invention (25) is read out. If a certain asset group 98 does not have to actually delete the data element ut ~ the element is zero, and the judgment module data element is not stored in the U1 (in fact, the generator 92B and the address generated by it are: The processing of ingredients. The report reveals that Guang Beicheng uses Wucheng's access to the data element Qi j to access the data system, and then clarifies that it can reduce the internal The number of accesses to the memory 102. ί $: 2 When the f is quantized, the present invention can cooperate-rotate the information in the bit plane. For this situation, see

Bit two flat f party; person. = For the temporary storage module 102 in a rotary type (r〇tati〇n: ―The second ancestor f / present is not intended. For example, in the process of reading the first two = = / 〇 to + Q〇7 At this time, the judging module 98 may first determine whether to actually read the data element according to the line t. After the processing is completed, each bit of the line R0 will be shifted to the left by ^^ ′ to correspond to the data element Q0 The bit is shifted to the left of the line ... = ^ ^, but the bit corresponding to the data element Q〇〇 will follow the direction of rotation H f row / 0 to the far right. The next 'to be processed for data element one' Day guard 'judgment module 98 can still be based on the leftmost bit of row R0

To determine whether to actually read the data element Q〇 丨 (because its corresponding f ^^ is translated to the far left of row R0); after processing the data element Q〇i: the bits of 仃 R0 are the same Pan left, and the position corresponding to data element Q0i is shifted to the far right of the row. In this way, when the reading of the material elements Q〇〇 ～ Q〇7 is completed, the bit plane intestine row r0 will just return to the initial state (that is, the bit plane ^^ has just been established When done

Page 31 View No. 92134163 — Month Revision Ⅴ. Case of Invention Description (26)), keep the information of row R 0. By analogy, when the reading of each > material element Q i j is finished, the bit plane N will also retain all corresponding information. The time is used in the domain material, and the conversion is performed in the prime frequency domain. The domain data is used to transform the group constants in the frequency domain. The domain data is converted to group 96B in the frequency domain as shown in Figure 10. The information of the meta-plane N can also be used to simplify the inverse conversion in one step when performing the inverse frequency city conversion. As is well known to those skilled in the art, Yun Shengzhong exchanges, i day dependent, 仏 τ >miscellaneous; M ^ < rx w yv 1 ^ ——, when converting, it is equivalent to performing a double dimensional inverse frequency in When performing one-dimensional inverse frequency domain conversion, if only DC frequency-domain data elements in a line's frequency-domain data are not zero, the remaining AC materials are all zero, and one-dimensional space converted from one-dimensional inverse frequency domain A column is a constant array (that is, each element is equal to one or two = f. In the present invention, since the bit plane has recorded whether each frequency band is Ling, it can be used to determine whether each row in the array has The above: v. Dimension 7 shows that in the processing process of the present invention, the two-dimensional inverse loop of the mysterious silk thread 80 is performed by the conversion module inspection module 94. The two constant operations: "set in group 90" When performing a one-dimensional inverse frequency-domain conversion operation mode to perform a one-dimensional inverse frequency-domain conversion, the corresponding row on a bit plane N of the lean matrix array in the rubidium domain is converted to check the θ bismuth group 94. According to = prime is a non-zero value, that is, the bit is flat, and the bit with a frequency of DC is a digital "丨 人 _ 应 打 是否= Current in this row only pay frequency domain; said quantity, representing the frequency zero 'and the one-dimensional inverse frequency domain rpm /, I AC output frequency one-dimensional array fields, fruit ®

Page 32 I 1-‘V ,, '' Tao Yanza 92134163 ^ month, month, day, amendment 5. Invention description (27) should be a constant array. At this time, the constant array 9 6 A can be used to calculate the constant array as an output array of one-dimensional inverse frequency domain conversion 0 p. In contrast, if the corresponding row of the bit plane N shows that the row has a non-zero AC frequency domain component, the conversion operation module 9 6 B will actually perform a one-dimensional inverse frequency domain conversion to generate a corresponding output array. P. Please refer to Figure 19 (also refer to Figure 17). Figure 19 is an algorithm to describe the above-mentioned one-dimensional inverse frequency domain conversion. Suppose that one-dimensional inverse frequency domain conversion is performed on the frequency domain data elements BmO, Bml, ..., Bm7 (m is an integer) of a row, and the bits Nm0,

Nml, ... Nm7 correspond to the above-mentioned frequency-domain data elements, which respectively represent whether these frequency-domain data elements are zero. To perform one-dimensional inverse frequency domain conversion, the present invention can use bits Nmi, Nm2 to Nm7 to correspond to AC frequency domain data, prime bits' to determine whether the AC frequency domain data elements are all zero. If it is 丄, each element of the output array OP can be set to the same number C0 (this constant can be calculated by the constant operation module 96A). If not, an output array oop is generated by the conversion operation module 96B actually performing a one-dimensional inverse frequency domain conversion. The constant operation module 9 conversion operation module 96B's output array is then subjected to another one-dimensional inverse frequency domain conversion to produce the corresponding block of the frequency domain data array.

t Γΐ ^ In the compression / decompression of image data (that is, encoding / decoding), the internal memory in the processing circuit needs to access an array of 1 = = array. This frequency domain data array is usually presented as A sparse & matrix has multiple data elements that are all zero.

On page 33, this feature cannot be used. Each data element must internally record the volume of the memory resource and increase it. In contrast, in the present invention, the module is temporarily stored to temporarily store a bit. By recording the frequency domain data correspondingly in the flat bit, one can quickly use the bits of bit I to quickly determine whether the bit data element is zero, and then control the access in the body and make the image data ^ The implementation information discussed in FIGS. 4 to 16 allows the memory resources of the memory of the zero-value frequency-domain data department to be completed. Similarly, the information in Fig. 17 to also allows zero-valued frequency-domain data elements, and also makes the inverse frequency-domain conversion sparse. The process of the present invention releases a large amount of memory bandwidth requirements and The related power consumption reduces the cost and improves the efficiency. In the group, hardware circuits can be used to implement the processing unit to execute the firmware code. The circuits 30 and 80 can also be integrated into a single-function processing circuit. For example, the actual access of the memory in the frequency domain data array consumes the bandwidth requirement of the internal memory. It is a simple translation of the register surface ’to determine whether the array elements of this bit plane are zero. This $ shift method is used to access bit plane and mid plane information to judge that each frequency 2 system frequency domain data array internally records & the compression / decompression process is faster. For example, in the present invention, the use of bit-level element access does not actually occupy the internal memory, which can make the streaming scan process faster. In the eighteenth embodiment, the bit-plane element does not actually access the internal memory line. fast. Using frequency domain data array technology can compress / decompress resources in the image data, reduce the internal memory and make relevant processing circuits. In the embodiments of the present invention, each module 'or the center of the processing circuit can achieve its Features. The aforementioned process has a judgment mode in the processing circuits 3 0 and 80

Page 34 Date_No. 92134163 Revision V. Description of Invention (29) Group can be integrated into the same judgment module to control the access of non-zero data elements to internal memory during the compression / decompression process. Similarly, during the compression / decompression process, the same temporary storage module can also be used to temporarily store the bit plane. 0 The above description is only a preferred embodiment of the present invention, and all changes made equally according to the scope of the patent application of the present invention Both the modification and the modification should be covered by the patent of the present invention.

Page 35 Call No. 92134163 A_ Revision Modification Simple Description of the Schematic Brief Description of the Schematic Means -s' step. The picture is intended to show the code. Do n’t go alone. Indent the fabric. Press the fabric. Daytime image. The middle-class code flow. 1-It is the road that can work only as shown in Figure 1-2. OHL Shrinking Solution / Shrinking Material Knowledge of the image and shadow is a practice. The three diagrams and diagrams show the example of the block energy function. The implementation is all the way ^ ¾ J 11 J1 is explained. Sending a book is meant to show four picture elements. The bitmap is intended to display the array of fabrics. The flat frequency of the Yuanyuan bit frequency is 1. A data bank is stored in the middle of the road. The fourth and fourth pictures are shown in the figure. . The flat image element is shown in the middle distance. The drawing is sweeping, the stream is being repaired, the evolution path, the electric line management department, the fourth mode is temporarily stored, the first is forty, the picture is from eight to nine, and the figure is 4gl. The figure should be opposite the Luping electric element. In Figure 4, the intention is shown as the third part of the description. The sequence is sequenced, the flow is described, and the two rows are the same as the decimal place. The situation in the picture is the same as that in the example group, and the model is actually stored in the first group, the fourth in the group is saved, and the ten is stored in the temporary group. Ten diagrams and diagrams show an example of a block's ability to perform another way? | 1 JJ. The figure clearly indicates that the display version is shifted to seven levels and the ten-level chart is shifted. The time-shifted level is shifted back to the mode to save the group temporarily. The number seventy is eight.

Page 36 1 Qin No. 92134163 A_3. Revision Amendment The diagram is not intended to be simply explained. FIG. 19 is a schematic diagram of an algorithm when the processing circuit in FIG. 17 performs a one-dimensional inverse frequency domain conversion. Symbol description of the drawings 10-12 Process 14, 32, 82 Central processing unit 1 6, 3 6, 8 6 Memory access module 1 8, 3 8 Dynamic estimation module 20, 30, 80 Processing circuit 22, 40 frequency Domain conversion / quantization module 2 4 Inverse frequency domain conversion / inverse quantization module 2 6, 3 4, 8 4 External memory 2 8, 5 2, 1 0 2 Internal memory 42A Frequency domain conversion module 4 2 B Quantization Module 4 2 C Quantization Correction Module 46, 92B Data Generator 48A, 98 Judgment Module 48B Inspection Module 5 0, 1 0 0 Temporary Module 5 4, 1 0 4 Translation Control Modules 62A-62E, 66A -66L steps

Page 37

: Han F Schematic description 64 Arrow 68 Multiplexer 70 Translation controller 88 Dynamic compensation module 90 Conversion module 92A Anti-scan module 92C Variable length code solution j 94 Conversion check module 96A Constant operation module 96B Conversion operation module STP flag N-bit plane Cb Control signal A Daytime surface B Block Bi j Pixel C, Q, S, R, data 3 Ci j, Qij, Sk, BmO N-bit plane Ni j, NmO -Nm7 bit R0- R7 line M image data Al- A5 day surface 0j object data element

Page 38

Page 39

Claims (1)

t number 92134163, amendment 6, patent application scope 1. A method for encoding / decoding data, including: obtaining a data array, the data array having a plurality of data elements; processing the data array Establishing a reference array so that the reference array has a plurality of reference elements, and each reference element corresponds to a data element, and each reference element is used to represent whether the corresponding data element meets a preset value; and When the data array is written into a memory, a judgment step is performed for each data element, so that when the reference element corresponding to a data element represents that the data element meets the preset value, the data element is not written to The memory. 2. If the method of applying for the first item of the patent scope, further includes: when performing the judgment step, if the reference element corresponding to the data element represents that the data element does not meet the preset value, write the data element Into the memory. 3. If the method of applying for the first item of the patent scope, further includes: obtaining an image data; processing the image data to generate a block; performing a frequency domain conversion on the block to generate an output data; and processing the output The data generates the data array. 4. For the method in the third scope of the patent application, wherein the frequency domain conversion is a Page 40 msm 'soil No. 92134163 Amendment VI. Two-dimensional discrete cosine transform (DFT) of patent application scope 0 5. For the method of patent application scope item 3, where When the data array converted from the frequency domain generates the data array, the output data is quantized (quatization) to generate the data array. 6. If the method of applying for the first item of the patent scope, further includes: when the data array stored in the memory is to be read out, a second judgment step is performed for each reference element, so that when the The reference element indicates that when the corresponding data element matches the preset value, the memory is not read. 7. If the method of applying for item 6 of the patent scope, further includes: when performing the second judgment step, if the reference element represents that the corresponding data element does not conform to the preset value, it is stored in the memory. The data element is read out. 8. If the method of claim 6 of the scope of patent application, further includes: after performing the second judgment step on a reference element, performing an inspection step on each reference element that has not undergone the second judgment step to check Whether there is a reference element to indicate that the corresponding data element does not meet the preset value 0 Page 41, "_ No. 92134163, said Amendment •, the column table .: Array material No. 1 in the middle-aged body matriculation test together with Lei Su Yi * Examination of a rune element record, whether the test should be taken, It should be a reference, "quote, get, read the right element ^ take the prime element, when the element is not h, yuan, and get, when the former material is used to evaluate the qualifications, the value of the Marxist Lexicon is listed, value _ Each set of data should be pre-coded for each pair of material steps, and the table should be judged. The table should be compiled and replaced on the basis of the judgment. The material should be included to obtain a symbol. Participating in the elementary element, the elementary element voxel material is used to test the number of memory materials, and the memory of the resource element is to be re-referenced to take one of the examinations. There should be one each; 1 In its package element is set at every sixth, the scope of patent application 9. If the method of the scope of patent application item No. 8, it also contains: If in the inspection step, all references to the second judgment step have not been performed Each element represents that the corresponding data element meets the preset value, and then the reading of the data array is ended. 1 0. For the method of the first item of the patent application scope, in which The reference element is a one-bit piece of data to indicate whether the corresponding data element meets the preset value. 1 1. The method of item 1 in the scope of patent application, where the preset value is zero. 1 3. If the patent is applied for The method of item 12 of the scope further includes: when performing the determining step, when a reference element represents a corresponding data element that does not meet the preset value, the data element is read out from the memory. Page 42 j No. 92134163 Λ_ Amendment VI. Application for Patent Scope 1 4. The method for applying for Patent Scope Item 12 also includes: After performing the judgment step on a reference element, the judgment step has not been performed. Each reference element is subjected to a checking step to check whether there are any reference elements representing that the corresponding data element does not meet the preset value. 15. The method according to item 14 of the scope of patent application, which further includes: If during the inspection step, all reference elements that have not been subjected to the judgment step represent that their corresponding data elements meet the preset value, The reading of the data array is ended. A type of memory module with a plurality of resources, and when preset mode is broken, it makes the pre-16. A complex number temporarily has an element in one to judge the memory break, which is consistent with the material element group and each parameter. Group; the judgement is a processing circuit for encoding / decoding of set data, which includes: a data array that can be stored; wherein the data array has elements; used to store a reference array; Element, and make each reference element correspond to a data reference element used to represent whether the corresponding data element is consistent, and when the processing circuit is to write the data array to the writing module, each data element can be judged separately. When the reference element corresponding to a data element represents the data element, the data element will not be written to the memory. 1 7 · If the processing circuit of item 16 of the scope of patent application, where the judgment Page 43 Tao 1 Lion) :::: i 丨 逵 号 92134163__ 年月 q Amendment 6. When judging the patent application module, if the reference element corresponding to the data element represents that the data element does not meet the preset value When this data element is written into the memory. 1 8 · If the processing circuit of item 16 of the scope of patent application, it further includes a frequency domain conversion module for performing a frequency domain conversion on a block to generate an output data; and a quantization module To process the output data to generate the data array. 1 9 · The processing circuit of item 18 in the scope of patent application, wherein the frequency domain conversion is a two-dimensional (tw 〇-dimensi ο na 1) discrete cosine transform (DFT) ° 2 0 · as applied The processing circuit of the eighteenth aspect of the patent, wherein the quantization module generates the data array by quantizing the output data (quatizati ο η). 2 1 · If the processing circuit of the 16th item of the scope of patent application, when the processing circuit is to read out the data array stored in the memory, the judgment module may separately perform another reference for each reference element. A judgment is made that when a reference element represents that the corresponding data element conforms to the preset value, the processing circuit will not read the data element from the memory. 2 2 · If the processing circuit in the scope of patent application No. 21, where the processing Page 44 _2 fiber "Cable No. 92134163 Λ_ Revision VI. When the patent application circuit reads the data array stored in the memory, if the reference element represents its corresponding data element does not meet the preset When the value is set, the judgment module will cause the data element to be read out from the memory. 2 3. If the processing circuit of the scope of patent application No. 21, it further includes: an inspection module, the inspection module After the judging module judges a reference element, the group may perform a checking step on each reference element that has not been judged to check whether there are still reference elements representing that the corresponding data element does not meet the preset value. 2 4. If the processing circuit of item 23 of the scope of patent application is applied, after the inspection module performs an inspection, if all reference elements that have not made the judgment represent that their corresponding data elements meet the preset value, then The inspection module will cause the processing circuit to finish reading the data array. It is assumed that the item 6 1M at the circuit power J1 of the circuit will be requested. • Zero 5 2 is 6 2 Model, the stock materials should be temporarily funded by the middle yuan. One way is to set the electricity system to pre-condition the element's test symbol. Whether or not 6 1 each is the first element, and the Weifan tools and materials are used to deposit funds. For the time being, please apply to Shen Ping. If a table is used as a group, you should take the reading order and follow it. Let the road pre-arrange the power and the road should be handled. The power should be around the norm. Special group please apply for the system as controlled • Move 7 2 level Page 45 Shape-shaped thorns--thorn true [ί— ί: Page number 921341M means amendment 6. When the data elements of the patent application lean material array are applied, the order of the flat controls the temporary storage module in sequence: J 1: Knowing the preset 1 group can judge the correspondence of each data element in order. The parameter = is used to make the judgment module 2 8 · — a kind of memory | There are a plurality of places for encoding / decoding data, which are used to store-sound thick ^ Logic circuit, which contains: data elements;枓 array; where the data array contains | a number of reference elements I and temporary storage modules for storing-two test elements, each-Table 2-the reference array contains the useful material representing the corresponding f material f branch π prime Each I judges whether the module is qualified or not—the default value; when arraying, the element is judged to meet the expected element. The judgment module can be: e =: f reads the data set value in the memory; 参考; the reference element represents its corresponding data; the processing circuit will not be read by the memory; 2 2 9 · If you apply for patent scope When the module makes a judgment, if _ ^ = processing circuit, when the judgment does not meet the preset value, the two tables and their corresponding data elements are read out in the memory: broken Wu ,, Only then can the data element be processed by the patent No. 28 processing circuit, and the human element can be checked in the judgment module pair—refer to J prime \ ^ >λ;:-, v: 辕 号 92134163 (Amendment VI) After judging the scope of the patent application, a check step is performed on each reference element that has not been judged to check whether there are any reference elements. The corresponding data element does not conform to the preset value. 3 1. If the processing circuit of the 30th scope of the patent application, after the inspection module is inspected, if all reference elements that have not been judged represent that their corresponding data elements meet the preset value, then the Checking the module will cause the processing circuit to finish reading the data array. 3 2. If the processing circuit of item 28 of the patent application scope further includes a translation control module; when the processing circuit is to read the data elements of the data array in a preset order, the translation control module The translation of the temporary storage module is sequentially controlled according to the preset order, so that the judgment module can sequentially judge the reference elements corresponding to each data element. 3 3. A method for encoding / decoding data and materials, including: obtaining a frequency domain array, the frequency domain array having a plurality of frequency domain elements; providing a reference array to enable the reference The array has a plurality of reference elements, and each reference element corresponds to a frequency domain element, and each reference element is used to represent whether the corresponding frequency domain element meets a preset value; and a conversion step is performed to process the reference element. The frequency domain array generates an output array. The conversion step includes: performing a conversion check step to check whether the reference array meets a pre- Page 47 Set the array; if the reference does not match the preset array, perform a conversion operation on the frequency domain array to generate a corresponding output array; and if the reference array matches the preset array, do not match the frequency domain The array performs the conversion operation, and a constant array is used as the round-out array. 34. The method according to claim 33 of the patent application, wherein at least one of the frequency domain elements is a DC frequency domain element, and the other frequency domain elements are AC frequency domain elements. And when the reference array conforms to the preset array, the reference element corresponding to each AC frequency domain element in the reference array t represents that the parent stream frequency domain element meets the preset value. The elementary steps are: Calculate > t number has Yun ii constants, the package is constant in another number and other regular phase, enter a method, when the number is calculated, the number of elements is counted in the element element 3 Set the first column of the elementary array around the frequency range, converge, and the straight line should be aligned with the special line. If you want to apply for the root line, please refer to the line. 5 3 times 36. The method of claim 33, wherein the preset value is zero. 37. The method according to item 33 of the scope of patent application, wherein the conversion operation is an inverse discrete cosine transform. Page 48 Ί _ No. 92134163_ Years and Months Revision _ 6. Application for Patent Scope 3 8.-A processing circuit for data encoding / decoding, which includes ... a memory for storing a frequency domain array There are a plurality of frequency domain elements in the frequency domain array; a temporary storage module for temporarily storing a reference array, wherein the reference array has a plurality of reference elements, and each reference element corresponds to a Frequency domain elements, and each reference element is used to indicate whether the corresponding frequency domain element conforms to a preset value; and a conversion module is used to process the frequency domain array to generate a corresponding output array; the conversion module includes Have: A conversion operation module; and a conversion check module for checking whether the reference array conforms to a preset array; if the reference array does not conform to the preset array, the conversion check module causes the conversion operation module Perform a conversion operation on the frequency domain array to generate a corresponding output array; if the reference array matches the preset array, the conversion check module does not cause the conversion operation module to perform the conversion operation on the frequency domain array , And a constant array is used as the output array. 39. The processing circuit according to item 38 of the scope of patent application, wherein at least one of the plurality of frequency domain elements is a DC frequency domain element, and the other frequency domain elements are AC frequency domain elements; and when When the reference array matches the preset array, the reference element corresponding to each AC frequency domain element in the reference array indicates that the AC frequency domain element meets the preset value. Page 49 No. 92134163: Modification of the prime conversion, the array frequency in the time domain array, the frequency of the array is often set straight, pre-set the data, the electric modular root array array array modulus . When the matrix is calculated, the normal number g is tested. The number of the normal number of students born in the 3 parameters of the yuan should be the normal number, so that the profit group will be valued. Check the number of packages, such as the number of detections, and other conversions. There are four groups of one revolution, and the number of patent applications is 4. 1. The processing circuit of item 38 of the patent applications, where the preset value is zero. 4 2. The processing circuit according to item 38 of the scope of patent application, wherein the conversion operation module can perform an inverse discrete cosine transform. Page 50