1227595 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於一種用於拉升電晶體的鬧極控制電路， 尤指一種用於高電壓輸入之拉升電晶體的閘極控制電路。 【先前技術】 第1圖示意顯示一習知拉升電晶體電路，在此電路 中，PMOS拉升電晶體（MPU) 1之源極端（S)和其基底（B) 連接在一起，然後被連接至電源位準Vdd，電晶體MPU 1 之閘極端（G)被連接至Vss，而電晶體MPU 1之汲極端（D) 被連接至NMOS電晶體MN1之汲極端（D)，電晶體MN1 之基底（B)被連接至Vss，電晶體MN1之閘極端（G)被連接 至電源位準（Vdd)，而電晶體MN1之源極端（S)被連接至 焊墊（PAD)。在第1圖的電路中，因爲NMOS電晶體MN1 之閘極端（G)被連接至電源位準（Vdd)，所以在正常狀態 下，焊墊節點的電位將會是電晶體MN 1的源極電壓，因 此，焊墊電壓能夠高達Vdd-Vtn。如果此焊墊節點爲系統 電路板上的其中一個輸入訊號，則會產生下面的問題。 (1 )小雜訊容限：如果在電源平面上有雜訊，則能夠 據以減小焊墊電壓。如果焊墊電壓係低於其他晶片上的輸 入臨界電壓，則可能會發生系統故障。 (2)漏洩電流：因爲焊墊電壓沒有充分到達電源位 準，所以在其他晶片中會有漏洩電流，這是因爲輸入訊號 不能夠完全使其他晶片中的P Μ 0 S電晶體截止。 (2) 1227595 因此，在第1圖的電路中’焊墊電壓不能夠充分上升 到達電源電位位準，所以會因爲小雜訊容限而造成系統故 障。 第2圖示意顯示另一習知拉升電晶體電路’在此電路 中，拉升PMOS電晶體MPU 2之源極端（S)被連接至電源 位準（V d d)，電晶體Μ P U 2之閘極端（G)被連接至V s s，拉 升電晶體MPU 2之基底（Β)被連接至一 Ν井’而拉升電晶 體MPU 2之汲極端（D)被連接至焊墊。 在第2圖的電路中，介於焊墊與用於拉升電阻器之拉 升電晶體Μ P U 2的閘極端（G )間之電壓差能夠比閘極氧化 物崩潰電壓及TDDB(時變電介質崩潰）規格電壓還高。因 此，在第 2圖的電路中，會發生可靠度問題，例如 TDDB。 綜上所述，當高電壓訊號被施加於焊墊時，如果吾人 不能夠控制拉升電晶體之閘極偏壓電壓，則會產生諸如 TDDB之可靠度問題，並且由於較小的雜訊容限而導致系 統故障。 【發明內容】 本發明之目的在於克服習知拉升電晶體電路的小雜訊 容限、漏洩電流及TDDB等問題而提供一種用於拉升電阻 器用之拉升電晶體的閘極控制電路，以便將V d d位準給 予焊墊節點，以及足夠的雜訊容限，實質地去除可靠度問 題。 (3) 1227595 依據本發明，提供一種包含一用於拉升電晶體之閘極 控制電路的電路，其中，拉升電晶體之閘極端（G)被連接 至閘極控制電路，拉升電晶體之源極端（S )被連接至電源 電位，拉升電晶體之汲極端（D)被連接至焊墊節點，且拉 升電晶體之基底（B)被連接至一 N井，該電路之特徵在 於，當高電壓訊號被施加時，該閘極控制電路被用來控制 拉升電晶體之閘極偏壓電壓。 依據本發明，提供一種用於拉升電晶體之閘極控制電 路，其包含兩個η通道MOSFETs和一 p通道MOSFET。 依據本發明，提供另一種用於拉升電晶體之閘極控制 電路’其使用多級電源。 依據本發明，提供另一種用於拉升電晶體之閘極控制 電路’其包含兩個NMOS電晶體以構成二極體連接。 依據本發明，提供另一種用於拉升電晶體之閘極控制 電路’其包含雨個以上串聯之NMOS電晶體以構成二極體 連接。 依據本發明，提供另一種用於拉升電晶體之閘極控制 電路’其包含兩個PM0S電晶體以構成二極體連接。 依據本發明，提供另一種用於拉升電晶體之閘極控制 電路’其包含兩個以上串聯之PMOS電晶體以構成二極體 連接。 依據本發明，提供另一種用於拉升電晶體之閘極控制 電路’其包含兩個被動電阻器以形成一分壓器。 依據本發明，提供另一種用於拉升電晶體之閘極控制 -6- (4) 1227595 電路’其包含兩個二極體以形成一分壓器。 依據本發明，提供另一種用於拉升電晶體之閘極控制 II 5各’其包含兩組以上二極體的串級連接做爲分壓器。 依據本發明，提供另一種用於拉升電晶體之閘極控制 電路’其包含一 NMOS電晶體及一 PMOS電晶體以構成一 偏壓電路。 依據本發明，提供另一種用於拉升電晶體之閘極控制 電路’其包含兩個以上之NMOS電晶體及兩個以上之 PMOS電晶體以構成偏壓電路。 依據本發明，提供另一種用於拉升電晶體之閘極控制 電路’其包含一 NMOS電晶體及一 PMOS電晶體以構成一 反相器。 【實施方式】 現在將在下文中參照附圖來說明根據本發明之較佳實 施例。 第3圖係顯示依據本發明之包含一用於拉升電晶體之 閘極控制電路的示意電路圖，在此電路中，拉升電晶體 MPU 3之閘極端（G)被連接至閘極控制電路3 1，電晶體 MPU 3之源極端（S)被連接至電源位準（Vdd)，電晶體MPU 3之汲極端（D)被連接至焊墊（PAD)節點，且電晶體MPU 3 之基底（B)被連接至一 N井。第3圖之電路的操作爲當高 電壓訊號被施加時，閘極控制電路3 1係用來控制拉升電 晶體MPU 3之閘極偏壓電壓，也就是說，藉由閘極控制 (5) 1227595 電路3 1來控制拉升電晶體MPU 3的閘極電壓，並且電晶 體Μ P U 3的井偏壓被控制，以去除焊墊與電源位準 V d d 之間的漏洩電流。 第4圖顯示第3圖之閘極控制電路其中一實施例的示 意電路，在此電路中，閘極控制電路4 1係由兩個n通道 MOSFETs MN2 及 MN3 和一 p 通道 MOSFET MP1 所構成 的，其中，電晶體 MN2及MN3之閘極端（G)被連接至 Vdd (電源），電晶體MN2之汲極端（D)被連接至拉升電晶 體MPU 4之閘極端（G)，電晶體MN2之源極端（S)和電晶 體MN3之汲極端（D)連接在一起，電晶體MN3之源極端 (S)被連接至接地電位（GND)，並且電晶體MN2及MN3之 基底（B)也被連接至GND。再者，電晶體MP1之閘極端（G) 被連接至Vdd，電晶體MP1之源極端（S)或汲極端（D)分別 被連接至拉升電晶體MPU 4之閘極端（G)或PAD節點，端 視PAD之電壓而定，而PAD之電壓變化範圍係從零伏到 Vdd+α，並且電晶體MP1之基底（B)被連接至一 N井。 也就是說，當PAD電壓小於Vdd+ Vtp(Vtp爲電晶體MP1 的導通電壓）時，電晶體MP1將會截止，所以拉升電晶體 MPU 4的閘極端（G)電壓爲零，而當PAD電壓大於Vdd + Vtp且小於Vdd+ Vtp + α時，電晶體MP1將會導通，所 以拉升電晶體MPU 4的閘極端（G)電壓等於PAD電壓。此 外，電晶體MPU 4之源極端（S)被連接至電源位準，電晶 體MPU 4之汲極端（D)被連接至焊墊節點，且電晶體MPU 4之基底（B)被連接至一 N井。 (6) 1227595 參照第4圖，因爲電晶體Μ N 2及Μ N 3相較於電晶體 MP 1爲寬度與長度的比値非常小的電晶體，所以在正常的 狀態下，電晶體MP1係關閉的，此時，電晶體MPU 4之 閘極電壓經由NMOS電晶體MN2及MN3而被連接至接 地。但是，如果比Vdd+Vthp (Vthp爲電晶體MP1的臨 界電壓）還高的電壓被施加於PAD節點，則電晶體MPU 4 之閘極電壓將會上升到達PAD電壓，而且，吾人可以賦 予電晶體MPU 4之閘極電壓適當的尺寸及適當的偏壓。 有了此電路，在正常的狀態下，PAD電壓能夠被充分地拉 升，並且如果較高的電壓被施加於焊墊，則電晶體MPU 4 之閘極電壓將會介在PAD電壓與接地之間，因此，在 PAD節點與電晶體MPU 4之閘極電壓間的電壓差値係小 於閘極氧化物崩潰電壓。雖然PAD電壓高於可靠度規格 的限制，因爲電晶體MPU 4之閘極電壓係等於PAD節點 的電壓位準，所以沒有可靠度問題發生。 第 5圖爲本發明的另一代表性電路，其使用多級 (m u 11 i -1 e v e 1)電源，在此情況中，其中一級的電源被直接 連接至拉升電晶體之閘極端（G)。在第5圖的電路中，拉 升電晶體MPU 5之閘極端（G)被連接至VGC(其具有電源 與接地之間的電壓位準），電晶體MPU 5之源極端（S)被連 接至Vdd，電晶體MPU 5之汲極端（D)被連接至PAD節 點，且電晶體MPU 5之基底（B)被連接至N井。 在正常的狀態下，因爲拉升電晶體MPU 5之閘極端 (G)被連接至VGC，所以PAD電壓能夠經由拉升PMOS電 (7) 1227595 晶體MPU 5而被充分地拉升，並且因爲在PAD節點與電 晶體MPU 5之閘極電壓間的電壓差値係小於閘.極氧化物 崩潰電壓，所以沒有可靠度問題發生。 下面參照第6圖到第1 5圖來說明依據本發明之閘極 控制電路的實施例。 第6圖示意顯示依據本發明之閘極控制電路，其中， 使用兩個NMOS電晶體來構成二極體連接。在第6圖的電 路中，閘極控制電路61包含兩個η通道MOSFETs MN4 及MN5，在此電路中，NMOS電晶體MN5之閘極端（G)和 其汲極端（D)相連接，然後再連接至 Vdd，NMOS電晶體 MN4之閘極端（G)被連接至其汲極端（D)，而電晶體MN4 之汲極端（D)和電晶體MN5之源極端（S)相連接，然後再 連接至拉升電晶體MPU 6之閘極端（G)，電晶體MN4之源 極端（S)被連接至GND，並且電晶體MN4及MN5之基底 (B)也被連接至GND。此外，拉升電晶體MPU 6之源極端 (S)被連接至電源位準（Vdd)，電晶體MPU 6之汲極端（D) 被連接至PAD節點，且電晶體MPU 6之基底（B)被連接至 一 N井。 此時，拉升PMOS電晶體MPU 6之閘極電壓係在電 源與接地之間。和第5圖的說明相同地，PAD電壓能夠被 充分地拉升至電源位準，並且因爲在電晶體MPU 6之閘 極電壓與pAD電壓間的電壓差値係小於閘極氧化物崩潰 電壓，所以沒有可靠度問題發生。 第7圖示意顯示依據本發明之另一閘極控制電路，其 -10- (8) 1227595 中，使用兩個以上串聯的N Μ 0 S電晶體來構成二極體連 接。在第7圖的電路中，閘極控制電路71包含四個η通 道 MOSF£Ts ΜΝ6，ΜΝ7, ΜΝ8,及 ΜΝ9，在此電路中，電 晶體MN6及MN7形成一組二極體連接，且電晶體MN7 之閘極端（G)和其汲極端（D)連接在一起，然後再被連接至 Vdd，電晶體 MN6之閘極端（G)和其汲極端（D)連接在一 起，然後再被連接至電晶體MN7之源極端（S)。同時’電 晶體MN8及MN9形成另一組二極體連接，且電晶體MN9 之閘極端（G)被連接至其汲極端（D)，電晶體MN8之閘極 端（G)和其汲極端（D)連接在一起，然後再被連接至電晶體 MN9之源極端（S)，且電晶體MN8之源極端（S)被連接至 GND。此外，電晶體MN6之源極端（S)和電晶體MN9之汲 極端（D)相連接，然後再被連接至拉升電晶體MPU 7之閘 極端（G)，並且電晶體MN6，MN7，MN8,及MN9之基底（B) 一起被連接至GND。 再者，拉升電晶體MPU 7之源極端（S)被連接至電源 位準（Vdd)，電晶體MPU 7之汲極端（D)被連接至PAD， 且電晶體MPU 7之基底（B)被連接至一 N井。第7圖之電 路的操作和第6圖之電路的操作相同，所以拉升PMOS電 晶體MPU 7之閘極電壓係在電源與接地之間。同樣地， PAD電壓能夠被充分地拉升至電源位準，並且因爲在電晶 體MPU 7之閘極電壓與PAD電壓間的電壓差値係小於閘 極氧化物崩潰電壓，所以沒有可靠度問題發生。 第8圖示意顯示依據本發明之另一閘極控制電路，其 -11 - (9) 1227595 中，使用PMOS電晶體來構成二極體連接。在第8圖的電 路.中，閘極控制電路8 1包含兩個p通道.MOSFETs MP2 及Μ P 3，在此電路中，電晶體Μ P 3之閘極端（G )被連接至 其汲極端（D)，而電晶體MP3之源極端（S)被連接至Vdd， 電晶體Μ P 2之閘極端（G)被連接至其汲極端（D )，而電晶 體ΜΡ2之源極端（S)和電晶體MP3之汲極端（D)相連接， 然後再被連接至拉升電晶體MPU 8之閘極端（G)，電晶體 ΜΡ2之汲極端（D)被連接至GND，並且電晶體ΜΡ2及MP3 之基底（Β)也一起被連接至Vdd。 此外，拉升電晶體MPU 8之源極端（S)被連接至電源 位準（Vdd)，電晶體MPU 8之汲極端（D)被連接至PAD， 且電晶體MPU 8之基底（B)被連接至一 N井。第8圖之電 路的操作和第6圖之電路的操作相同，所以拉升PMOS電 晶體MPU 8之閘極電壓係在電源與接地之間。同樣地， PAD電壓能夠被充分地拉升至電源位準，並且因爲在電晶 體MPU 8之閘極電壓與PAD電壓間的電壓差値係小於閘 極氧化物崩潰電壓，所以沒有可靠度問題發生。 第9圖示意顯示依據本發明之另一閘極控制電路，其 中，使用兩個以上串聯的PMOS電晶體來構成二極體連 接。在第9圖的電路中，閘極控制電路91包含四個p通 道MOSFETs MP4，MP5，MP6,及MP7，在此電路中，電晶 體MP4及MP5形成一組二極體連接，且電晶體MP4及 MP5之閘極端（G)分別被連接至其汲極端（D)，電晶體MP5 之源極端（S)被連接至Vdd，而電晶體MP4之源極端（S)被 (10) 1227595 連接至電晶.體MP5之汲極端（D)。同時，電晶體MP6及 MP7形成另一組二極體連接，且電晶體MP6及MP7之閘 極端（G)分別被連接至其汲極端（D)，而電晶體MP6之源 極端（S)被連接至電晶體MP7之汲極端（D)，電晶體MP6 之汲極端（D)被連接至GND。此外，電晶體MP4之汲極端 (D)和電晶體MP7之源極端（S)相連接，然後再被連接至拉 升電晶體MPU 9之閘極端（G)，並且電晶體MP4，MP5, MP6,及MP7之基底（B)—起被連接至Vdd。 再者，拉升電晶體MPU 9之源極端（S)被連接至電源 位準（Vdd)，電晶體MPU 9之汲極端（D)被連接至PAD， 且電晶體MPU 9之基底（B)被連接至一 N井。第9圖之電 路的操作和第6圖之電路的操作相同，所以拉升PMOS電 晶體MPU 9之閘極電壓係在電源與接地之間。同樣地， PAD電壓能夠被充分地拉升至電源位準，並且因爲在電晶 體MPU 9之閘極電壓與PAD電壓間的電壓差値係小於閘 極氧化物崩潰電壓，所以沒有可靠度問題發生。 第1 〇圖示意顯示依據本發明之另一閘極控制電路， 其中，使用兩個被動電阻器做爲分壓器。在第10圖的電 路中，閘極控制電路1 01包含兩個電阻器 R1及R2，其 中，電阻器 R 1的第一端被連接至V d d，電阻器 R 1的第 二端和電阻器 R2的第一端相連接，然後再被連接至拉升 電晶體MPU 1 0之閘極端（G)，並且電阻器 R2的第二端 被連接至GND。 此外’拉升電晶體Μ P U 1 〇之源極端（s )被連接至電源 (11) 1227595 位準（Vdd)，電晶體MPU 10之汲極端（D)被連接至PAD， 且電晶體MPU 10之基底（B)被連接至一 N井。第10圖之 電路的操作和第6圖之電路的操作相同，所以拉升PMOS 電晶體MP U 1 0之閘極電壓係在電源與接地之間。同樣 地，PAD電壓能夠被充分地拉升至電源位準，並且因爲在 電晶體MPU 1 0之閘極電壓與PAD電壓間的電壓差値係 小於閘極氧化物崩潰電壓，所以沒有可靠度問題發生。 第1 1圖示意顯示依據本發明之另一閘極控制電路， 其中，使用兩個二極體做爲分壓器。在第1 1圖的電路 中，閘極控制電路1 1 1包含兩個二極體 D 1及D 2，其 中，二極體 D1之陽極端被連接至Vdd，二極體 D1之陰 極端和二極體 D2之陽極端相連接，然後再被連接至拉升 PMOS電晶體MPU 1 1之閘極端（G)，並且二極體 D2之陰 極端被連接至GND。 此外，拉升電晶體MPU 1 1之源極端（S)被連接至電源 位準（Vdd)，電晶體MPU 11之汲極端（D)被連接至PAD， 且電晶體MPU 11之基底（B)被連接至一 N井。第11圖之 電路的操作和第6圖之電路的操作相同，所以拉升PMOS 電晶體MPU 1 1之閘極電壓係在電源與接地之間。同樣 地，P A D電壓能夠被充分地拉升至電源位準，並且因爲在 電晶體MPU 1 1之閘極電壓與PAD電壓間的電壓差値係 小於閘極氧化物崩潰電壓，所以沒有可靠度問題發生。 第1 2圖示意顯示依據本發明之另一閘極控制電路， 其中，使用兩組以上二極體的串級連接做爲分壓器。在第 -14 - (12) 1227595 1 2圖的電路中，閘極控制電路1 2 1包含四個二極體 D 3， D4，D5,及D6，在此電路中，二極體 01及〇2形成第一 組二極體串級連接，而二極體 D 3及D 4形成第二組二極 體串級連接，並且，第一組串級連接二極體之陽極端被連 接至Vdd，第一組串級連接二極體之陰極端和第二組串級 連接二極體之陽極端相連接，然後再被連接至拉升PMOS 電晶體MPU 12之閘極端（G)，並且第二組串級連接二極 體之陰極端被連接至GND。 此外，拉升電晶體MPU 12之源極端（S)被連接至電源 位準（Vdd)，電晶體MPU 12之汲極端（D)被連接至PAD， 且電晶體MPU 12之基底（B)被連接至一 N井。第12圖之 電路的操作和第6圖之電路的操作相同，所以拉升PMOS 電晶體 MPU 1 2之閘極電壓係在電源與接地之間。同樣 地，PAD電壓能夠被充分地拉升至電源位準，並且因爲在 電晶體MPU 12之閘極電壓與PAD電壓間的電壓差値係 小於閘極氧化物崩潰電壓，所以沒有可靠度問題發生。 第1 3圖示意顯示依據本發明之另一閘極控制電路， 其中，使用一 NMOS電晶體及一 PMOS電晶體來構成偏壓 電路。在第1 3圖的電路中，閘極控制電路1 3 1包含一 PMOS電晶體MP8和一 NMOS電晶體MN10以形成二極體 連接，在此電路中，PMOS電晶體MP8之閘極端（G)和 NMOS電晶體MN10之閘極端（G)相連接，然後再連接至 拉升PMOS電晶體MPU 13之閘極端（G)，PMOS電晶體 Μ P 8之源極端（S )和其基底（B )連接在一起，然後再連接至 (13) 1227595 V d d，Ρ Μ 0 S電晶體 Μ P 8之汲極端（D )和 Ν Μ 0 S電晶體 ΜΝ10之汲極端（D)相連接，然後再連接至拉升PMOS電晶 體MPU 13之閘極端（G)，並且NMOS電晶體MN10之源 極端（S)和其基底（B)連接在一起，然後再連接至GND。 此外，拉升電晶體MPU 13之源極端（S)被連接至電源 位準（Vdd)，電晶體MPU 13之汲極端（D)被連接至PAD， 且電晶體MPU 13之基底（B)被連接至一 N井。第13圖之 電路的操作和第6圖之電路的操作相同，所以拉升PMOS 電晶體MPU 1 3之閘極電壓係在電源與接地之間。同樣 地，PAD電壓能夠被充分地拉升至電源位準，並且因爲在 電晶體MPU 13之閘極電壓與PAD電壓間的電壓差値係 小於閘極氧化物崩潰電壓，所以沒有可靠度問題發生。 第1 4圖示意顯示依據本發明之另一閘極控制電路， 其中，使用兩個以上之NMOS電晶體及兩個以上之PMOS 電晶體來構成偏壓電路。在第1 4圖的電路中，閘極控制 電路 141包含兩個 PMOS電晶體MP9及MP10和兩個 NMOS電晶體MN11及MN12，在此電路中，PMOS電晶 體MP9及MP10形成第一組串級連接，且電晶體MP9及 MP10之基底（B)和電晶體MP9之源極端（S)連接在一起， 然後再連接至Vdd，電晶體MP9之閘極端（G)被連接至其 汲極端（D)，然後再和電晶體MP 10之源極端（S)相連接。 同時，NMOS電晶體MN1 1及MN12形成第二組串級連 接，且電晶體MN11及MN12之基底（B)和電晶體MN11 之源極端（S)連接在一起，然後再連接至 GND，電晶體 (14) 1227595 MN 12之閘極端（G)被連接至其汲極端（D)，然後再和電晶 體Μ N 1 1之源極端（S )汲極端（D )相連接。再者，第一組串 級連接之電晶體ΜΡ 1 0的閘極端（G)和第二組串級連接之 電晶體ΜΝ 1 1的閘極端（G)相連接，然後再連接至拉升 PMOS電晶體MPU 14之閘極端（G)，第一組串級連接之電 晶體ΜΡ10的汲極端（D)和第二組串級連接之電晶體ΜΝ1 1 的汲極端（D)相連接，然後再連接至拉升PMOS電晶體 Μ P U 1 4之閘極端（G)。 此外，拉升電晶體MPU 14之源極端（S)被連接至電源 位準（Vdd)，電晶體MPU 14之汲極端（D)被連接至PAD， 且電晶體MPU 14之基底（B)被連接至一 N井。第14圖之 電路的操作和第6圖之電路的操作相同，所以拉升PMOS 電晶體 MPU 1 4之閘極電壓係在電源與接地之間。同樣 地，PAD電壓能夠被充分地拉升至電源位準，並且因爲在 電晶體Μ P U 1 4之閘極電壓與P A D電壓間的電壓差値係 小於閘極氧化物崩潰電壓，所以沒有可靠度問題發生。 第1 5圖示意顯示依據本發明之另一聞極控制電路， 其中，使用一 NMOS電晶體及一 PMOS電晶體來構成偏壓 電路。在第1 5圖的電路中，閘極控制電路1 5 1包含一 PMOS電晶體MP11和一 NMOS電晶體MN13，以形成一 反相器，在此電路中，電晶體MP1 1及MN13之汲極端（D) 被連接至拉升電阻器電晶體MPU 15之閘極端（G)，電晶 體MP11及MN13之閘.極端（G)被連接至Res_en，電晶體 Μ P 1 1之源極端（S )被連接至拉升電阻器電晶體Μ P U 1 5之 (15) 1227595 汲極端（D)，電晶體MN13之源極端（S)被連接至VGC ’而 VGC係本系統所使用的其中一種電源且必須低於Vdd .位 準，並且電晶體MN13之基底（B)被連接至GND ° 此外，拉升電晶體Μ P U 1 5之源極端（s )被連接至電源 位準（Vdd)，電晶體MPU 15之汲極端（D)被連接至PAD’ 且電晶體MPU 15之基底（B)被連接至一 N井。 第15圖之電路的操作如下，如果Res-en輸入爲邏 輯，，高，，，則拉升電阻器電晶體Μ P U 1 5之閘極端（G )被連 接至V G C，其具有電源與接地之間的電壓位準，而此電 路的操作和第6圖之電路的操作相同，所以拉升ρ Μ 0 S電 晶體MPU 1 5之閘極電壓係在電源與接地之間。同樣地’ PAD電壓能夠被充分地拉升至電源位準，並且因爲在電晶 體Μ P U 1 5之閘極電壓與P A D電壓間的電壓差値係小於 閘極氧化物崩潰電壓，所以沒有可靠度問題發生。如果 R e s _ e η輸入爲邏輯”低”，則拉升電晶體Μ P U 1 5之閘極端 (G)被連接至電源（Vdd)，因此，此拉升電晶體MPU 1 5不 動作。 因此，藉由閘極偏壓控制電路來控制拉升電晶體的閘 極電壓，依據本發明之用於拉升電晶體的閘極控制電路能 夠解決習知拉升電晶體電路的小雜訊容限、漏洩電流及 TDDB等問題，實質地去除可靠度問題。 故由前述本發明之閘極控制電路實施例的詳細說明可 知，本發明提供一種新穎的用於拉升電晶體之閘極控制電 路，可有效地改善習知之拉升電晶體電路的缺點，確實爲 -18- (16) 1227595 一兼具新穎性及進步性之設計’應可符合專利之申請要 件，爰依法提出申請。 【圖式簡單說明】 爲使 貴審查委員能夠進一步瞭解本發明之優點、 特徵及其他目的，茲附以圖式詳細說明於下。 圖式部分： 第1圖係示意顯示一習知拉升電晶體電路之電路圖。 鲁 第2圖係示意顯示另一習知拉升電晶體電路之電路 圖。 第3圖係示意顯示依據本發明之代表性電路的電路 圖。 桌4 Η係不思威不桌3圖之鬧極控制電路其中一實施 例的電路圖。 第5圖係示意顯示使用多級電源之依據本發明之另一 代表性電路的電路圖。 _ 第6圖係顯示依據本發明之閘極控制電路的示意電路 圖。 第7圖係顯示依據本發明之另一閘極控制電路的示意 電路圖。 第8圖係顯示依據本發明之另一閘極控制電路的示爲 電路圖。 第9圖係顯示依據本發明之另一閘極控制電路的示思 電路圖。 -19- (17) 1227595 第1 〇圖係顯示依據本發明之另一閘極控制電路的斧: 意電路圖。 第1 1圖係顯示依據本發明之另一閘極控制電路的斧: 意電路圖。 第1 2圖係顯示依據本發明之另一閘極控制電路的示 意電路圖。 第1 3圖係顯示依據本發明之另一閘極控制電路的示 意電路圖。 第1 4圖係顯示依據本發明之另一閘極控制電路的示 意電路圖。 第1 5圖係顯示依據本發明之另一閘極控制電路的示 意電路圖。 圖號部分 31， 41， 61， 71， 81， 91， 101， 111， 121， 131， 141， 151 閘極控制電路 MPU1-MPU15 拉升電晶體 ΜΝ1-ΜΝ13 NMOS 電晶體 ΜΡ1-ΜΡ1 1 PMOS 電晶體 Rl，R2電阻器 D卜D6二極體 -20-1227595 (1) 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to an alarm control circuit for pulling up a transistor, and more particularly to a gate control circuit for pulling up a transistor for high voltage input . [Prior art] Figure 1 schematically shows a conventional pull-up transistor circuit. In this circuit, the source terminal (S) of the PMOS pull-up transistor (MPU) 1 and its base (B) are connected together, and then Connected to the power level Vdd, the gate terminal (G) of transistor MPU 1 is connected to Vss, and the drain terminal (D) of transistor MPU 1 is connected to the drain terminal (D) of NMOS transistor MN1. The base (B) of MN1 is connected to Vss, the gate terminal (G) of transistor MN1 is connected to the power level (Vdd), and the source terminal (S) of transistor MN1 is connected to the pad (PAD). In the circuit of Figure 1, because the gate terminal (G) of the NMOS transistor MN1 is connected to the power level (Vdd), under normal conditions, the potential of the pad node will be the source of the transistor MN 1 Voltage, therefore, the pad voltage can be as high as Vdd-Vtn. If this pad node is one of the input signals on the system board, the following problems will occur. (1) Small noise tolerance: If there is noise on the power plane, the pad voltage can be reduced accordingly. If the pad voltage is lower than the input threshold voltage on other wafers, a system failure may occur. (2) Leakage current: Because the pad voltage does not reach the power level sufficiently, there will be leakage current in other chips. This is because the input signal cannot completely turn off the PMOS transistor in other chips. (2) 1227595 Therefore, in the circuit of Figure 1, the 'pad voltage cannot rise sufficiently to reach the power supply potential level, so a small noise margin will cause system failure. Figure 2 schematically shows another conventional pull-up transistor circuit. In this circuit, the source terminal (S) of the pull-up PMOS transistor MPU 2 is connected to the power level (V dd), and the transistor M PU 2 The gate terminal (G) is connected to V ss, the substrate (B) of the pull-up transistor MPU 2 is connected to an N well 'and the drain terminal (D) of the pull-up transistor MPU 2 is connected to the pad. In the circuit of FIG. 2, the voltage difference between the pad and the gate terminal (G) of the pull-up transistor M PU 2 for the pull-up resistor can be greater than the gate oxide breakdown voltage and TDDB (time-varying). Dielectric breakdown) Specification voltage is still high. Therefore, reliability problems such as TDDB occur in the circuit of Figure 2. In summary, when a high voltage signal is applied to the pad, if we cannot control the gate bias voltage of the transistor, it will cause reliability issues such as TDDB, and due to the small noise capacity This can lead to system failure. [Summary of the Invention] The purpose of the present invention is to overcome the problems of small noise tolerance, leakage current, and TDDB of conventional pull-up transistor circuits, and to provide a gate control circuit for a pull-up transistor for a pull-up resistor. In order to give the V dd level to the pad node and sufficient noise margin, the reliability problem is substantially removed. (3) 1227595 According to the present invention, there is provided a circuit including a gate control circuit for pulling up a transistor, wherein a gate terminal (G) of the pulling up transistor is connected to the gate control circuit to pull up the transistor The source terminal (S) is connected to the power supply potential, the drain terminal (D) of the pull-up transistor is connected to the pad node, and the substrate (B) of the pull-up transistor is connected to an N-well. Characteristics of the circuit The reason is that when a high voltage signal is applied, the gate control circuit is used to control the gate bias voltage of the transistor. According to the present invention, a gate control circuit for a pull-up transistor is provided, which includes two n-channel MOSFETs and a p-channel MOSFET. According to the present invention, there is provided another gate control circuit for pulling up a transistor, which uses a multi-stage power supply. According to the present invention, another gate control circuit for pulling up a transistor is provided, which comprises two NMOS transistors to form a diode connection. According to the present invention, there is provided another gate control circuit for pulling up a transistor, which comprises more than NMOS transistors connected in series to form a diode connection. According to the present invention, there is provided another gate control circuit for pulling up a transistor, which comprises two PMOS transistors to form a diode connection. According to the present invention, there is provided another gate control circuit for pulling up a transistor, which includes two or more PMOS transistors connected in series to form a diode connection. According to the present invention, there is provided another gate control circuit for pulling up a transistor, which includes two passive resistors to form a voltage divider. According to the present invention, there is provided another gate control for a transistor 6- (4) 1227595 circuit ', which includes two diodes to form a voltage divider. According to the present invention, another gate control II 5 for pulling up a transistor is provided, each of which includes a cascade connection of two or more diodes as a voltage divider. According to the present invention, there is provided another gate control circuit for pulling up a transistor, which includes an NMOS transistor and a PMOS transistor to form a bias circuit. According to the present invention, another gate control circuit for pulling up a transistor is provided, which comprises two or more NMOS transistors and two or more PMOS transistors to form a bias circuit. According to the present invention, there is provided another gate control circuit for pulling up a transistor, which includes an NMOS transistor and a PMOS transistor to form an inverter. [Embodiment] A preferred embodiment according to the present invention will now be described below with reference to the drawings. FIG. 3 is a schematic circuit diagram showing a gate control circuit including a pull-up transistor according to the present invention. In this circuit, the gate terminal (G) of the pull-up transistor MPU 3 is connected to the gate control circuit. 3 1. The source terminal (S) of transistor MPU 3 is connected to the power level (Vdd), the drain terminal (D) of transistor MPU 3 is connected to the pad (PAD) node, and the base of transistor MPU 3 (B) is connected to an N well. The operation of the circuit in FIG. 3 is that when a high voltage signal is applied, the gate control circuit 31 is used to control the gate bias voltage of the pull-up transistor MPU 3, that is, by the gate control (5 1227595 Circuit 31 controls the gate voltage of the transistor MPU 3 and the well bias of the transistor M PU 3 is controlled to remove the leakage current between the pad and the power level V dd. Fig. 4 shows a schematic circuit of one embodiment of the gate control circuit of Fig. 3. In this circuit, the gate control circuit 41 is composed of two n-channel MOSFETs MN2 and MN3 and a p-channel MOSFET MP1. Among them, the gate terminal (G) of the transistor MN2 and MN3 is connected to Vdd (power supply), and the drain terminal (D) of the transistor MN2 is connected to the gate terminal (G) of the pull-up transistor MPU 4, and the transistor MN2 The source terminal (S) and the drain terminal (D) of transistor MN3 are connected together. The source terminal (S) of transistor MN3 is connected to the ground potential (GND), and the bases (B) of transistors MN2 and MN3 are Connected to GND. In addition, the gate terminal (G) of transistor MP1 is connected to Vdd, and the source terminal (S) or drain terminal (D) of transistor MP1 is connected to the gate terminal (G) or PAD of the transistor MPU 4 respectively. The node and end depend on the voltage of the PAD, and the voltage range of the PAD is from zero volts to Vdd + α, and the substrate (B) of the transistor MP1 is connected to an N-well. In other words, when the PAD voltage is less than Vdd + Vtp (Vtp is the on-voltage of transistor MP1), transistor MP1 will be turned off, so the voltage at the gate (G) of transistor MPU 4 is raised to zero, and when the PAD voltage When Vdd + Vtp is larger than Vdd + Vtp + α, the transistor MP1 will be turned on, so the voltage at the gate (G) of the transistor MPU 4 is pulled up to be equal to the PAD voltage. In addition, the source terminal (S) of the transistor MPU 4 is connected to the power supply level, the drain terminal (D) of the transistor MPU 4 is connected to the pad node, and the base (B) of the transistor MPU 4 is connected to a Well N. (6) 1227595 Referring to FIG. 4, since the transistors MN 2 and MN 3 are transistors with a very small ratio of width to length compared to the transistor MP 1, the transistor MP1 is in a normal state. When closed, the gate voltage of transistor MPU 4 is connected to ground via NMOS transistors MN2 and MN3. However, if a voltage higher than Vdd + Vthp (Vthp is the critical voltage of transistor MP1) is applied to the PAD node, the gate voltage of transistor MPU 4 will rise to reach the PAD voltage, and we can give the transistor The MPU 4 has a proper gate voltage and proper bias voltage. With this circuit, the PAD voltage can be fully pulled up under normal conditions, and if a higher voltage is applied to the pad, the gate voltage of the transistor MPU 4 will be between the PAD voltage and ground Therefore, the voltage difference between the gate voltage of the PAD node and the transistor MPU 4 is smaller than the gate oxide breakdown voltage. Although the PAD voltage is higher than the limit of the reliability specification, since the gate voltage of the transistor MPU 4 is equal to the voltage level of the PAD node, no reliability problem occurs. FIG. 5 is another representative circuit of the present invention, which uses a multi-stage (mu 11 i -1 eve 1) power supply. In this case, one of the power supplies is directly connected to the gate terminal of a pull-up transistor (G ). In the circuit in Figure 5, the gate terminal (G) of the pull-up transistor MPU 5 is connected to VGC (which has a voltage level between power and ground), and the source terminal (S) of the transistor MPU 5 is connected To Vdd, the drain terminal (D) of the transistor MPU 5 is connected to the PAD node, and the substrate (B) of the transistor MPU 5 is connected to the N well. In the normal state, because the gate terminal (G) of the pull-up transistor MPU 5 is connected to VGC, the PAD voltage can be fully pulled up by pulling up the PMOS power (7) 1227595 crystal MPU 5, and because The voltage difference between the gate voltage of the PAD node and the transistor MPU 5 is smaller than the gate-electrode breakdown voltage, so no reliability problem occurs. Embodiments of the gate control circuit according to the present invention will be described below with reference to FIGS. 6 to 15. FIG. 6 schematically shows a gate control circuit according to the present invention, in which two NMOS transistors are used to form a diode connection. In the circuit of FIG. 6, the gate control circuit 61 includes two n-channel MOSFETs MN4 and MN5. In this circuit, the gate terminal (G) and the drain terminal (D) of the NMOS transistor MN5 are connected, and then Connected to Vdd, the gate terminal (G) of NMOS transistor MN4 is connected to its drain terminal (D), while the drain terminal (D) of transistor MN4 and the source terminal (S) of transistor MN5 are connected, and then connected To the gate terminal (G) of the pull-up transistor MPU 6, the source terminal (S) of the transistor MN4 is connected to GND, and the substrate (B) of the transistor MN4 and MN5 is also connected to GND. In addition, the source terminal (S) of the pull-up transistor MPU 6 is connected to the power level (Vdd), the drain terminal (D) of the transistor MPU 6 is connected to the PAD node, and the base (B) of the transistor MPU 6 Connected to an N-well. At this time, the gate voltage of the pulled-up PMOS transistor MPU 6 is between the power source and the ground. As in the description of Figure 5, the PAD voltage can be sufficiently pulled up to the power supply level, and because the voltage difference between the gate voltage of the transistor MPU 6 and the pAD voltage is smaller than the gate oxide breakdown voltage, So no reliability issues occurred. FIG. 7 schematically shows another gate control circuit according to the present invention. In -10- (8) 1227595, two or more N M 0 S transistors connected in series are used to form a diode connection. In the circuit of FIG. 7, the gate control circuit 71 includes four n-channel MOSF £ Ts MN6, MN7, MN8, and MN9. In this circuit, the transistors MN6 and MN7 form a group of diode connections, and the The gate terminal (G) and the drain terminal (D) of the crystal MN7 are connected together and then connected to Vdd, and the gate terminal (G) and the drain terminal (D) of the transistor MN6 are connected together and then connected again. To the source terminal (S) of transistor MN7. At the same time, transistor MN8 and MN9 form another set of diode connections, and the gate terminal (G) of transistor MN9 is connected to its drain terminal (D), the gate terminal (G) of transistor MN8 and its drain terminal ( D) Connected together, and then connected to the source terminal (S) of transistor MN9, and the source terminal (S) of transistor MN8 is connected to GND. In addition, the source terminal (S) of transistor MN6 and the drain terminal (D) of transistor MN9 are connected, and then connected to the gate terminal (G) of pull-up transistor MPU 7, and the transistors MN6, MN7, and MN8 , And the base (B) of MN9 are connected to GND together. Furthermore, the source terminal (S) of the transistor MPU 7 is pulled up to the power level (Vdd), the drain terminal (D) of the transistor MPU 7 is connected to the PAD, and the base (B) of the transistor MPU 7 is connected Connected to an N-well. The operation of the circuit of Fig. 7 is the same as that of the circuit of Fig. 6, so the gate voltage of the pull-up PMOS transistor MPU 7 is between power and ground. Similarly, the PAD voltage can be fully pulled up to the power level, and because the voltage difference between the gate voltage of the transistor MPU 7 and the PAD voltage is smaller than the gate oxide breakdown voltage, no reliability problem occurs . FIG. 8 schematically shows another gate control circuit according to the present invention. In -11-(9) 1227595, a PMOS transistor is used to form a diode connection. In the circuit of FIG. 8, the gate control circuit 81 includes two p-channels. MOSFETs MP2 and MP3. In this circuit, the gate terminal (G) of the transistor MP3 is connected to its drain terminal. (D), while the source terminal (S) of transistor MP3 is connected to Vdd, the gate terminal (G) of transistor MP 2 is connected to its drain terminal (D), and the source terminal (S) of transistor MP2 Connected to the drain terminal (D) of transistor MP3, and then connected to the gate terminal (G) of pull-up transistor MPU 8, the drain terminal (D) of transistor MP2 is connected to GND, and transistor MP2 and The base (MP) of MP3 is also connected to Vdd. In addition, the source terminal (S) of the pull-up transistor MPU 8 is connected to the power level (Vdd), the drain terminal (D) of the transistor MPU 8 is connected to the PAD, and the base (B) of the transistor MPU 8 is connected Connected to an N-well. The operation of the circuit of Fig. 8 is the same as that of the circuit of Fig. 6, so the gate voltage of the pull-up PMOS transistor MPU 8 is between power and ground. Similarly, the PAD voltage can be fully pulled up to the power level, and because the voltage difference between the gate voltage of the transistor MPU 8 and the PAD voltage is smaller than the gate oxide breakdown voltage, no reliability problem occurs . Fig. 9 schematically shows another gate control circuit according to the present invention, in which two or more PMOS transistors are connected in series to form a diode connection. In the circuit of FIG. 9, the gate control circuit 91 includes four p-channel MOSFETs MP4, MP5, MP6, and MP7. In this circuit, the transistors MP4 and MP5 form a group of diode connections, and the transistor MP4 The gate terminal (G) of MP5 is connected to its drain terminal (D), the source terminal (S) of transistor MP5 is connected to Vdd, and the source terminal (S) of transistor MP4 is connected to (10) 1227595. The drain of the transistor MP5 (D). At the same time, transistors MP6 and MP7 form another set of diode connections, and the gate terminals (G) of transistors MP6 and MP7 are connected to their drain terminals (D), while the source terminal (S) of transistor MP6 is Connected to the drain terminal (D) of transistor MP7, and the drain terminal (D) of transistor MP6 is connected to GND. In addition, the drain terminal (D) of the transistor MP4 and the source terminal (S) of the transistor MP7 are connected, and then connected to the gate terminal (G) of the pull-up transistor MPU 9, and the transistors MP4, MP5, MP6 , And the substrate (B) of MP7 are connected to Vdd. Furthermore, the source terminal (S) of the transistor MPU 9 is pulled up to the power level (Vdd), the drain terminal (D) of the transistor MPU 9 is connected to the PAD, and the base (B) of the transistor MPU 9 is connected Connected to an N-well. The operation of the circuit of Fig. 9 is the same as that of the circuit of Fig. 6, so the gate voltage of the pull-up PMOS transistor MPU 9 is between power and ground. Similarly, the PAD voltage can be fully pulled up to the power level, and because the voltage difference between the gate voltage of the transistor MPU 9 and the PAD voltage is smaller than the gate oxide breakdown voltage, no reliability problem occurs . FIG. 10 schematically shows another gate control circuit according to the present invention, in which two passive resistors are used as voltage dividers. In the circuit of FIG. 10, the gate control circuit 101 includes two resistors R1 and R2, wherein the first end of the resistor R1 is connected to V dd, the second end of the resistor R1 and the resistor The first terminal of R2 is connected, and then connected to the gate terminal (G) of the pull-up transistor MPU 10, and the second terminal of the resistor R2 is connected to GND. In addition, the source terminal (s) of the pull-up transistor M PU 1 〇 is connected to the power source (11) 1227595 level (Vdd), the drain terminal (D) of the transistor MPU 10 is connected to the PAD, and the transistor MPU 10 The base (B) is connected to an N-well. The operation of the circuit of FIG. 10 is the same as the operation of the circuit of FIG. 6, so the gate voltage of the pull-up PMOS transistor MPU 10 is between the power source and the ground. Similarly, the PAD voltage can be fully pulled up to the power level, and because the voltage difference between the gate voltage of the transistor MPU 10 and the PAD voltage is smaller than the gate oxide breakdown voltage, there is no reliability problem occur. FIG. 11 schematically shows another gate control circuit according to the present invention, in which two diodes are used as a voltage divider. In the circuit of FIG. 11, the gate control circuit 1 1 1 includes two diodes D 1 and D 2, wherein an anode terminal of the diode D1 is connected to Vdd, a cathode terminal of the diode D1 and The anode terminal of the diode D2 is connected, and then connected to the gate terminal (G) of the pull-up PMOS transistor MPU 1 1, and the cathode terminal of the diode D2 is connected to GND. In addition, the source terminal (S) of the transistor MPU 1 1 is connected to the power supply level (Vdd), the drain terminal (D) of the transistor MPU 11 is connected to the PAD, and the substrate (B) of the transistor MPU 11 is connected. Connected to an N-well. The operation of the circuit of FIG. 11 is the same as the operation of the circuit of FIG. 6, so the gate voltage of the pull-up PMOS transistor MPU 1 1 is between power and ground. Similarly, the PAD voltage can be fully pulled up to the power level, and because the voltage difference between the gate voltage of the transistor MPU 1 and the PAD voltage is smaller than the gate oxide breakdown voltage, there is no reliability problem occur. FIG. 12 schematically shows another gate control circuit according to the present invention, in which a cascade connection of two or more diodes is used as a voltage divider. In the circuit of Figs. -14-(12) 1227595 12, the gate control circuit 1 2 1 includes four diodes D 3, D4, D5, and D6. In this circuit, diodes 01 and 0 2 forms a first group of diode cascade connections, while diodes D 3 and D 4 form a second group of diode cascade connections, and the anode end of the first group of cascade connected diodes is connected to Vdd The cathode terminal of the first group of cascaded diodes and the anode terminal of the second group of cascaded diodes are connected, and then connected to the gate terminal (G) of the pull-up PMOS transistor MPU 12, and the first The cathode terminals of the two series-connected diodes are connected to GND. In addition, the source terminal (S) of the pull-up transistor MPU 12 is connected to the power level (Vdd), the drain terminal (D) of the transistor MPU 12 is connected to the PAD, and the base (B) of the transistor MPU 12 is Connected to an N-well. The operation of the circuit of Fig. 12 is the same as that of the circuit of Fig. 6, so the gate voltage of the pull-up PMOS transistor MPU 1 2 is between power and ground. Similarly, the PAD voltage can be fully pulled up to the power level, and because the voltage difference between the gate voltage of the transistor MPU 12 and the PAD voltage is smaller than the gate oxide breakdown voltage, no reliability problem occurs . FIG. 13 schematically shows another gate control circuit according to the present invention, in which an NMOS transistor and a PMOS transistor are used to form a bias circuit. In the circuit of FIG. 13, the gate control circuit 131 includes a PMOS transistor MP8 and an NMOS transistor MN10 to form a diode connection. In this circuit, the gate terminal (G) of the PMOS transistor MP8 Connected to the gate terminal (G) of the NMOS transistor MN10, and then connected to the gate terminal (G) of the PMOS transistor MPU 13, the source terminal (S) of the PMOS transistor MP 8 and its base (B) Connected together, and then connected to the (13) 1227595 V dd, the drain terminal (D) of the P M 0 S transistor MP 8 and the drain terminal (D) of the NM 0 S transistor MN10, and then connected The gate terminal (G) of the PMOS transistor MPU 13 is pulled up, and the source terminal (S) of the NMOS transistor MN10 and its base (B) are connected together, and then connected to GND. In addition, the source terminal (S) of the pull-up transistor MPU 13 is connected to the power level (Vdd), the drain terminal (D) of the transistor MPU 13 is connected to the PAD, and the base (B) of the transistor MPU 13 is connected Connected to an N-well. The operation of the circuit of FIG. 13 is the same as that of the circuit of FIG. 6, so the gate voltage of the pull-up PMOS transistor MPU 1 3 is between power and ground. Similarly, the PAD voltage can be fully pulled up to the power level, and since the voltage difference between the gate voltage of the transistor MPU 13 and the PAD voltage is smaller than the gate oxide breakdown voltage, no reliability problem occurs . FIG. 14 schematically shows another gate control circuit according to the present invention, in which two or more NMOS transistors and two or more PMOS transistors are used to form a bias circuit. In the circuit of FIG. 14, the gate control circuit 141 includes two PMOS transistors MP9 and MP10 and two NMOS transistors MN11 and MN12. In this circuit, the PMOS transistors MP9 and MP10 form a first group of cascades. Connected, and the bases (B) of transistors MP9 and MP10 and the source terminal (S) of transistor MP9 are connected together, and then connected to Vdd, and the gate terminal (G) of transistor MP9 is connected to its drain terminal (D ), And then connected to the source terminal (S) of the transistor MP 10. At the same time, the NMOS transistors MN1 1 and MN12 form a second group of cascade connections, and the bases (B) of the transistors MN11 and MN12 and the source terminal (S) of the transistor MN11 are connected together, and then connected to GND. (14) 1227595 The gate terminal (G) of MN 12 is connected to its drain terminal (D), and then connected to the source terminal (S) of the transistor MN 1 1 (D). Furthermore, the gate terminal (G) of the first cascaded transistor MP 10 is connected to the gate terminal (G) of the second cascaded transistor MN 1 1 and then connected to the pull-up PMOS The gate terminal (G) of the transistor MPU 14, the drain terminal (D) of the first cascaded transistor MP10 and the drain terminal (D) of the second cascaded transistor MN1 1 are connected, and then Connected to the gate terminal (G) of the pull-up PMOS transistor M PU 1 4. In addition, the source terminal (S) of the pull-up transistor MPU 14 is connected to the power supply level (Vdd), the drain terminal (D) of the transistor MPU 14 is connected to the PAD, and the base (B) of the transistor MPU 14 is connected Connected to an N-well. The operation of the circuit of Fig. 14 is the same as that of the circuit of Fig. 6, so the gate voltage of the pull-up PMOS transistor MPU 1 4 is between power and ground. Similarly, the PAD voltage can be sufficiently pulled up to the power level, and because the voltage difference between the gate voltage of the transistor M PU 1 and the PAD voltage is smaller than the gate oxide breakdown voltage, there is no reliability The problem occurred. FIG. 15 schematically shows another snout control circuit according to the present invention, in which an NMOS transistor and a PMOS transistor are used to form a bias circuit. In the circuit of FIG. 15, the gate control circuit 15 includes a PMOS transistor MP11 and an NMOS transistor MN13 to form an inverter. In this circuit, the drain terminals of the transistors MP1 1 and MN13 (D) Connected to the gate terminal (G) of the pull-up resistor transistor MPU 15, and gates of the transistor MP11 and MN13. The terminal (G) is connected to Res_en, the source terminal of the transistor MP 1 1 (S) Connected to the pull-up resistor transistor MU PU 1 (15) 1227595 Drain terminal (D), the source terminal (S) of transistor MN13 is connected to VGC ', and VGC is one of the power sources used in this system and Must be lower than Vdd. Level, and the base (B) of transistor MN13 is connected to GND. In addition, the source terminal (s) of the pull-up transistor M PU 1 5 is connected to the power level (Vdd), the transistor The drain terminal (D) of the MPU 15 is connected to PAD 'and the base (B) of the transistor MPU 15 is connected to an N-well. The operation of the circuit of FIG. 15 is as follows. If the Res-en input is logic, high, and high, the gate terminal (G) of the pull-up resistor transistor M PU 1 5 is connected to VGC, which has a power source and a ground. The operation of this circuit is the same as the operation of the circuit of Fig. 6, so the gate voltage of the ρ Μ 0 S transistor MPU 1 5 is raised between the power source and the ground. Similarly, the PAD voltage can be fully pulled up to the power level, and because the voltage difference between the gate voltage of the transistor MU PU 5 and the PAD voltage is smaller than the gate oxide breakdown voltage, there is no reliability The problem occurred. If the R e s _ e η input is logic "low", the gate terminal (G) of the pull-up transistor MPU 1 5 is connected to the power source (Vdd), and therefore, the pull-up transistor MPU 1 5 does not operate. Therefore, the gate voltage of the pull-up transistor is controlled by the gate bias control circuit. The gate control circuit for the pull-up transistor according to the present invention can solve the small noise capacity of the conventional pull-up transistor circuit. Limits, leakage currents, and TDDB issues, virtually eliminating reliability issues. Therefore, from the detailed description of the foregoing embodiment of the gate control circuit of the present invention, it can be known that the present invention provides a novel gate control circuit for a pull-up transistor, which can effectively improve the shortcomings of the conventional pull-up transistor circuit. For -18- (16) 1227595, a design that is both novel and progressive should meet the requirements for patent application, and submit an application in accordance with the law. [Brief Description of the Drawings] In order to allow your reviewers to further understand the advantages, features, and other purposes of the present invention, the drawings are detailed below. Schematic part: Figure 1 is a schematic diagram showing a conventional pull-up transistor circuit. Figure 2 is a schematic diagram showing another conventional pull-up transistor circuit. Fig. 3 is a circuit diagram schematically showing a representative circuit according to the present invention. Table 4 is a circuit diagram of one embodiment of the alarm control circuit shown in Figure 3 and Table 3. Fig. 5 is a circuit diagram schematically showing another representative circuit according to the present invention using a multi-stage power supply. _ Figure 6 is a schematic circuit diagram showing a gate control circuit according to the present invention. Fig. 7 is a schematic circuit diagram showing another gate control circuit according to the present invention. Fig. 8 is a circuit diagram showing another gate control circuit according to the present invention. Fig. 9 is a schematic circuit diagram showing another gate control circuit according to the present invention. -19- (17) 1227595 Figure 10 shows an axe: intentional circuit diagram of another gate control circuit according to the present invention. FIG. 11 is a circuit diagram showing another gate control circuit according to the present invention. Fig. 12 is a schematic circuit diagram showing another gate control circuit according to the present invention. Fig. 13 is a schematic circuit diagram showing another gate control circuit according to the present invention. Fig. 14 is a schematic circuit diagram showing another gate control circuit according to the present invention. Fig. 15 is a schematic circuit diagram showing another gate control circuit according to the present invention. Part No. 31, 41, 61, 71, 81, 91, 101, 111, 121, 131, 141, 151 Gate control circuit MPU1-MPU15 Pull-up transistor MN1-MN13 NMOS transistor MP1-MP1 1 PMOS transistor Rl, R2 resistor D1 D6 diode -20-