1226747 案號 92126408 年 月 曰 修正 五、發明說明（1) 尤指一種低雜訊放大器。 發明所屬之技術領域 本發明提供一種放大器 先前技術 低雜訊放大器已被使用於廣泛的領域中，如無線網路以 及手機之無線電頻率（RF )通訊系統中。改進並提升低雜 訊放大器之效能和可靠性及降低其成本為當前業界之趨 勢。 圖一為傳統低雜訊放，大器1 0的示意圖，圖一中以一虛線 將晶片内（on - ch i p )以及晶片.外（〇 f f - ch i ρ )區分開來。低 雜訊放大器10包含有一電晶體22，電晶體22具有一汲 極，經由第一電感器26連於一操作電壓Vdd。一 RF輸入訊 號（RF input signal)經由一第二電感器2 8連接至電晶體 2 2之閘極，而低雜訊放大器1 0之輸出訊號經由電晶體2 2 之汲極輸出。電晶體2 2之閘極連接於一電流鏡電路2 4， 電流鏡電路2 4經由一電阻器提供一偏壓電流。電晶體2 2 之源極經過晶片内之節點Q而連接至接地1 2，晶片内節點 Q亦使電流鏡電路2 4接地。低雜訊放大器1 0之操作方法 為：經由RF輸入節點輸入之RF輸入訊號會根據操作電壓 Vdd、偏壓電流及電感器26、28之電感而放大。 依據CMOS製程製作低雜訊放大器1 0時，除了一晶片外接 1226747 案號 92126408 年月日 修正 五、發明說明（2) 地1 2以外，上述所有元件皆設置於晶片内·。請參考美國 專利號弟5，5 7 4，4 0 5號’其已完整敛述晶片内兀件在類似 圖一所示之低雜訊放大器中的優點。然而在節點Q之連接 會導致較差的絕緣效果及穩定度，且對雜訊較敏感。其 他缺點還包括具有一相對較窄之頻寬以及必須設置電感 器2 8而增加晶片面積。 在美國專利號第6，1 9 8，3 5 2號中描述了另一低雜訊放大 器，包含一電阻，取代低雜訊放大器1 0中的電感器2 8。 其缺點為，該電阻在直流模式下，會造成相對應之功率 損耗，電晶體2 2之汲極電壓的不穩定，以及雜訊的增 加0 發明内容 本發明主要目的在於提供一種改良結構及較佳製造方法 之低雜訊放大器。 本發明之低雜訊放大器包含有第一及第二電晶體、電感 器以及電阻器。該第一電晶體之閘極係連接於一輸入節 點（R F i n p u t η 〇 d e )，而其源極連接於一第一接地節點。 該第二電晶體之源極連接於該第一電晶體之汲極，而第 二電晶體之沒極連接於一輸出節點（RFoutput node)， 同時該第二電晶體之閘極連接於第一偏壓。本發明之低 雜訊放大器另包含有一電流鏡電路，連接於第一電晶體1226747 Case No. 92126408 Amendment V. Description of the invention (1) Especially a low noise amplifier. FIELD OF THE INVENTION The present invention provides an amplifier. Prior art Low noise amplifiers have been used in a wide range of fields, such as wireless networks and radio frequency (RF) communication systems for mobile phones. Improving and enhancing the performance and reliability of low-noise amplifiers and reducing their costs are current trends in the industry. Figure 1 is a schematic diagram of a conventional low-noise amplifier, the amplifier 10. In Figure 1, a dashed line is used to distinguish the inside (on-ch i p) and the outside (0 f f-ch i) of the chip. The low-noise amplifier 10 includes a transistor 22 having a drain and connected to an operating voltage Vdd via a first inductor 26. An RF input signal is connected to the gate of the transistor 22 through a second inductor 28, and the output signal of the low noise amplifier 10 is output through the drain of the transistor 22. The gate of the transistor 22 is connected to a current mirror circuit 24. The current mirror circuit 24 provides a bias current through a resistor. The source of the transistor 2 2 is connected to the ground 12 through the node Q in the chip, and the node Q in the chip also grounds the current mirror circuit 2 4. The operation method of the low noise amplifier 10 is: The RF input signal input through the RF input node is amplified according to the operating voltage Vdd, the bias current, and the inductance of the inductors 26 and 28. When manufacturing a low noise amplifier 10 according to the CMOS process, except for a chip externally connected to 1226747 case No. 92126408. Rev. 5. Description of the invention (2) Ground 12. All the above components are placed in the chip. Please refer to U.S. Patent No. 5,5 7,4,405, which has a complete description of the advantages of the chip components in the low noise amplifier similar to that shown in Figure 1. However, the connection at node Q will result in poor insulation effect and stability, and it is more sensitive to noise. Other disadvantages include having a relatively narrow bandwidth and the need to place inductors 28 to increase the chip area. Another low-noise amplifier is described in U.S. Patent No. 6,19,3,52, which includes a resistor instead of the inductor 28 in the low-noise amplifier 10. The disadvantages are that the resistor will cause corresponding power loss in the DC mode, the instability of the drain voltage of the transistor 22, and the increase of noise. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide an improved structure and a relatively low Low noise amplifier with best manufacturing method. The low-noise amplifier of the present invention includes first and second transistors, an inductor, and a resistor. The gate of the first transistor is connected to an input node (R F i n p u t η 〇 d e), and its source is connected to a first ground node. The source of the second transistor is connected to the drain of the first transistor, and the terminal of the second transistor is connected to an RF output node, and the gate of the second transistor is connected to the first transistor. bias. The low-noise amplifier of the present invention further includes a current mirror circuit connected to the first transistor.
第7頁 1226747 案號 92126408 五、發明說明（3) 年 月 修正 之閘極，用來提供一預定之偏壓電流。電感器係連接於 該輸出節點及操作電壓之間。電阻器係並聯於該電感 器。 . . 該輸出節點具有一電容值。該電感器及該電容值決定一 共振頻率（resonant frequency)，且比一預定之操作頻 率（operating frequency)大1· 5倍以上，其中該電容可 為該RF輸出節點之寄生電容或為一般電容。藉由該電感 器可控制該共振頻率。 該電流鏡的一電晶體之源極、該第一接地節點及該電容 器分別經由獨立之接地通路而接地。此外，該第一及第 二電晶體、該電感器以及該電阻器係由一 CMOS製程製作 於一基板上，而該些獨立接地通路的寄.生電感實質上完 全由該些晶片外銲線提供。 本發明之該第一及第二電晶體係製作於一單一深N極井 (deep N-we11)中。 本發明之優點： 1 .有較大的頻寬，有平穩的操作範圍。 2. 三個獨立接地通路能有效改善隔離效果及穩定性，並 降低雜訊。 3. 該等晶片外銲線提供適當的寄生電感，而不再需要外 加電感器。Page 7 1226747 Case No. 92126408 V. Description of the invention (3) Month Modified The gate is used to provide a predetermined bias current. The inductor is connected between the output node and the operating voltage. A resistor is connected in parallel to the inductor. .. The output node has a capacitance value. The inductor and the capacitance value determine a resonant frequency, which is more than 1.5 times greater than a predetermined operating frequency. The capacitance may be a parasitic capacitance of the RF output node or a general capacitance. . The resonance frequency can be controlled by the inductor. The source of a transistor of the current mirror, the first ground node, and the capacitor are respectively grounded through independent ground paths. In addition, the first and second transistors, the inductor, and the resistor are fabricated on a substrate by a CMOS process, and the independent inductances of the independent ground paths are substantially entirely formed by the outer wires of the chips. provide. The first and second transistor systems of the present invention are fabricated in a single deep N-we11 well. Advantages of the present invention: 1. It has a large bandwidth and a stable operating range. 2. Three independent ground paths can effectively improve the isolation effect and stability, and reduce noise. 3. These die bond wires provide proper parasitic inductance without the need for an external inductor.
1226747 ^ — 案蟓92126408 年 五、發明說明（4) ............................. t該第一及第二電晶體係設於同 降低雜訊。 實施方式 月 曰 修正 N極井中，因此能有 紙 H :晶片30的示意圖。晶片3〇包 3金2拉用來設置保護一晶粒（chlp dle) 34。晶粒1 連接點36以及銲線38而電連接 冰34係错^ 4 0。曰物q 人丄 包逆接於日日片3 0的一外部連接 曰片曰3曰〇可—^ 3有一個本發明之低雜訊放大器。因此， 曰曰 可女衣於一印刷電路板（PCB)或類似裴置中。 ΐ ί ” Ϊ :—低雜訊放大器50的電路示意圖，在圖-中係以一虛線區隔晶片内曰 S〜 包含有一第—及二楚^以及曰曰片外。低雜訊放大器5〇 第一電阻哭58晶體52、54及一電感器56和— t 私讲即58。弟一電晶體52之汲極 h 體54之源極。第一雷曰騁於弟一電晶 sk而皆+弟電日日體52之閘極連接於一 RF輪入笳 點，而弟一電晶體52之源極係連接於_曰K f 第二電晶體5 4之間極連接於一第一偏壓曰外接地=。 體54之汲極係經由電感器56以及弟一电晶 作電壓Vdd。低雜訊放大器50之一 RF輪出阻連接於操 晶體5 4之汲極輪出。 出成遽係由第二電 弟一電晶體5 2之閘極係經由一晶片外録 入節點，而第一電晶體52之源極係經由6曰0a連接於RF輸 銲線60a、60b與圖二中之銲線38相類如~鮮線60b接地。 貝似’提供將晶片内 1226747 曰 修正 寒麗、92126408 年 月 五、發明說明（5) —一:一 6〇心60lJ i片外元件的功能。根據本發明，銲線 提供符合兩f適當之規格及材料，以使銲線60a、60b能 外部之電^ ^的寄生電感 '，意即，本發明並不需要晶片 本發明低 容器66以 6 2係被用 以一定的 連接於第 阻器係設 體5 2之閘 地，汲極 晶體的閘 操作電壓 流鏡電路 晶片外鲜 器6 6接地 雜訊放大器50另包含有一電流鏡電路62、一電 及一電容器6 8。如熟於此技術者所知，電流^ 來產生一 DC電流，而該DC電流係為一參考電流 比例放大而成。電流鏡電路6 2經由一偏壓電^ 一電晶體5 2之閘極。在電流鏡電路6 2中，其電 於電流鏡電路6 2内之電晶體閘極以及第一電晶 極之間，而該電流鏡電路6 2電晶·體之源極接 則連接至閘極。電流鏡電路6 2從其所包含之電 極及汲極接收一第二偏壓Vb2。電容器66連接於 Vdd以及晶片外接地70之間。電容器68連接於電 6 2電晶體之源極和第二電晶體5 4之閘極之間。 線6 0 c、6 0 d係分別用來使電流鏡電路6 2和電容1226747 ^ — Case 蟓 92126408 V. Description of Invention (4) ............... the first and second The transistor system is set to reduce noise. The embodiment is modified in the N-pole well, so that a schematic diagram of paper H: wafer 30 can be provided. The chip 30 package 3 gold 2 pull is used to protect a chlp dle 34. The die 1 is connected to the point 36 and the bonding wire 38 while the electrical connection to the ice 34 is wrong. An external connection is connected to the Japanese-Japanese film 30. The Japanese-Japanese film 3 can be an external connection. There is a low-noise amplifier of the present invention. Therefore, women's clothing can be placed on a printed circuit board (PCB) or similar. ΐ ί ”—:-circuit diagram of low-noise amplifier 50. In the figure-a dashed line separates the inside of the chip S ~ and contains a first- and second-chu ^^ and said off-chip. Low-noise amplifier 5〇 The first resistance cry 58 is a crystal 52, 54 and an inductor 56 and -t are privately spoken as 58. The first diode 52 is the source of the drain h of the body 54. The first one is called the first crystal sk. + The gate of the younger electric body 52 is connected to an RF wheel entry point, and the source of the younger electric transistor 52 is connected to _Y K f The second transistor 5 4 is connected to a first bias The external ground =. The drain of the body 54 is applied to the voltage Vdd via the inductor 56 and the first transistor. One of the low-noise amplifier 50's RF wheel output resistance is connected to the drain of the operating crystal 54. Output The gate electrode of the second transistor, the transistor 52, is input to the node via an off-chip, and the source of the first transistor 52 is connected to the RF welding wires 60a, 60b and FIG. 2 via 6a. Phase 38 of the welding wire is similar to ground of fresh wire 60b. Beisi 'provided that the chip is 1226747 modified Han Li, 92126408 5th, invention description (5) — 1: 60 core 60lJ i off-chip According to the present invention, the bonding wire provides appropriate specifications and materials in accordance with the two specifications, so that the bonding wire 60a, 60b can have external parasitic inductance, meaning that the present invention does not require a chip. The container 66 is connected to the gate ground of the second resistor system body 5 2 with a 6 2 series. The gate operation voltage of the drain crystal is a current mirror circuit chip. The 6 6 ground noise amplifier 50 also contains a current. Mirror circuit 62, an electric and a capacitor 68. As known to those skilled in the art, the current ^ generates a DC current, and the DC current is amplified by a reference current ratio. The current mirror circuit 62 is passed through a The bias electrode ^ a gate of a transistor 52. In the current mirror circuit 62, it is electrically connected between the transistor gate of the current mirror circuit 62 and the first transistor, and the current mirror circuit 6 2 The source of the transistor and the body is connected to the gate. The current mirror circuit 62 receives a second bias voltage Vb2 from the electrodes and the drain included in it. The capacitor 66 is connected between Vdd and the chip external ground 70. Capacitor 68 is connected to the source of the transistor 6 and the gate of the second transistor 5 4 Room. Line 6 0 c, 6 0 d line respectively for causing a current mirror circuit 62 and a capacitor
晶片外銲線6 〇 b、6 0 c、6 0 d則提供了三個獨立的接地通 路，改善了絕緣情況和穩定性，及降低了電路雜訊。取 代傳統低雜訊放大器中的電感器，使得晶片面積縮小， 也可降低製造成本。 在操作時，〆RF輸入訊號傳送至銲線60a，在第一電晶體The wafer outer bonding wires 60b, 60c, and 60d provide three independent ground paths, which improves insulation and stability, and reduces circuit noise. Replacing inductors in traditional low-noise amplifiers reduces chip area and reduces manufacturing costs. During operation, the RF input signal is transmitted to the bonding wire 60a.
1226747* -- …- 9212_8 月 曰 修正 五、發明說明（6) 52之閑極j皮接收。接著，該RF輪入訊號會依據第一偏壓 Vb^以及第二偏壓Vb2、操作電壓vdd、電感器56對第一電 ^器^的比值而被加以放大。最後，被放大的訊號會從 第二電晶體54之汲極輸出。一般而言，低雜訊放大器5〇 的運作和習知技術大約相同，也為習於此技術者所熟 =。、该輸出節點具有一電容值，藉由選定該電感器5 6之 電^值與該電容值相配合，以使RF輸出節點的共振頻率 比操作頻率範圍大i · 5倍，其中該電容可為該^?輸出節點 之寄生電容或為一般電容，即直接增加一電容器與該電 容器59並聯。請參考圖四，根據本發明（曲線82)與習知 •低雜訊放大器（曲線8 〇 )相較，在第一電阻器5 8與電感器 56配合下，能降低品質因數UuaHty fact〇r)，也^ 善頻寬。 匕 對直流模式而言，電感器5 6提供了可忽略電阻的路經， 允ό午在電晶體5 4、5 2中有已知流暈的電流。而對交流模 式而言，電阻器58會降低電感器56之並聯等效電阻。、 本發明低雜訊放大器5 0之第一及第二電晶體5 2、5 4形成 於一基板上的共同深Ν極井。圖五為用來製作第一及第二 電晶體5 2、5 4之上視圖，而圖六為圖五所示的剖視圖。 在基板90上，二ρ極井9 2形成於同一 Ν極井94中，而Ν極井 9 4係没在一深ν極井9 6之上。圖五及圖六中所示結構的黎】 作和操作為熟於此技術者所習知，故不在此贅述。1226747 *-…-9212_August Said Amendment V. Description of the invention (6) 52 Reception of leisure time. Then, the RF input signal is amplified according to the first bias voltage Vb ^ and the second bias voltage Vb2, the operating voltage vdd, and the ratio of the inductor 56 to the first resistor ^. Finally, the amplified signal is output from the drain of the second transistor 54. Generally speaking, the operation of the low noise amplifier 50 is about the same as the conventional technology, and it is also familiar to those skilled in this technology. The output node has a capacitance value. By selecting the electrical value of the inductor 56 to match the capacitance value, the resonance frequency of the RF output node is i. 5 times larger than the operating frequency range. The capacitance can be The parasitic capacitance of the output node is a general capacitance, that is, a capacitor is directly added in parallel with the capacitor 59. Please refer to FIG. 4. According to the present invention (curve 82), compared with the conventional low noise amplifier (curve 80), the quality factor UuaHty fact〇r can be reduced with the cooperation of the first resistor 58 and inductor 56. ), Also ^ good bandwidth. For the DC mode, the inductor 56 provides a negligible path, allowing a known halo current in the transistors 5 4 and 5 2. For AC mode, resistor 58 reduces the parallel equivalent resistance of inductor 56. The first and second transistors 5 2 and 5 4 of the low noise amplifier 50 of the present invention are formed on a common deep N-pole well on a substrate. FIG. 5 is a top view of the first and second transistors 5 2 and 5 4, and FIG. 6 is a cross-sectional view shown in FIG. 5. On the substrate 90, two p-pole wells 92 are formed in the same N-pole well 94, and the N-pole well 9 4 is not above a deep v-pole well 96. The operations and operations of the structures shown in FIGS. 5 and 6 are well known to those skilled in the art, so they will not be repeated here.
1226747 案號 92126408 年 月 日 修正 五、發明說明（7) 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明專利之涵 蓋範圍。 1226747 案號 92126408 年月日 修正 圖式簡單說明 圖式之簡單說明 圖一為習知低雜訊放大器之電路示意圖。 圖二為一晶片以及一封裝結構的剖視圖。· 圖三為本發明一低雜訊放.大器之電路不意圖。 圖四為圖三所示之低雜訊放大器的品質因數對頻率的曲 線圖。 ， 圖五為圖三所示之電晶體在CMOS上的佈局示意圖。 圖六為圖五所示電晶體在CMOS上的剖視圖。1226747 Case No. 92126408 Amendment V. Description of the Invention (7) The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application for the present invention shall belong to the invention patent. Coverage. 1226747 Case No. 92126408 Amendment Brief description of the diagram Brief description of the diagram Figure 1 is a circuit diagram of a conventional low noise amplifier. FIG. 2 is a cross-sectional view of a chip and a package structure. · Figure 3 is a circuit diagram of a low noise amplifier. Figure 4 is a plot of the figure of merit versus frequency for the low noise amplifier shown in Figure 3. Figure 5 is a schematic layout of the transistor shown in Figure 3 on CMOS. FIG. 6 is a cross-sectional view of the transistor shown in FIG. 5 on a CMOS.
圖式之符號說明 10^ 50 低雜訊放大器 12、 7 0 接地 11、 52、54 電 晶體 24 電流鏡電路 26^ 28、 56 電 感器 30 CMOS晶片 32 封裝結構 34 晶粒 36 晶粒連接點 38 鲜線 40 外部連接點 58> 64 電阻器 6 0a 、60b、 60c 銲線 62 電流鏡電路 66^ 68 電容器 80、 82 曲線 90 : 基板 92 P極井 94 N極井 9 6 深N極井Symbols in the drawings 10 ^ 50 Low noise amplifier 12, 7 0 Ground 11, 52, 54 Transistor 24 Current mirror circuit 26 ^ 28, 56 Inductor 30 CMOS chip 32 Package structure 34 Die 36 Die connection point 38 Fresh line 40 External connection point 58> 64 Resistor 6 0a, 60b, 60c Welding wire 62 Current mirror circuit 66 ^ 68 Capacitor 80, 82 Curve 90: Substrate 92 P-pole well 94 N-pole well 9 6 Deep N-pole well
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