TWI225716B - Magnetoresistive random access memory structure and method for manufacturing the same - Google Patents

Abstract

A magnetoresistive random access memory (MRAM) cell structure and a method for manufacturing the same are disclosed. In the method, two conductive lines used to write a data into a selected magnetoresistive random access memory cell are deposed on an upper side of a magnetic tunnel junction (MTJ) device of the selected magnetoresistive random access memory cell. In addition, the two conductive lines can be formed by using a deposition method, a photolithography method, and an etching method, and a chemical mechanical polishing (CMP) method is not implemented.

Description

1225716 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to a magnetoresistive random access memory (Magne tor es isti ve Random Acces s Memory; MRAM) cell structure and a method for manufacturing the same, and In particular, it relates to a type of two wires used for writing, a memory cell structure located above a magnetic tunnel junction (MTJ) element of a magnetoresistive random access memory cell, and no chemical mechanical polishing (Chemical Mechanical Polishing; CMP) method for manufacturing a magnetoresistive random access memory cell structure. [Other technologies] Magnetoresistive random access memory is a new type of non-volatile (Non-Volatile) memory. This type of magnetoresistive random access memory uses ‘high-sensitivity magnetoresistive materials. The characteristics of this type of magnetoresistive random access memory are that it has many advantages such as read and write speed, high integration, high durability, low power consumption, and anti-radiation. It also integrates dynamic random access memory. (DRAM), static random access memory (SRAM), and flash memory (F 1 ash Mem ry) are designed specifically for the characteristics of memory elements. In addition, the magnetoresistive random access A memory process can be integrated with the existing complementary metal-oxide-semiconductor (CMOS) process with high process compatibility.

A magnetoresistive random access memory system is a memory element based on a magnetic channel interface element. The magnetic channel interface components are mainly composed of "Free" Ferromagnetic Layer, "Tunnel Juncti0n" layer, and " Pinned " Ferromagnetic Layer (" Pinned " Ferr 〇magnetic Uyer). Under the external magnetic field, the free ferromagnetic layer can rotate freely, while the pinned ferromagnetic layer cannot rotate freely under the external magnetic field. Pinned iron

Page 6 1225716 V. Description of the invention

The magnetic layer is generally composed of a ferromagnetic layer and an anti-ferromagnetic (AFM) layer. The antiferromagnetic layer is used to pin the magnetic properties of the ferromagnetic layer. The channel current from one ferromagnetic layer through the insulation interface layer to the other ferromagnetic layer is based on the magnetic properties of the free ferromagnetic layer. That is, when the magnetism of the free ferromagnetic layer is the same as the magnetic direction of the pinned ferromagnetic layer, the channel current is larger, and when the magnetism of the free ferromagnetic layer is opposite to the magnetic direction of the pinned ferromagnetic layer, the channel current is more small. Therefore, there are two logic states of a magnetoresistive random access memory cell: a high channel junction resistance and a low channel junction resistance. Since binary logic data can be stored without electricity, the magnetoresistive random access memory is a non-volatile memory.

Please refer to FIG. 1. FIG. 1 is a cross-sectional view showing a structure of a conventional magnetoresistive random access memory cell. In this magnetoresistive random access memory cell, a gate electrode 106 is formed on the substrate 100, and a drain electrode 102 and a source are implanted in the substrate 100 on both sides of the gate electrode 106.极 104。 The pole 104. The dielectric layer 108 covers the gate 106 and the substrate 100, the dielectric layer 112 is located on the dielectric layer 108, and the wires 116 and the conductive layer 114 are located in the dielectric layer 112. Among them, a plug 11 () composed of a conductive material penetrates the dielectric layer 108 to electrically connect the source electrode 104 and the conductive layer 114. The dielectric layer 118 is located on the dielectric layer 112 and exposes a part of the conductive layer 114. The dielectric layer ι24 is located on the "electrical layer 118" and the wires 1 2 0 and the magnetic channel interface elements that guide the stray current are located in the dielectric layer 1 2 4 in which the wires 120 are located in a part On the dielectric layer 118 and the conductive layer 114, and the magnetic channel interface element 1 2 2 is located on a part of the wire 丨 2 0. The wire 1 2 6 is located on the dielectric layer 124 and the magnetic channel interface element 122. Each other Interleaved wires 丨 2 6 and wires 1 丨 6 are used to write data into the selection

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V 1225716 V. Description of the Invention (3) The magnetoresistive random access memory cell. The wires 126 and 116 are located above and below the magnetic channel interface element 122 to provide a combination of magnetic fields. The combination of this magnetic field realizes a large and strong magnetic field to overcome the magnetic turning threshold determined by the Astroid Curve. The other magnetoresistive random access memory cells along the wires 1 2 6 and the wire 11 16 are only affected by the magnetic force of a single magnetic field and cannot exceed the magnetic turning threshold. Therefore, the magnetoresistive random access memory cell at the intersection of the lead 1 26 and the lead 116 can complete the writing of data without disturbing other magnetoresistive random access memory cells. In this magnetoresistive random access memory cell, when reading data in the magnetoresistive random access memory cell, it needs to be electrically connected with a transistor or diode to prevent discrete Reading of current interference data. Therefore, it is necessary to additionally provide a bypass connection electrically connected to the magnetic channel interface element 12 and the transistor (that is, composed of the gate electrode 106, the drain electrode 102 and the source electrode 104) or the diode. 1 2 0 to block discrete currents. Since the wires 1 2 6 and the wires 116 are located on the upper and lower sides of the magnetic channel interface element 1 2 2 respectively, the production of the wires 11 16 first etches the trenches 1 28 in the dielectric layer 1 12 and then deposits conductive materials such as metal (Not shown), and then use a chemical mechanical polishing process to remove a portion of the conductive material to form a conductive wire 116 having a flat surface. However, it is difficult for the CMP process to accurately control the remaining thickness of the entire wafer, so that the thickness distribution of the wires 116 is uneven. Therefore, the writing current density and magnetic flux efficiency will vary with the thickness of the lead 116. That is to say, it is necessary to retain a relatively wide process range, and inevitably requires a large write current. In addition, the bypass wire 120 will increase the area of each unit cell, which will cause the density of the memory cell to decrease.

Page 8 1225716 V. Description of the invention (4) --- [Summary of the invention] The purpose of the present invention is to provide a magnetoresistive random access memory cell structure, where the two wires used to write congratulations are located here The same side of the magnetic channel interface element of the magnetoresistive random access memory and memory cell structure. Therefore, when reading the data in this magnetoresistive random access memory cell, discrete current can be prevented. Another object of the present invention is to provide a magnetoresistive random access memory cell structure without the need to additionally provide a bypass wire next to a magnetic channel interface element in the magnetoresistive random access memory cell structure. , When reading the data in the magnetoresistive random access memory cell, the discrete current is passed along the magnetic channel interface element and the plug and conductive layer below it into the transistor or diode, and Prevent the effects of discrete currents. Therefore, the area of the magnetoresistive random access cell structure can be effectively reduced, thereby increasing the setting density of the magnetoresistive random access memory cell and increasing the degree of chip accumulation. Another object of the present invention is to provide a method for manufacturing a magnetoresistive random access memory cell structure, which is to arrange two wires for writing data in the magnetism of the magnetoresistive random access memory cell structure. The identity of the channel interface elements. In this way, the two wires' can be fabricated using deposition, lithography, and etching techniques without using a chemical mechanical polishing step. Therefore, it is possible to eliminate the problem that the CMP process is difficult to control the overall thickness, and the influence of process variations can be reduced, thereby effectively improving the implementability of the process. It is still another object of the present invention to provide a manufacturing method of a magnetoresistive random access memory crystal j, which uses deposition, lithography, and etching techniques to produce two wires for writing data. Therefore, the thickness of the wire has a very good control ability, and a thinner wire can be obtained, which greatly improves

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High wire flux efficiency. According to the above-mentioned objective cell structure of the present invention, at least: one of the active elements may be the above-mentioned active element and the above-mentioned active element; a first one, and the material of the first conductive wire may be On the above-mentioned first wire, a second wire is located above the first wire and the second wire to separate the first wire from the second wire, and the wire is connected to the wire described above. A magnetoresistive element is located on a random semiconductor. Diodes, etc .; This magnetic channel is located on the above-mentioned magnetic flux and other conductive materials. The insulating layer may be an insulating layer, where this—the magnetic flux surface element magnetic channel is connected to the fabric; a general access memory crystal substrate The road junction element is electrically connected to the upper junction element, wherein the insulation layer is located on a dielectric material; the insulation layer is electrically according to a preferred embodiment of the present invention, and the magnetic channel junction element includes at least: an antiferromagnetic layer, A pinned layer is next to the antiferromagnetic layer described above, where the antiferromagnetic layer fixes the magnetization direction of the pinned layer; a free layer; and a channel resistance 2. barrier layer

Layer) is located between the pinned layer and the free layer. The material of the channel barrier layer may be an oxide inscription (A 12 03). In addition, the pinned layer and the free layer may be a single layer structure or a multi-layer structure. According to another object of the present invention, a magnetoresistive random access memory cell is proposed. The manufacturing method of the structure includes at least the following steps. First, a semi-octane conductor substrate is provided. At least one active element has been formed on the semiconductor substrate. The active element may be, for example, a transistor or a diode. A magnetic channel interface element is further formed on the above active element, wherein the magnetic channel interface element

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1225716 V. Description of the invention (6) It is electrically connected with the above active element. Next, a first wire is formed on the magnetic channel interface element, and the first wire is electrically connected to the magnetic channel interface element. An insulating layer is further formed on the first wire. Then, a second wire is formed on the insulating layer, wherein the insulating layer electrically isolates the first wire from the second wire. According to a preferred embodiment of the present invention, when forming the first conductive line and the second conductive line, they are fabricated by means of deposition, lithography, and etching, instead of using chemical mechanical polishing.

Since the 'first wire and the second wire are located on the upper side of the magnetic channel interface element, and are manufactured by means of deposition, lithography, and etching, no chemical mechanical polishing step is required. Therefore, there is no need to set additional bypass wires, which can increase the degree of accumulation. In addition, it can also get rid of the difficulty of controlling the thickness of the chemical mechanical polishing process, which is not only conducive to the operation of the process, but also can obtain the thinner first and second wires, and improve the magnetic flux efficiency of the first and second wires. [Embodiment]

The invention discloses a magnetoresistive random access memory cell structure and a manufacturing method thereof. The first wire and the second wire used for writing data are located on the upper side of the magnetic channel interface member, and the process control force is used. More excellent deposition, :: two and etching steps to make. Therefore, it is possible to greatly increase the magnetoresistive memory cell density, reduce the difficulty of the process, and effectively reduce the high magnetic flux efficiency. In order to make the narrative diagram / 70 of the present invention, refer to the following description and cooperate with the diagrams of Figs. 2 to 5.

Page 11 1225716

In the current magnetoresistive random access memory, the wires are respectively located under the magnetic channel abutment interface elements. In the manufacturing process, it is a very stringent picking flow, which can generate more magnetic The current density will increase, and the thickness of the wire will be flattened when the magnetic flux is located under the magnetic channel interface element during the grinding step to flatten the wire. Since it is difficult to effectively control, it is necessary to increase the process range, so that the wire will have a lower power drop, which will increase the power consumption. The disadvantage of the magnetoresistive random access memory cell junction technology. In the memory cell, two are used to write data on the top and bottom sides of the device. It is located on the magnetic flux, and it is used for chemical mechanical grinding. It is known that when the wire carries a higher electric flux, and when the wire is thinner, the internal efficiency of the wire is also improved. However, in terms of wires, it is always difficult to control the thickness of the wires on the entire wafer by using chemical machinery to guide the entire wafer to compensate for the lack of process. As a result, the flow density results in a lower magnetic flux efficiency. Therefore, the present invention provides a structure and a manufacturing method thereof to improve the conventional knowledge.

Please refer to FIGS. 2 to 5, and FIGS. 2 to 5 are cross-sectional views showing a manufacturing process of a magnetoresistive random access memory cell according to a preferred embodiment of the present invention. First, a semiconductor substrate 200 is provided, and at least an active element has been formed on the substrate 200, such as a transistor composed of a source 202, a drain 204, and a gate 21o. General diode. Among them, the gate electrode 2 is composed of the gate dielectric layer 206 and the conductive layer 208, and the source electrode 202 and the drain electrode 204 are located in the substrate 20 on both sides of the closed electrode 21, as described in Figure 2 shows. This active element + can be used as a switch when reading data from a magnetoresistive random access memory cell. Next, a dielectric layer is formed by, for example, chemical vapor deposition (CVD).

Page 12 1225716 V. Description of the invention (8)-21 2 Covers the source 2 0 2 of the substrate 2 0, the pole 2 0 4 and the gate 2 1 0. Then use, for example, lithography and etching techniques to define the opening of the plug 2 丨 4 in the dielectric layer 2 1 2 and expose a portion of the source electrode 2 0 2, and use a method such as deposition or recording to the plug 2 1 The opening of 4 is filled with a conductive material, and a " plug 2 1 4 is formed in the dielectric layer 2 丨 2. Subsequently, a dielectric layer 216 is formed over the dielectric layer 212 and the plug 214 by, for example, chemical vapor deposition. The openings of the conductive layer 218 are defined in the dielectric layer 216 by using, for example, lithography and residual technology, and the plug 2 1 4 and a portion of the dielectric layer 2 1 2 are exposed. After the opening of the conductive layer 2 1 8 is formed, the opening of the conductive layer 2 1 8 is filled with a conductive material by using, for example, deposition or electroplating to form a conductive layer 218 in the dielectric layer 216, as shown in FIG. The conductive layer 218 is electrically connected to the source electrode 202 through the plug 214. In the above description, although the plug 214 and the conductive layer 218 are separately manufactured, the dual metal damascene process can also be used to simultaneously manufacture the plug 214 and the conductive layer 218, but the present invention is not limited thereto. Next, a method such as chemical vapor deposition is used again to form a dielectric layer 22 covering the dielectric layer 216 and the conductive layer 218. The lithography and engraving processes are used to define the interposer in the dielectric layer 220. The opening of the plug 222 is exposed, and the conductive layer 218 of the plug 222 is exposed. After the opening of the plug 222 is formed, the opening of the plug 222 is filled with a conductive material by, for example, deposition or plating, and the conductive layer 218 is A plug 222 is formed in the dielectric layer 220. After the plug 222 is formed, an antiferromagnetic layer 224, a pinning layer 226, and a channel resistance are sequentially stacked on the dielectric layer 220 and the plug 222 by, for example, a deposition method. The barrier layer 228 and the free layer 23 are formed in a stacked structure. The material of the channel barrier layer 228 may be, for example, alumina, and the pinned layer 226 and the free layer 230 are so-called “pinned”, ferromagnetic layers, respectively. Take 1225716 V. Description of the invention (9) Second freedom: iron: layer. In addition, the 'pinned layer 22 6 and the free layer 23 0 may be a single layer: heap 2 ::: structure. The structure is then defined using, for example, photolithography and etching processes, and the antiferromagnetic layer 224, the channel barrier layer 228, and the free layer 23 are removed, and part 9 is exposed and the plug 2 is exposed. 22 and the other united introduction 介 99〇1 ^: ^ 丄 电 件 232. A magnetic channel junction element is formed on the zinc magnetic m electrical layer 2 20 = 232 'After the magnetic channel junction element 232 is formed, a dielectric sound 234 frost is formed using a method such as chemical vapor phase / child product. The electrical layer is overlaid on the dielectric layer 22 of the exposed road. After that, a wire 23δ cover is formed in the dielectric layer 234 and the magnetic flux collision interface by using a cover such as deposition, lithography, and etching to form a wire 23δ cover. As shown. It uses a wire that writes data to a magnetoresistive random access memory cell and the material of the wire 236 can be a general metal or a straight-line [two-use deposition, lithography and sweet engraving method to make the wire 236 Has better control ability, and can obtain thickness = lead: using the chemical vapor deposition method of Example 1 above to form the insulating layer 2㈣: on: the line 236, the material of the insulating layer 238 can be ordinary materials. Re-use, for example, deposition, lithography, and etching, on the magnetically-concentrated puller—form the wires from Λ-8 to form the 240-bit position due to the “use” on the part of the insulating layer 238 above. 32. Similarly, by = 系 ㈣> The thickness of the wire 240 is better by the methods of product, lithography, and ㈣. There is a better _ She 丨 + amp; + Uncle for the wire 240, so the guideline = this force, and the thickness of the wire 240 is the same. It can be a gold-like material, etc. In addition, the lead 236 and the lead 24 are staggered, meaning that the direction of the lead 240 is perpendicular to the paper surface, and

Page 14 1225716 V. Description of the invention (ίο) " -----: Parallel to paper. After the wire 240 is formed, a dielectric layer 242 is formed on the insulating layer 238 and the wire 24o by, for example, chemical vapor deposition, and the fabrication of the magnetoresistive random access memory cell is completed, as shown in FIG. According to the above-mentioned preferred embodiments of the present invention, one of the advantages of the present invention is that the two wires used to write data are located above the magnetic channel interface element, and can be used after the magnetic channel interface element is formed. Deposition, lithography, and etching processes can be used to make these two wires without using a chemical mechanical polishing process. Therefore, ′ has a very good control ability for the thickness of the wire, and a thinner wire can be obtained, thereby greatly improving the magnetic flux efficiency of the wire and achieving the purpose of improving the performance of the magnetoresistive random access memory. As can be seen from the above-mentioned preferred embodiments of the present invention, another advantage of the present invention is that it is possible to read the magnetoresistive random access memory cell without additional bypass wires beside the magnetic channel interface element. During the data transmission, the discrete current is allowed to enter the active component as a switch along the magnetic channel interface element and the plug and conductive layer below it, which can effectively prevent the discrete current from interfering with the reading of the data. Therefore, the area of the structure of the magnetoresistive random access memory cell can be reduced, and the setting density of the magnetoresistive random access memory cell can be effectively improved, thereby achieving the purpose of increasing the degree of chip accumulation. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of an invention shall be determined by the scope of the attached patent application.

Page 15 1225716 Brief Description of Drawings Figure 1 is a sectional view showing the structure of a conventional magnetoresistive random access memory cell. Figures 2 to 5 are cross-sectional views showing a process of a magnetoresistive random access memory cell according to a preferred embodiment of the present invention. [A brief description of the element representative symbols] 100: substrate 1 0 2: drain 1 0 4: source I 0 6 · 'gate 108: dielectric layer 110: plug II 2: dielectric layer I 14: conductive layer II 6: Conductor 11 8: Dielectric layer 1 2 0: Conductor 122: Magnetic channel interface element 1 2 4: Dielectric layer 1 2 6: Conductor 128: Channel 20 0: Substrate 2 0 2: Source 2 0 4: Drain 2 0 6: Gate dielectric

1225716 on page 16 Brief description of the diagram 208 conductive layer 210 gate 212 dielectric layer 214 plug 216 dielectric layer 218 conductive layer 220 dielectric layer 222 plug 224 antiferromagnetic layer 226 pinning layer 228 channel barrier layer 230 Free layer 232 magnetic channel interface element 234 dielectric layer 236 wire 238 insulating layer 240 wire 242 dielectric layer < 1

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Claims (1)

1225716 6. Scope of patent application A · —A kind of magnetoresistive random access memory (MRAM) cell structure, including at least: an active element on a substrate; * a magnetic channel junction (MTJ) element on the active element And the magnetic channel is connected to the surface element electrically connected to the active element; a first wire is located on the magnetic channel interface element, and the first wire is electrically connected to the magnetic channel interface element; and the second wire is located on The first wire is electrically insulated from the first wire. 2 · The magnetoresistive random access memory cell structure according to item 1 of the scope of the patent application, wherein the magnetic channel interface element includes at least: 4-an antiferromagnetic (AFM) layer; a pinned layer ) Next to the antiferromagnetic layer, wherein the antiferromagnetic layer fixes the magnetization direction of the pinned layer; a free layer; and a tunnel barrier layer is located between the pinned layer and the free layer Between layers. 3. The magnetoresistive random access memory cell structure according to item 2 of the scope of the patent application, wherein the pinned layer is a single layer structure. 4. The magnetoresistive random access memory cell structure according to item 2 of the scope of the patent application, wherein the pinned layer is a multi-layer (Mu 1 t 1 ay e r) structure. Page 18 ^ 257i6 Force's patent application scope 5. The resistive random access memory cell structure described in item 2 of the patent application scope, wherein the free layer is a single-layer structure. 6. The squat resistance random access memory cell structure according to item 2 of the scope of patent application, wherein the free layer is a multi-layer structure. 7 · The impedimental random access memory cell structure as described in item 2 of the scope of the patent application, wherein the material of the channel barrier layer is vaporized aluminum (ai2o3). • The magnetoresistive random access memory cell as described in item 1 of the scope of the patent application, which further includes at least an insulating layer between the first wire and the second wire to be electrically isolated The first wire and the second wire. & The magnetoresistive random access memory cell as described in item 1 of the scope of the patent application, wherein the active element is a transistor. 1 〇 As in the structure, the magnetoresistive random access memory cell described in item 1 of Shen Qing's patent scope, wherein the active element is a diode. 1. A magnetoresistive random access memory cell structure including at least:-an active element is located on a substrate; a channel interface element is located on the active element, and the channel interface element is electrically connected to the active element; A wire is located on the magnetic channel interface element, and the first wire is electrically Page 19 1225716 Sixth, the scope of the patent application is connected to the magnetic channel interface element; an insulating layer is located on the first wire; a second wire is located on the insulating layer; a wire and the second wire. And wherein the insulating layer electrically isolates the first-12 · cell structure according to item 1 of the scope of the patent application, wherein the active element is a magnetic random access memory crystal as described above. 1Q,, ^ ^ Even magnetic P and random access memory crystal 1 3 · The magnetic cell structure as described in item 11 of the patent scope of Shenyan, wherein the active element is a diode. 1 4 · The magnetoresistive random access memory cell structure according to item 11 of the scope of the patent application, wherein the magnetic channel interface element includes at least an antiferromagnetic layer; a pinned layer adjacent to the antiferromagnetic layer Layer, wherein the antiferromagnetic layer fixes the magnetization direction of the pinned layer; a free layer; and a channel barrier layer is located between the pinned layer and the free layer. 15 11 A & Department of Patent Application, the magnetoresistive random access memory cell structure described in item 14 of the present invention, wherein the pinned layer is a single layer structure. 16 · The cell structure of claim 14 in the scope of patent application, wherein the pinned layer is a multi-layer structure of the magnetoresistive random access memory crystal described in the item. [225716, patent application scope 17] The magnetoresistive random access memory cell structure described in item 14 of the patent application scope, wherein the free layer is a single-layer structure. 18 · The magnetoresistive random access memory cell structure according to item 14 of the scope of patent application, wherein the free layer is a multi-layer structure. 19. The magnetoresistive random access memory cell structure according to item 14 of the scope of the patent application, wherein the material of the channel barrier layer is vaporized aluminum. 20. The magnetoresistive random access memory cell structure according to item 11 of the scope of the patent application, wherein the first wire and the second wire are staggered. 21 · — A type of magnetoresistive random access memory cell structure, including at least: — an active element; a magnetic channel interface element, wherein the active element is located on one side of the magnetic channel interface element, and the magnetic channel interface An element is electrically connected to the active element; a first wire is located on the other side of the magnetic channel interface element, the first wire is electrically connected to the magnetic channel interface element, and a second wire is located on the magnetic channel interface The other side of the device, and the second wire is electrically insulated from the first wire. 22. The magnetoresistive random access memory cell structure according to item 21 of the application, wherein the magnetic channel interface element includes at least: 1225716 6. The scope of the patent application is an antiferromagnetic layer; a pinned layer is adjacent to the antiferromagnetic layer, wherein the antiferromagnetic layer fixes the magnetization direction of the pinned layer; a free layer; and a channel barrier layer is located in the Between the pinned layer and the free layer 2 3. The magnetoresistive random access memory cell structure described in item 22 of the patent application scope, wherein the pinned layer is a single-layer costructure. 24. The magnetoresistive random access memory cell structure according to item 22 of the scope of the patent application, wherein the pinned layer is a multi-layered structure. 25. The magnetoresistive random access memory cell structure according to item 22 of the scope of the patent application, wherein the free layer is a single-layer structure. 26. The magnetoresistive random access memory cell structure according to item 22 of the scope of the patent application, wherein the free layer is a multi-layer structure. 2 7 · The magnetic random access method described in item 22 of the scope of patent application " Hidden cell structure, where the material of the channel barrier layer is alumina 〇〇,, ^ ^ > & Magnetoresistive random access memory crystal 28. Tenderness as described in item 21 of the scope of patent application 3 & cell structure, which further includes at least an insulating layer located on the second: wire "^ Second Between the wires, the third wire and the first wire are electrically isolated. Page 22 1225716 6. Scope of patent application 29. The magnetoresistive random access memory cell structure as described in the scope of patent application No. 21), wherein the active element is a transistor. 30. The magnetoresistive random access memory cell structure according to item 21 of the scope of the patent application, wherein the active element is a diode. 31. Provided is a manufacturing method for forming an electrical forming connection to form a first type of magnetoresistive random access memory cell structure, at least one substrate, wherein at least one magnetic channel interface element has been formed on the substrate. The active element is connected to; a first wire is connected to the magnetic channel interface element on the magnetic channel interface element; an insulation layer is on the first conductor; and a second wire is on the insulation layer, wherein the wire and the第二 线。 The second wire. μ an active element; 'and electrically isolated from the active element' and the first wire is electrically isolated. For example, the active element is X τ $ in the scope of the patent application. The manufacturing method of the structure, wherein the * meer,..., Resistance random access memory crystal 33. As in the scope of application for the scope of the patent application No. 31, +, dagger structure manufacturing method, described in the resistance type Bajia 4 Active element, 'random access memory crystals are polar bodies 1225716 * _______________ _______ VI. Scope of patent application '4 · The manufacturing method of obstructive random access memory cell structure as described in item 31 of Shenyan Patent Fan Yuan, where the magnetic channel is connected == includes: A ferromagnetic layer; a pinned layer next to the antiferromagnetic layer, wherein the antiferromagnetic layer fixes the magnetization direction of the pinned layer; a free layer; and a channel barrier layer between the pinned layer and the free layer between. 35. The method for manufacturing a resistive random access memory cell structure as described in item 34 of the scope of patent application, wherein the pinned layer is a single layer structure. b. The manufacturing method of the haptic random access memory cell structure as described in item 34 of the patent application scope, wherein the pinned layer is a multi-layer structure. 37. The method for manufacturing a magnetoresistive random access memory cell structure according to item 34 of the scope of the patent application, wherein the free layer is a single-layer structure. 38. The method for manufacturing a magnetoresistive random access memory cell structure according to item 34 of the scope of the patent application, wherein the free layer is a multi-layer structure. 39. The method for manufacturing an obstructive random access memory cell structure as described in item 34 of the scope of patent application, wherein the material of the channel barrier layer is alumina. 40. A magnetic random access memory crystal as described in item 3 of the scope of patent application 1225716 VI. Manufacturing method of patented cell structure, wherein the first wire and the second wire are staggered a. 41. Manufacturing method of magnetoresistive random access memory cell structure as described in item 31 of the patented scope The step of forming the first conductive line further includes at least a deposition step, a lithography step, and an etching step. 42. The method for manufacturing a magnetoresistive random access memory cell structure according to item 31 of the scope of the patent application, wherein the step of forming the second wire further includes at least a deposition step, a lithography step, and an etching step. . Page 25