1225710 五、發明說明（1) 【發明所屬之技術領域】 本發明是有關於半導體製程技術，且特別是有關於一 種阻質降低（resistance-reduced)半導體元件之製造方 法0 【先前技術】 隨著半導體元件積集度的提升，相對如閘極長度 (gate iengthe)、閘介電層厚度（thickness Qf gate dielectric)、接合深度（J_uncti〇n depth)等元件參數之 要求也隨之減少。因此採用多晶矽閘極（p〇ly —gat/)之半 導體製造方法已無法因應因元件特徵尺寸縮減所需要之低 電阻值，故因應上述趨勢而研發出採用替代多晶矽之新閘 :及新穎之閘極結構’如當今主要之採用轉化金屬 夕：：(tr;nsiti:n metal silicide)材質的 化金 屬 Cpol ysi 11 cide)閘極。 然而，於多晶矽化金屬閘極之組成中通常 矽材料而增加了其達成低電 μ·成有 加了鬥=ί應，夕曰曰 金屬閘極中之多晶矽成分將掸 加了閘極介電層之有效厚声， — 风刀特曰 硼滲透或摻質擴散等類似門顳 S摻雜多晶矽之 力。 6政等類似問碭亦限制了其達成低電阻值能 近年來，業界之研發主| 以達到低電阻值之閘極元件的目二：蕻=々材料之使用 材料可形成更低電阻值之金屬朽二^ -新穎之閘極 I鱼屬閘極材料，此些材料例如為 0548^00461^, ⑽），92196 ; Shawn.ptd $ 6頁 1225710 五、發明說明（2) 鎢（W )、鈦（丁 i ) 石夕基材中間能隙 阻值之金屬閘極 等問題。於美國 極結構及製造方 與閘極絕緣層間 因此，若能 種降低其電阻值 成本、製程步驟 多晶梦化金屬閘 之需求。 、氫化鎢（WN)、氮化鈦（ΠΝ)等具有相對於 之功函數值的金屬材料，以形成具有低電 ，其並具有防止前述之硼穿透或閘極空 專利第6 340 629號t揭露了 一種鎢金屬閉 法，所使用之閘電極層材質為鎢金屬，其 則存在有一附著層以增加其附著能力。/、 針對當今主流之多晶矽化金屬閘極提出一 之方法則可降低閘極材料更換所對於製程 等方面的衝擊，並可延長於半導體業界中 極製程之製程壽命，進而滿足元件縮小化 内容】 鐘於此，本發明的主要^ ^ ^ ^ ^ ^ ^ ^ ^ ^ -種半導體製程。）就疋犍供可降低兀件電 5上Si的皮本發明提供了-種閘極元件之製造方 屬石夕化物層中，以；；；=;質於閘極元件所露 2小化趨勢所需之低電阻值V、阻值並進而滿足因 包i發明之—種阻值降低半導體元件之製造方 序形成一介電層、一導雷 體基底具有-第—導層體基底上，其 化物層；施行-摻雜:導電層表面露出有- 牙序’摻雜具有第二導電性之 第7頁 0548-A50046TWF(Nl) ； 92196 ； Shawn.ptd 1225710 五、發明說明（3) 摻質於金屬矽化物層内以降低導電層之阻值，其中第二導 :l± f於第：導電性；形成一上蓋層於導電層上；依序定 、、上盍層、導電層及介電層以形成一圖案化之閘極結構； 乂及幵^成對源/汲極區於閘極結構兩側之半導體基底内 _ 乂幵y成阻值降低閘極元件，其中該些源/没極區具有 同於該第二導電性之一第三導電性。 、此外本發明之一種阻值降低半導體元件之製造方法 ，適=於動態隨機存取記憶體製程，其步驟包括·· 其& 一電容器之一半導體基底，其中半導體 二弟一導電性；以及形成一阻值降低閘極元件於 接於兮二部份表面上，其中阻值降低閘極元件電性連 值降低閘極元件传：由ic記憶體元件，而此阻 方法所形成。值降低半導體元件之製造 了τίί’本發明之阻值降低半導體元件之製造方法，除 憶體製程。 衣備/、有千面電容器之動態隨機存取記 由於本發明之阻值降低 降低具有金屬-牛¥體兀件之製造方法可適度 件縮小化所需之較低電阻 L值’如此可滿足兀 化物等導電材料為;屬材;中之多晶石夕及金屬石夕 生產成本開銷以及製程轉換上的風2低製程轉換之機台或 第8頁 0548-A50046TWF(Nl) ； 92196 i Shawn.ptd 五、發明說明（4) 【實施方式】 第一實施例： 1 s岡U月-之阻值降低半導體元件之製造方法將配合第 -ΛΛ Λ之第一實施例作—詳細錢。首先如第1圖所 Γ日μ皇二2體基底100上，例*為一半導體石夕基底上， 程依序形成一介電層1〇2和一導電層1〇8。 上 100具有Ν型或Ρ型摻雜之第-導電性，而介電 曰，、\吊疋以乾式或濕式熱氧化法在7 0 0〜1 0 0 0。(：下緩慢 =成之氧化矽層，其厚度約在^〜丨〇〇埃間或為少於3〇埃之 厚度。$此’介電層1〇2之材質亦可替代為如氧化鋁、氧 化铪、氧化鍅、氮氧化铪、氧化鑭等具有介電常數高於5 之高介電常數材料（hlgh dielectric c〇nstant material)或此些材料之組合。 在此’導電層108例如為第1圖中所示之一複合導電 層’其係由依序堆疊於介電層1〇2上之一多晶矽層1〇4以及 =金屬矽化物層106所組成。其中，多晶矽層1〇4之材質為 經#雜（doped)之多晶矽，而金屬矽化物層1〇6則例如為矽 化鎢、石夕化铭等由耐火金屬與多晶矽所組成之材質。在 此’以製作N型金氧半導體（nm〇s)元件為例，導電層1〇8之 形成可藉由電漿化學氣相沈積（PECVD)法並臨場^^丨tu) 地掺雜磷化氫（phosphine)或砷化三氫（arsine)等具有異 於第一導電性之第二導電性之摻質的氣體以形成厚約1225710 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to semiconductor process technology, and in particular, to a method for manufacturing a resistance-reduced semiconductor element. 0 [Previous technology] With The improvement of the semiconductor device accumulation degree has relatively reduced the requirements for device parameters such as gate length (thickness), gate thickness (thickness Qf gate dielectric), and junction depth (junction depth). Therefore, the semiconductor manufacturing method using polycrystalline silicon gates (p0ly-gat /) has been unable to cope with the low resistance value required due to the reduction of the feature size of the components. Therefore, in response to the above trends, new gates that replace polycrystalline silicon have been developed: and novel gates The pole structure is the same as today's main use of transformed metal :: (tr; nsiti: n metal silicide) of the metallized metal Cpol ysi 11 cide) gate. However, in the composition of polysilicon metal gates, silicon materials are usually added to achieve low power μ · 成 有 加 斗 = 应 Ying, said that the polycrystalline silicon component in metal gates will add gate dielectric Layers of effective thick sound, — Air knife special boron infiltration or dopant diffusion and other similar to portal-temporal S-doped polycrystalline silicon. Similar issues such as the 6 government have also limited its ability to achieve low resistance. In recent years, the industry's research and development master | to achieve a low resistance value of the gate element two: 蕻 = 々 material use of materials can form a lower resistance value Metal Decay ^-Novel Gate I Fish is a gate material, such materials are, for example, 0548 ^ 00461 ^, ⑽), 92196; Shawn.ptd $ 6 pages 1225710 V. Description of the invention (2) Tungsten (W), Titanium (butadiene) metal gates in the middle band gap resistance value of Shi Xi substrate. In the United States, the structure of the electrode and the gate and the insulating layer of the gate. Therefore, if it can reduce its resistance value, the cost and process steps of polycrystalline dream metal gates. Metal materials with relative work function values such as tungsten hydride (WN), titanium nitride (ΠN), etc., to form low-electricity, and have the prevention of the aforementioned boron penetration or gate air patent No. 6 340 629 t discloses a tungsten metal closing method. The material of the gate electrode layer used is tungsten metal, and there is an adhesion layer to increase its adhesion ability. / 、 Proposing a method for the current mainstream polysilicon metal gates can reduce the impact of gate material replacement on the process and other aspects, and can prolong the process life of the extreme processes in the semiconductor industry, thereby satisfying the content reduction of components. At this point, the main ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ of the present invention is a semiconductor process. The present invention provides a kind of gate element manufacturing method in the lithium oxide layer, in order to reduce the Si on the element 5, and the quality of the gate element is reduced. The required low resistance value V, the resistance value, and further satisfying the invention of the manufacturing method of a semiconductor device with a reduced resistance value to form a dielectric layer, a conductive body substrate, and- , Its compound layer; implementation-doping: the surface of the conductive layer is exposed-dental sequence 'doped with second conductivity page 0548-A50046TWF (Nl); 92196; Shawn.ptd 1225710 V. Description of the invention (3) Doped in the metal silicide layer to reduce the resistance value of the conductive layer, where the second conductivity: l ± f at the first: conductivity; forming an overlying layer on the conductive layer; sequentially ordering, upper layer, and conductive layer And a dielectric layer to form a patterned gate structure; 乂 and 幵 ^ paired source / drain regions in the semiconductor substrate on both sides of the gate structure 乂 幵 成 y into a resistance value to reduce the gate element, which The source / dead region has a third conductivity that is the same as one of the second conductivity. In addition, a method for manufacturing a semiconductor device with a reduced resistance value according to the present invention is suitable for a dynamic random access memory system. Its steps include: its & a semiconductor substrate of a capacitor, wherein the second semiconductor has a conductivity; and Forming a resistance-reducing gate element on the surface of the two parts, wherein the resistance-reducing gate element is electrically connected to reducing the gate element transmission: it is formed by an ic memory element, and this resistance method is formed. The manufacturing method of a semiconductor device having a reduced value τίί ′ The manufacturing method of a semiconductor device with a reduced resistance of the present invention, except for the process. Clothing / Dynamic random access memory with thousand-face capacitors. Due to the reduction of the resistance value of the present invention, the manufacturing method with metal-metal parts can reduce the lower resistance L value required for moderate part reduction. Carbide and other conductive materials are: metal materials; the production cost of polycrystalline stone and metal stone and the conversion process of the machine on the low 2 process or page 0548-A50046TWF (Nl); 92196 i Shawn .ptd V. Description of the Invention (4) [Embodiment] The first embodiment: The method for manufacturing a semiconductor device with a reduced resistance value of 1 sgang U-month will be used in conjunction with the first embodiment of the -ΛΛ Λ-detailed money. Firstly, as shown in FIG. 1, on a substrate of 100 μ-μμ2, for example, on a semiconductor stone substrate, a dielectric layer 102 and a conductive layer 108 are sequentially formed. The upper 100 has N-type or P-type doped first conductivity, while the dielectric is, the dry or wet thermal oxidation method in the 70 ~ 100 0 0. (: Slow down = Cheng's silicon oxide layer, its thickness is about ^ ~ 丨 00 Angstroms or less than 30 Angstroms. The material of this 'dielectric layer 102' can also be replaced by such as alumina , Holmium oxide, hafnium oxide, hafnium oxynitride, lanthanum oxide, and other materials with a dielectric constant higher than 5 (hlgh dielectric material) or a combination of these materials. Here, the 'conductive layer 108 is, for example, A composite conductive layer shown in FIG. 1 is composed of a polycrystalline silicon layer 104 and a metal silicide layer 106 sequentially stacked on the dielectric layer 102. Among them, the polycrystalline silicon layer 104 The material is doped polycrystalline silicon, and the metal silicide layer 106 is made of refractory metal and polycrystalline silicon, such as tungsten silicide, Shi Xihuaming, etc. Here, the N-type metal-oxide semiconductor is fabricated. (Nm〇s) element as an example, the formation of the conductive layer 108 can be doped with phosphine or arsenide by plasma chemical vapor deposition (PECVD) method in situ ^^ (Arsine) and other dopant gases having a second conductivity different from the first conductivity to form a thick
0548-A50046TWFCN1) ； 92196 ； Shawn.ptd 第9頁 1225710 五、發明說明（5) f形成金屬矽化物層1〇6，其厚度則約為5〇〇〜1〇〇〇埃，多 曰曰石夕層1 0 4與金屬石夕化物層1 〇 β之比例約介於2 : 1〜2 8 · J。 接著，為本發明之特徵步驟，藉由施行摻雜程序 以摻雜具有第三導電性之摻質（未顯示）於金屬矽化物層 =6内。在此，此摻質之第三導電性異於半導體基底之 弟一導電性。摻雜程序丨1〇可為離子植入（i〇n implantati〇n)程序或電漿浸入型離子植入 immersion ion implantati〇n，ριπ)程序或其他適當之 =程序。當使用離子植入程序時，其所使用之植入能量 〇M〇^：8. 0M 〇15 ^ ^ ^ ^(at〇ms/cm2) 〇 1 t ；： 型金虱半導體（NM0S)元件為例，摻雜程序11〇中可使用 2 ％以製作p型金氧半導體（刪s)元件為 払雜程序11 0中則可使用硼、銦等P型摻質。 金屬二掺:更程 = ^ r匕物層m之電阻值:、並進=導 睛參照第2圖，接著形成—卜芸奸〆 層1〇8，並藉由後鋒、上」：材枓(未顯示)於導電 施扞cm 貝S子兀線圖案以及微影蝕刻程序之 施订（未顯不）以於導電層108上形 圖案之上蓋層112a，並以上芸展119矛夕後之子兀線 -非專向性兹刻(未顯示)依序定義下 == 層以形成閘極結構i 0。在此，圖荦 1 : 乂及，丨電 181系化之閘極結構1 0係由依 第10頁 0548-A50046IWF(Nl) ; 92196 ； Shawn.ptd 1225710 五、發明說明（6) 序堆疊於半導體基底1〇〇上一閑極介電 &、一 ，以及一上蓋層―所組成，其中閉電極層二極為 如第2圖中所示包含依序堆疊於閘極介電層““上多晶矽 層1 〇4a及金屬矽化物層丨06a之一複合閘電極結構。 請參照第3圖，在此之後，可依照傳統製程技術，先 以離子植入與快速熱回火程序製作淡摻雜源極/汲極區 (LDD) 1 1 4，然後以化學氣相沈積與回蝕刻程序形成絕緣側 壁116，最後再以離子植入形成深源極/汲極區ιΐ8以及利 用f速熱回火形成源極/汲極區丨20，而完成具有阻值降低 之多晶石夕化金屬（polysi licide)閘極電晶體1〇，的製作， 其結構如第3圖所示，其中閘電極層丨08a之整體電阻值已 經由本發明之摻雜程序而適度降低。 接著請參照表一，藉由量測於不同試樣中大體相同位 置處具有相同尺寸（線寬與長度）之閘極元件片電阻值 (sheet resistance，Rs)以說明利用本發明方法斜於车墓 ，件電阻值降低之功效，其中各試樣中之第方== 寬約為0 · 1 9 8微米（// m)之n型多晶矽化鎢金屬 joly-tungsten si licide)閘極電晶體而第二閘極則為線 寬約為0· 154微米（//Hi)之n型矽化鎢金屬（poly — tungsten s i 1 i c i d e )閘極電晶體。 、 在此，表一中之試樣1〜3中之第一、第二閘極元件皆 為採用本發明之阻值降低半導體元件之製造方法所形成， 於閘電極層表面處之矽化鎢材質則已藉由本實施例中所描 述之掺雜程序11 〇條件摻雜磷摻質於其内以降低其整體電 第11頁 0548-A50046TWF(Nl) ； 92196 ； Shawn.ptd 12257100548-A50046TWFCN1); 92196; Shawn.ptd Page 9 1225710 V. Description of the invention (5) f forms a metal silicide layer 106, the thickness of which is about 500 ~ 100 Angstroms, and more The ratio of the evening layer 104 to the metallic stone oxide layer 1 〇β is approximately 2: 1 to 2 8 · J. Next, as a characteristic step of the present invention, a dopant process is performed to dopant (not shown) having a third conductivity in the metal silicide layer = 6. Here, the third conductivity of the dopant is different from that of the semiconductor substrate. The doping procedure 10 may be an ion implantation procedure or a plasma immersion ion implantation procedure or other appropriate procedures. When the ion implantation procedure is used, the implantation energy used by it is 〇M〇 ^: 8.0M 〇15 ^ ^ ^ ^ (at〇ms / cm2) 〇1 t: The type of gold lice semiconductor (NM0S) element is For example, in the doping procedure 110, 2% can be used to make a p-type metal-oxide-semiconductor (deletion) element. For the doping procedure 110, a p-type dopant such as boron or indium can be used. Metal dopant: more range = ^ r resistance value of the layer m:, advancing = guide eye Refer to the second figure, and then form-Bu Yun rape layer 108, and through the back, up ": wood (Not shown) The conductive pattern and the lithography etching process are ordered (not shown) to cover the layer 112a on the conductive pattern 108, and to display the above 119 sons. The lines-non-specificity (not shown) are sequentially defined as follows == layers to form the gate structure i 0. Here, Figure 荦 1: and, the gate structure of the electric 181 series 10 is based on page 10 0548-A50046IWF (Nl); 92196; Shawn.ptd 1225710 V. Description of the invention (6) Sequence stacked on the semiconductor The substrate 100 is composed of an anode dielectric & one, and an upper capping layer. The closed electrode layer as shown in FIG. 2 includes two layers sequentially stacked on the gate dielectric layer. Layer 104a and metal silicide layer 06a composite gate electrode structure. Please refer to Figure 3. After that, according to the traditional process technology, a lightly doped source / drain region (LDD) 1 1 4 can be fabricated by ion implantation and rapid thermal tempering, and then chemical vapor deposition is performed. The insulating sidewall 116 is formed with the etch-back process, and finally a deep source / drain region is formed by ion implantation, and a source / drain region is formed by f-speed thermal tempering. 20, and a polycrystalline silicon having a reduced resistance is completed. The structure of the polysi licide gate transistor 10 ′ is made as shown in FIG. 3, wherein the overall resistance value of the gate electrode layer 08a has been moderately reduced by the doping process of the present invention. Next, please refer to Table 1. By measuring the sheet resistance (Rs) of the gate element having the same size (line width and length) at substantially the same position in different samples to illustrate the use of the method of the present invention, the vehicle is inclined to the vehicle. Tomb, the effect of reducing the resistance value, in which the square of each sample == n-type polycrystalline tungsten silicide metal joly-tungsten si licide) gate width of about 0 · 198 microns (// m) The second gate is an n-type tungsten silicide (poly-tungsten si 1 pesticide) gate transistor with a line width of about 0.154 micrometers (// Hi). Here, the first and second gate elements in samples 1 to 3 in Table 1 are all formed by using the manufacturing method of the semiconductor element with reduced resistance value of the present invention, and the tungsten silicide material on the surface of the gate electrode layer Phosphorus has been doped in the doping procedure described in this example to reduce its overall electricity. Page 11 0548-A50046TWF (Nl); 92196; Shawn.ptd 1225710
五、發明說明（7) 阻值，而於表一中之試樣4〜6中之第—、第二鬧極一 為習知半導體技術中之閘極製造方法所形成，無"-件旮 本發明所揭露之電阻值降低製程。如表」所示額外採用 樣卜3及試樣4〜6之平均（averaged)片電阻值:有:f出試 異，採用本發明之降低電阻之摻雜程序之閘極元件的差 出較採用習知方法形成閘極元件較低之電阻值，其L表現 甚至可降低至14 ohms/sq，片電阻值之降低功效可$ 5值 片電阻值之百分之18，所形成之多晶矽化鎢閘極電晶體先 阻值表現已接近金屬閘極電晶體之片電阻值表現。99 -之 如此，依據本發明之阻值降低半導體元件之製造方法 可製備出具有低電阻值之多晶矽化金屬閘極元件，以滿足 ¥今線兔細小元件之需求’並可延長當今多晶石夕化金屬問 極製程之應用年限（process lifetime)，而無需替換間^ 元件中之多晶矽及金屬矽化物等導電材料為金屬二料:故 可減低製程轉換之機台或生產成本開鎖以及製程轉換上的 風險。 袤- 1 1¾- 2 試樣 3 平均片 電阻値 試樣 4 試樣 5 試樣 6 平均片 電阻値 降低坊 效ffi一 第蘭極 片電阻値 (ohms/sq) 14 14.2 13.9 14 17 17.1 17.3 17.1 18 第一蘭極 片電阻値 (ohms/sq) 15.5 16 15.1 15.5 19.9 18.9 19 19 — 18V. Description of the invention (7) Resistance value, and the first and second of the samples 4 to 6 in Table 1 are formed by the gate manufacturing method in the conventional semiconductor technology, without " -pieces电阻 The process of reducing the resistance value disclosed in the present invention. As shown in the table ", the average sheet resistance values of sample 3 and samples 4 to 6 are additionally used: yes: f is different, and the difference of the gate element using the doping procedure for reducing resistance of the present invention is more suitable. The conventional method forms the lower resistance value of the gate element, and its L performance can even be reduced to 14 ohms / sq. The reduction effect of the chip resistance value can be $ 5 value, 18% of the chip resistance value. The polycrystalline tungsten silicide formed The gate resistor's first resistance performance is close to that of the metal gate transistor. 99-In this way, according to the method for manufacturing a semiconductor element with reduced resistance value according to the present invention, a polycrystalline silicon silicided gate element with a low resistance value can be prepared to meet the needs of today's small rabbit components, and it can extend the current polycrystalline stone. The application lifetime of the metallization process is not required to replace the conductive material such as polycrystalline silicon and metal silicide in the element ^, so it can reduce the process conversion of the machine or the production cost. Unlocking and process conversion Risk.袤-1 1¾- 2 Sample 3 Average sheet resistance 値 Sample 4 Sample 5 Sample 6 Average sheet resistance 値 Reduces the square effect of the first electrode resistance (ohms / sq) 14 14.2 13.9 14 17 17.1 17.3 17.1 18 First blue plate resistance ohm (ohms / sq) 15.5 16 15.1 15.5 19.9 18.9 19 19 — 18
1225710 I五'發明說明（8) ~ 第二實施例： 除了上述第一貫施例之應用外，本發明之降低阻值半 導體元件之製造方法亦可整合於動態隨機存取記憶體 (DRAM)製程·.中’其製造方法則圖示於第4圖至第5圖中。 請茶照第4圖’首先提供一半導體基底2 〇 〇，例如為一經p 型摻雜（P-doped)之矽基底，於半導體基底2〇〇内則已藉由 傳統溝槽型動態隨機存取記憶體製程形成有一溝槽型 (^trench type)電容器20 2。在此，溝槽型電容器2〇2係以 簡圖緣示而不在此細述其元件，其主要由位於底部之電容 204、位於電容2 0 6上方之絕緣壁20 6及導線2〇8以及表面之 隔離物2 10所構成。此時半導體基底2〇〇之表面為大體平整 表面。 請繼續參照第5圖，接著於半導體基底表面上形成具 有阻值降低之閘極電晶體2丨2，其大體電性連結於由導線 20 8所擴散而成之一擴散區（標示為2〇8)。在此，閘極電晶 體2 1 2係藉由第一實施例中第j圖〜第3圖所圖示之步驟所形 成，而閘極電晶體21 2在此則例如為為一多晶矽化金屬閘 極’其主要包括形成於半導體基底2〇〇上之閘介電層214、 作為閘電極之用且包含多晶矽層216及金屬矽化層218之導 電層2 2 0、上盍層2 2 2以及絕緣側壁2 2 4，以及形成於半導 體基底2 0 0内之兩源/汲極區_226以分別作為源極與汲極， 此些源/汲極區2 2 6其中之一電性連結於由導線2 〇 8所擴散 而成之一擴散區（標不為2〇8)，而當中金屬矽化物層218之 電阻值已為如先前之摻雜程序11 〇所降低，故導電層22 0之 第13頁 0548-A50046TWF(Nl) ; 92196 ； Shawn.ptd 1225710 五、發明說明（9) 整體電阻值可更為降低 如此，請參照第5圖，於半導體基底2 〇 〇上形成有一阻 值降低之閘極電晶體2丨2以及一溝槽型電容器2 〇 2，兩者間 ϊ ί ^ 電性連接而組成—動態隨機存取記憶體⑽am) ϊΐ2Π ΐ藉由降低閘極電晶體212之電阻值，記億 /單表=較低之開啟電壓（如。n v〇nage)進而 體212上u連結不同記億單元23〇 下降（voltage drop)問題。 凡線（未圖不）之電壓 於上述應用中，電容器之種類並非以 底内之溝槽型電容器2〇2加以限定，本/成於+今體基 :體=之製造方法亦可與製備電容心半之導阻體值= 一動恕P現機存取記憶體製程加以整合j _ 土氐上之 (crown-shape)外型之一平面電容器，制、為具有冠狀 性表現之記憶單元。 衣造具有較佳電 雖然本發明已以較佳實施例揭露如 限定本發明，任何熟習此技藝者，在施W其亚非用以 和範圍内’當可作各種之更動與潤饰，發明之精神 範圍當視後附之申請專利範圍所界定 ^本發明之保護1225710 5th invention description (8) ~ Second embodiment: In addition to the application of the first embodiment described above, the manufacturing method of the semiconductor device with reduced resistance of the present invention can also be integrated into dynamic random access memory (DRAM) The manufacturing process is shown in Figure 4 to Figure 5. Please refer to FIG. 4 'Firstly, a semiconductor substrate 200 is provided, for example, a silicon substrate that is p-doped (P-doped). In the semiconductor substrate 200, a conventional trench-type dynamic random storage is used. A memory-type trench capacitor (202) is formed. Here, the trench capacitor 20 is shown in a simplified diagram and its components are not described in detail here. It is mainly composed of a capacitor 204 at the bottom, an insulating wall 20 6 and a lead 20 8 above the capacitor 2 06, and The surface is composed of spacers 2-10. At this time, the surface of the semiconductor substrate 2000 is a substantially flat surface. Please continue to refer to FIG. 5, and then form a gate transistor 2 丨 2 with a reduced resistance on the surface of the semiconductor substrate, which is generally electrically connected to a diffusion region (labeled 2〇) diffused by the wire 20 8. 8). Here, the gate transistor 2 1 2 is formed by the steps illustrated in FIG. J to FIG. 3 in the first embodiment, and the gate transistor 21 2 is, for example, a polycrystalline silicon silicide metal. The gate electrode mainly includes a gate dielectric layer 214 formed on a semiconductor substrate 2000, a conductive layer 2 2 0 serving as a gate electrode and including a polycrystalline silicon layer 216 and a metal silicide layer 218, and an upper layer 2 2 2 and The insulating sidewall 2 2 4 and two source / drain regions _226 formed in the semiconductor substrate 2000 are used as a source and a drain, respectively. One of these source / drain regions 2 2 6 is electrically connected to A diffusion region (not marked as 208) diffused by the conductive wire 2 08, and the resistance value of the metal silicide layer 218 has been reduced as in the previous doping procedure 11 0, so the conductive layer 22 0 Page 13 of 0548-A50046TWF (Nl); 92196; Shawn.ptd 1225710 V. Description of the invention (9) The overall resistance value can be further reduced. Please refer to FIG. 5 to form a resistance value on the semiconductor substrate 2000 The lowered gate transistor 2 丨 2 and a trench capacitor 2 〇2 are formed by electrical connection between them. Dynamic random access memory ⑽am) ϊΐ2Π ΐBy reducing the resistance value of the gate transistor 212, record 100 million / single table = lower turn-on voltage (eg. Nv〇nage) and then connect u to different 212 million units on the body 212 23〇 Voltage drop problem. Where the voltage of the line (not shown) is used in the above application, the type of capacitor is not limited by the trench capacitor 002 in the bottom. The manufacturing method of this / produced + this body: body = can also be prepared with The capacitance value of the half of the capacitance core = one is a plane capacitor with a crown-shape appearance, which is integrated into the current memory access process. It is a memory unit with a coronal performance. Clothing has better electricity. Although the present invention has been disclosed in preferred embodiments, such as limiting the present invention, anyone skilled in this art can use it within its scope and scope. The spiritual scope should be defined by the scope of the attached patent application ^ The protection of the present invention
1225710 圖式簡單說明 第1〜3圖為一系列剖面圖，用以說明本發明之阻值降 低閘極元件之製造方法； 第4〜5圖為一系列剖面圖，用以說明本發明之阻值降 低半導體元件之製造方法於動態隨機存取記憶體製程中之 應用。 符號說明】 100、20 0〜半導體基底； 1 0 2〜介電層； 104、104a、2 16〜多晶矽層； 106、106a、218〜金屬石夕化物層 I 0 8〜導電層； II 0〜掺雜程序； 112a〜上蓋層； I 0 2 a、2 1 4〜閘極介電層； 108a、220〜閘電極層； II 4〜淺源極/汲極區 11 6、2 2 4〜絕緣側壁 1 1 8〜深源極/汲極區 120、22 6〜源極/汲極區 1 0〜閘極結構； 1 0 ’、2 1 2〜閘極電晶體： 2 0 2〜溝槽型電容器； 20 4〜電容；1225710 Brief description of the drawings. Figures 1 to 3 are a series of cross-sectional views, which are used to explain the manufacturing method of the resistance reduction gate element of the present invention. Figures 4 to 5 are a series of cross-sectional views, which are used to illustrate the resistance of the present invention. Application of a method for manufacturing a semiconductor device with reduced value in a dynamic random access memory system. Explanation of symbols] 100, 20 0 to semiconductor substrate; 102 to dielectric layer; 104, 104a, 2 16 to polycrystalline silicon layer; 106, 106a, 218 to metal oxide layer I 0 8 to conductive layer; II 0 to Doping procedure; 112a ~ cap layer; I 0 2 a, 2 1 4 ~ gate dielectric layer; 108a, 220 ~ gate electrode layer; II 4 ~ shallow source / drain region 11 6, 2 2 4 ~ insulation Side wall 1 1 8 ~ deep source / drain region 120, 22 6 ~ source / drain region 1 0 ~ gate structure; 1 0 ', 2 1 2 ~ gate transistor: 2 0 2 ~ trench type Capacitor; 20 4 ~ Capacitance;
0548-A50046TWF(Nl) ； 92196 ； Shawn.ptd 第15頁 1225710 圖式簡單說明 2 0 6〜絕緣壁； 2 0 8〜導線； 2 1 0〜隔離物； 2 3 0〜動態隨機存取記憶體單元0548-A50046TWF (Nl); 92196; Shawn.ptd Page 15 1225710 Schematic description of 2 0 6 ~ insulation wall; 2 0 8 ~ wire; 2 1 0 ~ spacer; 2 3 0 ~ dynamic random access memory unit
0548-A50046TWF(Nl) ； 92196 ； Shawn.ptd 第16頁0548-A50046TWF (Nl); 92196; Shawn.ptd page 16