TWI225683B - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure and a method for manufacturing the same are disclosed. In the method, after conductive regions are formed, surfaces of insulated regions between the conductive regions are passivated by using such as a selective reaction method, a plasma surface treatment method, or an ion implantation method, etc., so as to prevent atoms of the conductive regions from diffusing into the insulated regions via the surfaces of the insulated regions.

Description

1225683 Case No. 92106108 Rev. V. Description of the invention [Invention of the invention is related to a sub-expanding [first half and the copper that can conduct the life of the current component of the copper is a reduced version of gold, but it causes a layer of electricity In order to block the current of the atomic components from the current conductor, the current is called 0. Due to the low conductor in the conductive layer of most cities, the purpose is to increase the copper. The copper will still be electrically conductive due to the barrier of the conductor. (1) The technical field] Related to a semiconducting interconnect structure and adjacent insulation area] In the manufacturing process, due to the conductive density, not only the electrical stability of the sub-components is stabilized. In the integrated circuit, a lower wire system is selected and matched with Improved electrical resistance and better components can withstand the number of more wiring layers. Stability of electronic components 〇 Copper is the material of the barrier before the lead between the lead and the lead of the component: the atoms diffuse to the vicinity along the surface of the dielectric layer. Stability. The body structure and its manufacturing method, and especially its manufacturing method, can prevent the original line ruler signal in the conductor area from measuring the resistance of the product. (In the case of RC-induced migration circuits, the degree and reduction will increase the time, and then reduce the special arrangement of the ability to require extremely high materials, such as materials for De1 ay). The demand for copper from electronic elements is a metal phenomenon. It can greatly reduce the operating resistance of the production parts, and it is even better than the parts. As the interlayer is reduced to ground due to this calculation speed, copper easily diffuses into the dielectric layer and is externally conductive. Therefore, copper is embedded in the dielectric layer, such as tantalum (Ta) or tantalum nitride (TaN), on the sidewall and bottom of the opening of the dielectric layer. However, the copper of the copper wire diffuses and enters the dielectric layer, and the influence element exhibits a method to prevent the copper atoms of the copper wire from moving along the surface of the dielectric layer.

1225683 _Case No. 92106108_Year 1 Amendment _ V. Description of the invention (2) Surface diffusion is an additional layer of cover on the surface of the copper wire. Please refer to Fig. 1 to Fig. 2. Figs. 1 to 2 are cross-sectional views showing a manufacturing process of a conventional copper wire covering layer. First, a dielectric layer 102 is formed on the base material 100 on which a part of the interconnection layer of the electronic component has been formed, and then a photolithography and etching process is used on the dielectric layer 102. In a plurality of openings 104. Next, a barrier layer 106 is conformally covered on the opening 10 and the dielectric layer 102, and a metal material film (only the metal layer 1 0 8 is shown) is formed to cover the barrier layer 1 0 6 on. Then, the metal material film outside the opening 104 and the barrier layer 106 are removed by grinding, and a metal layer 108 is formed in the opening 104. A part of the barrier layer 106 and the metal layer 108 in the opening 104 is removed by means of excessive grinding or chemical etching, etc., so that the dielectric layer 1 0 2 surrounding the opening 104 is slightly higher than the opening. The metal layer 108 and the barrier layer 106 in 104 are formed as shown in FIG. 1. Next, a covering material film is formed on the dielectric layer 10, the barrier layer 106, and the metal layer 108 by a deposition method (only the covering layer 1 1 0 is shown therein), and the covering material is formed. The film fills the opening 104. Among them, the covering material film can block the diffusion of the material of the metal layer 108. Then, the covering material film outside the opening 104 is removed by grinding, and a covering layer 1 1 0 is formed on the barrier layer 10 and the metal layer 108 in the opening 104, as shown in FIG. 2 Show. At this time, the metal layer 108 is completely surrounded by the barrier layer 106 and the cover layer 110, so the material of the metal layer 108 can be prevented from diffusing into the surrounding dielectric layer 102. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor structure that forms a passivation layer on the surface of a dielectric layer between interconnect wires such as copper wires, thereby preventing copper in the copper wires. Atomic via

Case No. 1225683 Case No. 92106108 Amendment V. Description of the Invention (3) The surface of the adjacent dielectric layer diffused to cause unexpected conduction. Another object of the present invention is to prevent the edge layer of the conductive material in the conductive region from forming on the surface of the insulating layer between the conductive layer (Selective Reaction, treatment) or ion implantation line, The adjacent conductor is reduced, thereby improving the device. According to the above-mentioned object of the present invention, the structure includes at least one substrate; a substrate on the substrate; and a plurality of surfaces. According to a preferred embodiment of the present invention, the insulating region can be made of oxidized stone or the like, which is a selective reaction layer and plasma. According to another object of the present invention, the method first provides A substrate is then formed to form a plurality of conductor regions and a purified layer is formed in another conductor region. The conductor material is expanded in accordance with a preferred embodiment of the present invention.

In the dielectric layer, two adjacent copper wires are avoided to provide a method for manufacturing a semiconductor structure. After the area, a thin purification layer is formed by conducting a method such as selective reaction plasma surface treatment (Plasma Surface (Ion Implanation)). In the future, there may be a leakage current (the electrical stability of Leakage) that diffuses along the surface of adjacent insulating layers to between the isolated regions. A semiconductor structure is proposed in which a plurality of semiconductor regions of the semiconductor and a plurality of insulating region passivation layers are respectively located above The passivation layer on the surface area of the insulation area can prevent the conductor area in the conductor area. The above-mentioned conductor area can be made of copper wires or a dielectric material. The passivation layer can be a physical layer or an ion implantation layer. A semiconductor is proposed. The manufacturer of the structure forms an insulating layer on this substrate. It is connected to a part of the insulating layer. Then, the surface of the insulating layer is divided to prevent it from scattering into the insulating layer. The purification layer can use selective reactions, Electricity and other means to make, for example, nitrogen atoms and the insulating layer

Page 10 1225683 V. Description of the invention (4) Material on the surface Passivation of the conductive material located in the area Leakage current of the connection Increase the electricity of the component [Embodiment] The present invention discloses one

Mlt 92106108 is formed by a correction reaction. The surface of the insulation layer between the conductor regions can effectively prevent the diffusion along the surface of the insulation layer into the insulation layer and lower it. Therefore, the purpose of reliability can be increased without increasing the overall process burden. The conductor has a low inner diameter to achieve the purpose of expanding the insulation. Describe and know the material of the barrier layer in the electrical layer. Abrasive barrier layer with metal. Therefore, the efficiency reduction is shown in accordance with the figure. The edge layer is scattered so as to make the copper conductive surface of the semi-dielectric with the first part covered, and the technology is shifted, so as to achieve a partial complex. The present invention firstly interconnects the present invention. First, a semiconductor structure and its surface purification steps, That is, the edge layer can be used to achieve a more detailed description of the present invention. The diagrams in Figs. 3 to 4b (the surface of the layer is diffused to a part of the dielectric layer line when the conductor structure is interconnected, so that the steel conductor is formed in copper On the copper wire and dielectric layer on the wire, in addition to the excess barrier material, to prevent the copper material of the copper wire from being removed, the process is difficult, the process reliability, and the yield method are effective to prevent the components from being exhausted and completed. The surface of the wire needs to be grooved, filled and diffused in the copper material. Therefore, it is more reliable, and the electrical properties in the conductor area are relatively easy to prepare. You can refer to preventing the copper wire from being removed first. Week. Deposit another groove. Then the purpose on the surface of the wire. Therefore, the entire process causes the process cost here to provide a simple and easy to implement method of leakage current. Please refer to Figures 3 to 4b, A preferred embodiment 1 provides a semiconductor interconnect 200 with a substrate 200, wherein the substrate 200 has been formed on the following material with a solid degree of resistance in the enclosing interlayer, which is beneficial to the formation of copper. Cheng profile such as 1225683 _92106108 V. Description of the invention (5)

Correct the various material structure layers required for the component. The insulating layer 20 is formed by a CD method. === The material such as the chemical vapor deposition layer 20 2 can be oxidized on the material 200, for example, by using a lithography process and etching f 4, and Into a dielectric material. After forming the opening 204 having a wire pattern and forming the opening 206 in the insulating layer 202 of the knife, using, for example, physical gas II = to be opened 204 and a thin barrier material film (only network =, (PVD) method to form a 1 Π 舜 签 λ Yu secret 其中 Among them, the barrier layer 208 and the barrier layer 210) cover the insulating layer 202 and the opening 20 to change the opening, and the early barrier material film It may be composed of a gasification group or a group, for example. In the example, a technique such as electro-deposition or electroless deposition is used to form a conductor material, and the conductor material is donated * In the above-mentioned barrier material film :: In a preferred embodiment, the conductor material film is made of copper metal Structure 6: After this issue, the barrier material film and the conductor material film outside the opening are removed using a chemical mechanical polishing (CMp) technique, for example, and the barrier layer 208 and the conductor region 212 are formed. The shape of the opening m] = 2 in 4 of 4 and 2 1 4 in the conductor region, as shown in FIG. 3. ¥ Layer conductor area 2 丨 2 is formed with conductor area 214, and then blunted directly using techniques such as selective surgery, plasma surface treatment, or ion implantation, so that the openings are outside the openings 204 and 206. The passivation layer 2U on the surface of the insulating layer 2 0 2 is shown in FIG. 4a. Alternatively, as shown in the figure, a mask layer 218 is formed on the opening 204 and the opening 206 to cover the barrier body region 21 2 and the barrier layer 210 and the conductor region 214, and then the insulation layer ^ Surface passivation. In order to ensure the reliability of the process, the cover layer 2 1 8 table will be slightly larger than the opening 204 and the opening 206, and will cover the opening perimeter ——_—_ Kai D 2〇6 1225683 _ Case No. 106108_ V. Description of the invention (6) ~ " " " ~~ The surrounding insulating layer 2 0 2. Therefore, after the passivation treatment, a purified layer 2 2 0 is formed on a part of the surface of the insulating layer 2 2. In the present invention, after passivation treatment, a passivation layer 2 1 6 that completely covers the surface of the insulating layer 2 as shown in FIG. 4 a may be formed, or only a part of the insulation may be formed as shown in FIG. 4 b The passivation layer 2 2 0 on the surface of the layer 2 0 2. The blunt film formed on the surface of the insulating layer 2 only needs to make the conductive materials in the conductor regions 21 2 and 21 4 difficult to pass.

The diffusion from the surface of the insulating layer 202 into the insulating layer 202 may be sufficient, and the present invention is not limited to this. W It is worth noting that the passivation structure on the surface of the insulating layer 202 can not only be composed of a single passivation layer, but also can be formed by stacking several passivation layers. The passivation structure of the present invention is not limited to the above-mentioned preferred embodiments. Single passivation layer 0 When selective passivation technology is used to passivate the surface of the insulating layer 20 2, the nitrogen-containing chemical can be made of, for example, a nitrogen-containing chemical that is highly active and only interacts with the insulating layer 202 material. It reacts with the material on the surface of the insulating layer 2 0 2 to form a passivation layer 21 6 or a passivation layer 22 0. In addition, when plasma surface treatment is used to passivate the surface of the insulating layer 202, a nitrogen-containing gas can be used as the plasma source gas, and nitrogen atoms can be placed on the surface of the insulating layer 202 and the surface of the insulating layer 002. The material reacts to form a passivation layer 2 1 6 or a passivation layer 2 2 0. Furthermore, when the surface of the insulating layer 202 is purified by ion implantation technology, nitrogen atoms are implanted on the surface of the insulating layer 202 and a passivation layer 2 16 or a purification layer is formed on the surface of the insulating layer 202. 2 2 0. For example, if the material of the insulating layer 202 is silicon oxide, the passivation layer 2 16 or the passivation layer 2 2 0 generated by the above purification process step may be composed of oxynitride (si ON). Among them, the formation reaction of silicon oxynitride is self-limiting

Page 13 1225683 _1 Case No. 92106108 _ year and month amendment_ V. Description of the invention (7) (S e 1 f-1 imiting) reaction, so after the passivation reaction, the passivation layer composed of silicon oxynitride 2 1 6 Or the thickness of the passivation layer 2 2 0 can be quite thin, which can greatly reduce the impact on the dielectric constant of the insulating layer 2 2. As can be seen from the above-mentioned preferred embodiments of the present invention, one of the advantages of the present invention is that a passivation layer is formed on the surface of the dielectric layer between the wires of the interconnect layer, which can effectively prevent the conductive material in the wire from passing through the surface of the adjacent dielectric layer. Diffusion into the dielectric layer. In this way, accidental conduction between two adjacent wires can be avoided, and the purpose of improving the electrical reliability of the component can be achieved. It can be known from the foregoing preferred embodiments of the present invention that the present invention has the advantages of simple and easy implementation, improved process reliability and yield, and reduced process cost. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

Page 14 1225683 _: _ Case No. 92106108_ Year Month Amendment _ Brief Description of Drawings Figures 1 to 2 are cross-sectional views showing the manufacturing process of a conventional copper wire covering layer. Figures 3 to 4b are cross-sectional views of a semiconductor interconnecting process according to a preferred embodiment of the present invention. [Simple description of element representative symbols] 1 0 0: substrate 1 0 2: dielectric layer 104: opening 1 0 6: barrier layer 108: metal layer 110: cover layer 2 0 0: substrate 2 0 2: insulating layer 204: Opening 2 0 6 · Opening 2 0 8: Barrier layer 2 1 0: Barrier layer 212: Conductor area 214: Conductor area 2 1 6: Passive layer 2 1 8: Mask layer 2 2 0: Passive layer

Page 15

Claims (1)

1225683 Case number 92106108_ 年月 日 _j ^] L ___ VI. Patent application scope 1 A semiconductor structure includes at least: a substrate, a plurality of conductor regions and a plurality of insulating regions are located on the substrate; and a purification layer (Passivation Layer) is located on the surfaces of the insulation regions to prevent one of the conductor materials from diffusing into the insulation regions. 2. The semiconductor structure according to item 1 of the scope of patent application, wherein the conductor material is a metal. 3. The semiconductor structure according to item 1 of the scope of patent application, wherein the conductor material is copper. 4. The semiconductor structure according to item 1 of the scope of patent application, wherein the insulating and marginal regions are made of a dielectric material. 5. The semiconductor structure according to item 1 of the scope of patent application, wherein the passivation layer is a selective reaction layer. 6. The semiconductor structure described in item 1 of the patent application scope, wherein the passivation layer is a plasma treatment layer. 7. The semiconductor structure described in item 1 of the scope of patent application, wherein the passivation Page 16 1225683 _Case No. 92106108_Year Month Date__ VI. Scope of patent application The layer is an ion implantation layer. 8. A method of manufacturing a semiconductor structure, at least comprising: providing a substrate; forming an insulating layer on the substrate; forming a plurality of conductor regions in a portion of the insulating layer; and forming a purification layer on another portion A surface of the insulating layer to prevent one of the conductor regions from diffusing into the insulating layer. 9. The method for manufacturing a semiconductor structure as described in item 8 of the scope of patent application, wherein the material of the insulating layer is a dielectric material. 10. The method for manufacturing a semiconductor structure according to item 8 of the scope of the patent application, wherein the conductor regions are made of metal. 1 1. The method of manufacturing a semiconductor structure according to item 8 of the scope of patent application, wherein the conductor regions are made of copper. 1 2. The method of manufacturing a semiconductor structure as described in item 8 of the scope of the patent application, wherein the step of forming the passivation layer uses a selective reaction method. 1 3 · The method for manufacturing a semiconductor structure as described in item 12 of the scope of patent application, wherein the step of forming the passivation layer further includes at least using an active nitrogen-containing chemical, and the active nitrogen-containing chemical is only related to the insulating layer The material reaction. Page 17 1225683 _Case No. 92106108_Year_Month__ VI. Application for Patent Scope 1 4. The method for manufacturing a semiconductor structure as described in Item 8 of the Patent Application Scope, wherein the step of forming the passivation layer uses a plasma Surface treatment method. 15 · The method for manufacturing a semiconductor structure as described in item 14 of the scope of patent application, wherein the step of forming the passivation layer further includes at least using a nitrogen-containing gas as the plasma source gas. 1 6. The method for manufacturing a semiconductor structure according to item 8 of the scope of the patent application, wherein the step of forming the passivation layer uses an ion implantation method. 17 · The method for manufacturing a semiconductor structure as described in item 16 of the scope of patent application, wherein the step of forming the passivation layer further includes at least using a nitrogen-containing gas as an ion implantation gas. 18. A method of manufacturing a semiconductor structure, at least comprising: providing a substrate; forming an insulating layer on the substrate; forming a plurality of conductor regions in a portion of the insulating layer; and forming a passivation layer in another portion A portion of the surface of the insulating layer to prevent one of the conductor regions from diffusing into the insulating layer. 19. The method for manufacturing a semiconductor structure according to item 18 of the scope of patent application, wherein the conductor regions are made of copper. Page 18 1225683._Case No. 92106108_Year Month Amendment_ VI. Patent Application Scope 20 • The method of manufacturing a semiconductor structure as described in Item 19 of the Patent Application Scope, wherein the step of forming the passivation layer uses a Selective reaction method. 2 1 · The method of manufacturing a semiconductor structure as described in item 20 of the scope of patent application, wherein the step of forming the passivation layer further includes at least using an active nitrogen-containing chemical, and the active nitrogen-containing chemical is only related to the insulating layer The material reaction. 2 2 _ The method for manufacturing a semiconductor structure as described in item 19 of the scope of patent application, wherein the step of forming the passivation layer uses a plasma surface treatment method. 2 3 · The method for manufacturing a semiconductor structure as described in item 22 of the scope of the patent application, wherein the step of forming the passivation layer further includes at least using a nitrogen-containing gas as the plasma source gas. 24. The method for manufacturing a semiconductor structure according to claim 19, wherein the step of forming the passivation layer uses an ion implantation method. 25. The semiconductor as described in claim 24 A method of manufacturing a structure, wherein the step of forming the passivation layer further includes at least using a nitrogen-containing gas as an ion implantation gas. 2 6. A method of manufacturing a semiconductor structure, including at least: providing a substrate; Page 19 1225683 _Case No. 92106108_Year_Month__ VI. The scope of the patent application forms an insulating layer on the substrate; forming a plurality of conductor regions in a part of the insulating layer; and forming a plurality of purification layers on another A part of the surface of the insulating layer to prevent one of the conductor regions from diffusing the conductive material into the insulating layer. 27. The method of manufacturing a semiconductor structure as described in item 26 of the patent application scope, wherein These conductor regions are made of copper. 28. The method of manufacturing a semiconductor structure as described in item 26 of the scope of patent application, wherein the step of forming the passivation layers uses a selective reaction method. 2 9 · The method for manufacturing a semiconductor structure according to item 28 of the scope of patent application, wherein the step of forming the passivation layers further includes at least using an active nitrogen-containing chemical, and the active nitrogen-containing chemical is only insulated from the insulation The material of the layer reacts. 30. The method for manufacturing a semiconductor structure according to item 26 of the scope of the patent application, wherein the step of forming the passivation layers uses a plasma surface treatment method. 31. The method for manufacturing a semiconductor structure as described in item 30 of the scope of patent application, wherein the step of forming the passivation layers further includes at least using a nitrogen-containing gas as the plasma source gas. Page 20 1225683 _Case No. 92106108_Year_Month_ifi_ VI. Patent Application Range 3 2. The method of manufacturing a semiconductor structure as described in Item 26 of the Patent Application Range, wherein the steps of forming the passivation layers are performed using a Ion implantation. 33. The method for manufacturing a semiconductor structure according to item 32 of the scope of the patent application, wherein the step of forming the passivation layers further includes at least using a nitrogen-containing gas as an ion implantation gas. Page 21