TWI225680B - Method of fabricating a bottle shaped deep trench for trench capacitor dram devices - Google Patents
Method of fabricating a bottle shaped deep trench for trench capacitor dram devices Download PDFInfo
- Publication number
- TWI225680B TWI225680B TW92125401A TW92125401A TWI225680B TW I225680 B TWI225680 B TW I225680B TW 92125401 A TW92125401 A TW 92125401A TW 92125401 A TW92125401 A TW 92125401A TW I225680 B TWI225680 B TW I225680B
- Authority
- TW
- Taiwan
- Prior art keywords
- deep trench
- bottle
- silicon nitride
- trench
- shaped
- Prior art date
Links
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
12256801225680
發明所屬之技術領域 本發明係關於一種半導體製程,尤指 中I作狀狀(bottle-shaped)溝渠之 一種於半導體 基底 先前技術 隨著各 計也必 DRAM 元 一,其 渠電容 片空間 下,電 (capac 荷資訊 如何增 種電子產 須符合高 件結構即 係在半導 ,因而可 。然而, 容的面積 i tance ) 較難被偵 加電容的 口口朝小型化發 藉隹译 古—命臂勢,DRAM元件的設FIELD OF THE INVENTION The present invention relates to a semiconductor process, and more particularly to a bottle-shaped trench in a semiconductor substrate. In the prior art, DRAM elements are required along with each meter. Under the trench capacitor space, Electricity (how to increase the capacity of capac charge information must comply with the structure of high parts, which is tied to the semiconductor, so it is possible. However, the area of the capacity i tance) is more difficult to detect and add capacitors. Life force, design of DRAM components
之要求,而溝渠電容 二f界所廣泛採用之高密度DRAM架構之 體基材中姓刻出深溝渠並於其内製^溝 ”:小記憶單元之尺寸,*善利用晶 隨者製程線寬縮小至0.U微米,甚至以 也隨之減少,直接影響到電容的電容值 不足的電谷值將使得儲存在電容内的 測到,造成項取插作上的困擾。因此, 電容值實乃當務之急。 如熟習該項技藝者所知,增加電容值最直接有效的方法 之一就是增加電容表面積。習知技術中如由國際商業機 器(International Business Machines Corp·, IBM)公 司於2001年8月14曰提出申請的美國專利第6448131號, 題目為「一種增加溝渠電容電容值的方法(METHOD FOR INCREASING THE CAPACITANCE OF A TRENCH CAPACITOR)」即揭露利用金屬矽化物將溝渠表面粗糙Deep trenches are carved in the bulk substrate of the high-density DRAM architecture widely used in trench capacitors and f-fields, and trenches are made in them ": the size of small memory cells, and the best use of crystal follower process lines The width is reduced to 0. U microns, and even it is reduced accordingly. The electric valley value that directly affects the insufficient capacitance value of the capacitor will cause the measurement stored in the capacitor to cause troubles in terms of interpolation. Therefore, the capacitance value It is a matter of urgency. As those skilled in the art know, one of the most direct and effective ways to increase the capacitance value is to increase the surface area of the capacitor. In the known technology, for example, the International Business Machines Corp. (IBM) company in 2001 U.S. Patent No. 6,448,131, filed on August 14th, entitled "Method for Increasing Trench Capacitance (METHOD FOR INCREASING THE CAPACITANCE OF A TRENCH CAPACITOR)" discloses the use of metal silicide to roughen the trench surface
第7頁 1225680 ____案號 92125401_年月曰_修正_ 五、發明說明(2) 化,然後再將金屬矽化物移除以獲得較大的電容面積。 藉由控制金屬密度、金屬膜的厚度、矽化物的金屬相以 及選擇適當的金屬等參數,就可以決定溝渠表面被粗糙 化的程度。 習知技術又如IBM公司在2000年11月18日提出申請的美國 專利第6555430號,題目為「一種增加DRAM溝渠電容值的 製程(PROCESS FLOW FOR CAPACITANCE ENHANCEMENT IN A DRAM TRENCH)」則揭露在溝渠下部的表面上先形成不 連續的(discontinuous)多晶石夕層,不連續的多晶石夕層之 間具有許多的間隙,然後進行氧化以及蝕刻形成波浪式 (wavy)的溝渠表面,藉此增加電容面積。 另一種常用以增加電容面積的作法係將深溝渠的下部進 一步蝕刻成瓶狀(bottle-shaped),該等習知技術如西門 子(Siemens Aktiengesellschaft)與 IBM 公司所共有,並 在1998年6月26日提出申請之美國專利第60181 74號,題 目為「具有磊晶埋入層之瓶狀溝渠電容(BOTTLE-SHAPED TRENCH CAPACITOR WITH EPI BURIED LAYER)」揭露於半 導體基底中形成具有瓶狀下部之深溝渠,然後於深溝渠 的瓶狀下部表面上形成磊晶層作為電容之電極。Page 7 1225680 ____Case No. 92125401_Year Month_Amendment__ 5. Description of the invention (2) and then remove the metal silicide to obtain a larger capacitance area. By controlling the metal density, the thickness of the metal film, the metal phase of the silicide, and the selection of an appropriate metal, the degree of roughening of the trench surface can be determined. The conventional technology is also disclosed in the US patent No. 6555430 filed by IBM on November 18, 2000, entitled "A PROCESS FLOW FOR CAPACITANCE ENHANCEMENT IN A DRAM TRENCH". A discontinuous polycrystalline layer is first formed on the lower surface, and there are many gaps between the discontinuous polycrystalline layer, and then oxidized and etched to form a wavy trench surface, thereby Increase the capacitor area. Another method commonly used to increase the capacitance area is to further etch the lower part of the deep trench into a bottle-shaped. Such conventional technologies, such as Siemens Aktiengesellschaft and IBM Corporation, were shared on June 26, 1998. U.S. Patent No. 60181 74, filed on the same day, entitled "BOTTLE-SHAPED TRENCH CAPACITOR WITH EPI BURIED LAYER" was disclosed in a semiconductor substrate to form a deep trench with a bottle-shaped lower portion. Then, an epitaxial layer is formed on the bottle-shaped lower surface of the deep trench as a capacitor electrode.
又如Toshiharu等人於1998年5月28曰提出申請,專利權 由IBM公司所持有之美國專利第6190988號,其題目為 「用於DRAM儲存電極之受控制瓶狀溝渠製法(METHOD FORFor another example, Toshiharu et al. Filed an application on May 28, 1998. The patent right is US Patent No. 6,190,988 held by IBM Corporation, entitled "Controlled Bottle Trench System for DRAM Storage Electrodes (METHOD FOR
第8頁 1225680 _案號92125401__年 $ 日 修正_ 五、發明說明(3) A CONTROLLED BOTTLE TRENCH FOR A DRAM STORAGE NODE)」,揭露一種以兩次蝕刻步驟形成瓶狀溝渠之方 法。首先於基底中蝕刻出第一深度的溝渠,然後以矽氧 層以及氮化矽層保護溝渠側壁,接著繼續進行蝕刻,形 成更深的溝渠’接著在未被保護層遮蔽之溝渠内壁上植 入摻質’然後將摻雜摻質之溝渠側壁蝕刻掉,形成瓶狀 溝渠下部,最後再移除位於溝渠頸部側壁上的矽氧層以 及氮化矽層。 又如Shiao等人於2000年4月19曰提出申請,由茂德 (Promos Tech·, Inc)公司所持有之美國專利第6 3 6 548 5 號’其題目為「於瓶狀深溝渠中形成埋入電極盤之dram 技術(DRAM TECHNOLOGY OF BURIED PLATE FORMATION OF BOTTLE-SHAPED DEEP TRENCH)」,揭露一種瓶狀深溝渠 的作法’包括於基底中蝕刻出深溝渠,然後於深溝渠中 填入介電層,回蝕刻該介電層至預定深度,然後於該介 電層上之該深溝渠側壁上形成氮化矽側壁子,接著去除 該介電層’暴露出該氮化矽側壁子下方之該深溝渠側 壁’然後氧化該深溝渠下部所暴露出來的基底,形成矽 氧層’最後餘刻掉該石夕氧層,而得到瓶狀深溝渠結構。 然而’上述習知技藝所教授之瓶狀溝渠作法仍然過於繁 ί貞複雜’步驟太多而冗長,因此使得成本較高、效率低 且降低產能。由此可知,習知製作瓶狀深溝渠電容之該 等技藝仍有進一步改善之空間與必要。Page 8 1225680 _Case No. 92125401__ Year $ Day Amendment_ V. Description of the Invention (3) A CONTROLLED BOTTLE TRENCH FOR A DRAM STORAGE NODE ", discloses a method for forming a bottle-shaped trench in two etching steps. First, trenches of a first depth are etched into the substrate, and then the sidewalls of the trenches are protected by a silicon oxide layer and a silicon nitride layer, and then etching is continued to form deeper trenches. Then implanted doped on the inner wall of the trenches not covered by the protective layer. Then, the sidewalls of the doped doped trenches are etched away to form the lower part of the bottle-shaped trench. Finally, the silicon oxide layer and the silicon nitride layer on the sidewall of the trench neck are removed. For another example, Shiao et al. Filed an application on April 19, 2000. US Patent No. 6 3 6 548 5 held by Promos Tech, Inc. was titled "Forming in a Bottle-shaped Deep Trench." DRAM TECHNOLOGY OF BURIED PLATE FORMATION OF BOTTLE-SHAPED DEEP TRENCH ", reveals a method of bottle-shaped deep trenches, including etching deep trenches in the substrate and filling the dielectrics in the deep trenches. Layer, etch back the dielectric layer to a predetermined depth, and then form a silicon nitride sidewall on the sidewall of the deep trench on the dielectric layer, and then remove the dielectric layer to expose the silicon nitride sidewall below the silicon nitride sidewall. The side wall of the deep trench can then oxidize the substrate exposed at the lower part of the deep trench to form a silicon oxide layer. Finally, the stone layer can be etched away to obtain a bottle-shaped deep trench structure. However, the bottle-shaped trench method taught by the above-mentioned conventional techniques is still too complicated and complicated. The steps are too many and lengthy, which makes the cost higher, the efficiency is lower, and the productivity is reduced. From this, we can see that there is still room and necessity for further improvement of these techniques for bottle-shaped deep trench capacitors.
1225680 _案號 92125401 五、發明說明(4) 曰 修正 發明内容 據此,本發明之主要目的在提供一改良之瓶狀深溝渠製 作方法,可應用於溝渠電容DRAM積體電路製程。 本發明之較佳實施例係揭露一種製作瓶狀深溝渠之方 法,包含有提供一基底,其上設有一襯墊層;蝕刻該襯 墊層以及該基底,形成一深溝渠,其具有垂直側壁以及 底面;於該深溝渠垂直側壁以及底面上沈積一氮化矽保 護層;以離子轟擊部分位於該深溝渠上部之該氮化矽保 護層;選擇性地蝕刻掉被離子轟擊之該氮化矽保護層, 暴露出該深溝渠上部之該基底,且留下之位於該深溝渠 下部之該氮化矽保護層構成一氮化矽遮罩;氧化該深溝 渠上部之暴露基底,形成一頸部氧化矽層;選擇性地去 除該氮化矽遮罩;以及利用該頸部氧化矽層為蝕刻遮 罩,等向性蝕刻未被該頸部氧化矽層覆蓋之該深溝渠垂 直側壁以及底面,如此形成一瓶狀深溝渠。該離子爲擊 係利用包括氬及氮氣等惰性氣體並以3。至7。左右的斜角度 方式進行,離子轟擊能量約為20KeV左右,而離子轟擊的 劑量約為1E15至1E16 atoms/cm2左右。 為了使 貴審查委員能更近一步了解本發明之特徵及技 術内容,請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與輔助說明用,並非用來對本發明1225680 _ Case No. 92125401 V. Description of the Invention (4) Name Amendment Summary of the Invention According to this, the main object of the present invention is to provide an improved method for manufacturing a deep trench in a bottle shape, which can be applied to the manufacturing process of a trench capacitor DRAM integrated circuit. A preferred embodiment of the present invention discloses a method for manufacturing a bottle-shaped deep trench, which includes providing a substrate having a cushion layer thereon; etching the cushion layer and the substrate to form a deep trench having a vertical sidewall And a bottom surface; a silicon nitride protective layer is deposited on the vertical sidewalls and the bottom surface of the deep trench; the silicon nitride protective layer located on the upper part of the deep trench is bombarded with ions; and the silicon nitride is selectively etched away by the ion bombardment A protective layer exposes the substrate above the deep trench, and the silicon nitride protection layer located below the deep trench forms a silicon nitride mask; the exposed substrate above the deep trench is oxidized to form a neck A silicon oxide layer; selectively removing the silicon nitride mask; and using the neck silicon oxide layer as an etching mask to isotropically etch the vertical sidewalls and bottom surfaces of the deep trench not covered by the neck silicon oxide layer, This forms a bottle-shaped deep trench. This ion is made of an inert gas including argon and nitrogen. To 7. Left and right oblique angle method, the ion bombardment energy is about 20KeV, and the ion bombardment dose is about 1E15 to 1E16 atoms / cm2. In order to make your reviewers understand the features and technical contents of the present invention more closely, please refer to the following detailed description and drawings of the present invention. However, the drawings are only for reference and auxiliary explanation, and are not intended to be used for the present invention.
第10頁 ^5680Page 10 ^ 5680
加以限制者。 實施方式 2參閱圖一至圖九,圖一至圖九為本發明較佳實施例製 瓶狀溝渠之剖面示意圖。如圖一所示,首先提供一半 導體基底ίο,例如矽基底,其具有一主表面(main、 s^rface)ll,於主表面η上將形成各種半導體元件。接 著’依序於半導體基底1〇的主表面丨丨上形成襯氧化矽層 1 2以及襯氮化矽層丨4,其中襯氧化矽層丨2可以利用熱氧 化方式成長至50埃或以下之厚度,襯氮化矽層14可以化 學氣相沈積(chemical vapor deposition, CVD)法形 成。 如圖二所示,接著進行一黃光製程,於襯氮化矽層14上 形成一光阻層1 5 ’其具有開口 1 7,定義出欲形成深溝渠 之位置與形狀。如圖三所示,接著進行深溝渠乾蝕刻製 程,經由光阻層1 5的開口 1 7蝕刻襯氮化矽層丨4、襯氧化 矽層12以及半導體基底1〇,形成深溝渠2〇,其深度約為 基底表面以下7微米或更深。深溝渠2〇具有垂直側壁21以 及底面2 2。需注意的是,進行深溝渠乾蝕刻製程的同時 亦會梢微橫向姓刻掉深溝渠口附近部分的襯氧化矽層 12,使襯氧化矽層12輕微向後拉(puU back),形成在深 溝渠口附近的環形缺口 2 5。Limiters. Embodiment 2 Refer to FIGS. 1 to 9, which are schematic cross-sectional views of bottle-shaped trenches made according to a preferred embodiment of the present invention. As shown in FIG. 1, a semi-conductive substrate is first provided, such as a silicon substrate, which has a main surface (main, surface) 11 and various semiconductor elements will be formed on the main surface n. Next, a silicon oxide-lined layer 12 and a silicon nitride-lined layer 4 are formed on the main surface of the semiconductor substrate 10 in sequence. The silicon-oxide-lined layer 2 can be grown to 50 angstroms or less by thermal oxidation. The thickness of the silicon nitride-lined layer 14 can be formed by a chemical vapor deposition (CVD) method. As shown in FIG. 2, a yellow light process is next performed to form a photoresist layer 15 ′ on the silicon nitride-lined layer 14. The photoresist layer 15 has openings 17 and defines the position and shape of a deep trench to be formed. As shown in FIG. 3, a deep trench dry etching process is then performed, and the silicon nitride liner layer 4, the silicon oxide liner layer 12, and the semiconductor substrate 10 are etched through the opening 17 of the photoresist layer 15 to form a deep trench 20. Its depth is about 7 microns or more below the surface of the substrate. The deep trench 20 has a vertical side wall 21 and a bottom surface 22. It should be noted that, during the deep trench dry etching process, the silicon oxide lining layer 12 near the mouth of the deep trench is engraved in the lateral direction, so that the silicon oxide lining layer 12 is pulled back slightly (puU back) and formed in the deep Annular notches near the ditch opening 2 5.
第11頁 1225680 ___案號年 日 修正_ 五、發明說明(6) 如圖四所示’進行一化學氣相沈積製程,於襯氮化矽層 14上、深溝渠2〇的垂直側壁21以及底面22上沈積一厚度 約介於200至350埃左右之氮化矽保護層32。氮化矽層32 同時填滿形成在珠溝渠口附近的環形缺口 2 5。 如圖五所示’接著進行一斜角度離子轟擊(b〇mbardment) 製程,利用惰性氣體離子,例如氬或氮氣電漿等,以與 半導體基底10的主表面11垂直軸傾斜3。至7。左右的角度轟 擊深溝渠上部的氮化矽保護層3 2。以使用氮氣離子轟擊 為例,劑量約為1E15至1E16 atoms/cm2左右,轟擊的能量 ^2〇KeV左右。進时行該斜角度離子轟擊(bombardment)製 Ϊ之! 2 ί ί使深溝渠上部的氮化石夕保護層3 2結構鬆 散,而旎夠與位於深溝渠下部未被 護層32產生蝕刻率差昱。 卞彝擎之亂化石夕保 丨六所示 選擇性 .層 32, ,經過 下部未 〜6 : 1 ( 的氮化 原先填 護層32 矽保護 地去除 暴露出 離子轟 被離子 以磷酸 矽保護 滿形成 ,經過 層32形 ,進行 深溝渠 半導體 擊處理 轟擊之 溶液進 層3 2構 在深溝 濕Μ刻 成環狀 上部經過離子轟擊過的氮化矽 基底1 0。根據本發明之較佳實 過的氮化矽保護層3 2與位於深 ^化石夕保護層3 2之蝕刻率比約 行濕蝕刻時)。位於深溝渠下部 成氮化矽遮罩33。需注意的口 渠口附近的環形缺口25的氮化 之後’剩餘留在環形缺口 2 5的 氮化矽層3 4。 ^25680Page 11 1225680 ___ Case No. Amendment _V. Description of the Invention (6) As shown in Figure 4 ', perform a chemical vapor deposition process on the silicon nitride layer 14 and the vertical sidewall 21 of the deep trench 20. A silicon nitride protective layer 32 is deposited on the bottom surface 22 to a thickness of about 200 to 350 angstroms. The silicon nitride layer 32 simultaneously fills the annular gap 2 5 formed near the mouth of the bead trench. As shown in FIG. 5 ', an oblique angle ion bombardment process is then performed, using an inert gas ion, such as argon or nitrogen plasma, to incline 3 with the vertical axis of the main surface 11 of the semiconductor substrate 10. To 7. The left and right angles bombarded the silicon nitride protective layer 32 on the upper part of the deep trench. Taking nitrogen ion bombardment as an example, the dose is about 1E15 to 1E16 atoms / cm2, and the energy of the bombardment is about ^ 2 KeV. During the oblique angle ion bombardment (bombardment), the structure of the nitrided stone protective layer 3 2 in the upper part of the deep trench is loosened, and the etching rate difference with the unprotected layer 32 located in the lower part of the deep trench is loose. Yu. Fossil Yubao, the turmoil of Yiqing, shows the selectivity shown in Fig. 6. Layer 32, passes through the lower layer of the original protective layer 32 ~ 6: 1 (Nitride to protect the silicon), and exposes the ion bombardment, which is formed by the protection of ions with silicon phosphate. After layer 32 is formed, the solution subjected to deep trench semiconductor strike treatment is bombarded into layer 32. The structure is carved in deep trench wet M to form a ring-shaped silicon nitride substrate 10 which has been ion bombarded in the upper part. The preferred nitrogen according to the present invention The etching ratio of the silicon protective layer 32 and the deep-fossil protective layer 32 is about the same as that of wet etching). A silicon nitride mask 33 is formed below the deep trench. It should be noted that after the nitridation of the annular notch 25 near the mouth of the trench, the silicon nitride layer 3 4 remaining in the annular notch 2 5 remains. ^ 25680
如圖七 蓋之深 4 2,如 罩33上 例,熱 如圖八 氮化石夕 法,暴 利用熱 矽層42 溝渠下 氫氟酸 ,進行一氧化製程,在未被氮化矽遮罩3 3覆 /渠20表面上形成熱氧化矽(thermal oxide)層 其位置約介於環狀氮化矽層3 4以及氮化砍遮 2之間的深溝渠2 〇上部。根據本發明之較佳實施 I化石夕層42的厚度約為丨00至35〇埃之間。 遮$ 接著’選擇性地姓刻掉位於深溝渠下部的 $ =33,例如利用熱磷酸溶液等已知的濕蝕刻 :出深溝渠20的部分表面。如圖九所*,接著, 矽層4 2為蝕刻遮罩,以氨水蝕刻未被熱氧化 部δί) ^ ΐ ί渠2〇側壁21以及底面22,形成瓶狀深 i液。。酼後’去除熱氧化矽層4 2,例如利用豨釋 之較佳實施例,凡依本發明申請專 化與修飾’皆應屬本發明專利之涵 以上所述僅為本發明 利範圍所做之均等變 蓋範圍。As shown in Figure 7, the depth 4 of the cover, as in the case of the cover 33, the heat is as shown in the nitride method, using the hydrofluoric acid under the trench 42 of the hot silicon layer to perform an oxidation process, without the silicon nitride mask 3 A thermal oxide layer is formed on the surface of the cover / ditch 20, and the position of the thermal oxide layer between the ring-shaped silicon nitride layer 34 and the nitride trench 2 is at the upper part. According to a preferred implementation of the present invention, the thickness of the fossil evening layer 42 is between about 00 and about 350 angstroms. Shield $ and then 'selectively engraved $ = 33 located in the lower part of the deep trench, for example, using a known wet etch such as hot phosphoric acid solution: a part of the surface of the deep trench 20 is formed. As shown in Fig. 9 *, the silicon layer 42 is an etching mask, and the non-thermally oxidized portion δ) is etched with ammonia water. The side wall 21 and the bottom surface 22 of the channel 20 form a bottle-shaped deep liquid. . Afterwards, 'remove the thermal silicon oxide layer 42, for example, using the preferred embodiment of the interpretation, any application for specialization and modification according to the present invention' shall fall within the scope of the patent of the present invention. The range of equal change covers.
1225680 _案號92125401_年月曰 修正_ 圖式簡單說明 圖式之簡單說明 圖一至圖九為本發明較佳實施例製作瓶狀溝渠之剖面示 意圖。1225680 _ Case No. 92125401_ Year Month Amendment _ Brief Description of Drawings Brief Description of Drawings Figures 1 to 9 are schematic cross-sectional views of a bottle-shaped trench made in a preferred embodiment of the present invention.
圖 式之 符 號 說 明 10 半 導 體 基 底 11 主 表 面 12 襯 氧 化 矽 層 14 襯 氮 化 矽 層 15 光 阻 層 17 開 V 20 深 溝 渠 21 側 壁 22 底 面 25 環 形 缺 α 32 氮 化 矽 保 護 層 33 氮 化 矽 遮 罩 34 環 狀 氮 化 矽 層 42 熱 氧 化 矽 層 50 瓶 狀 深 溝 渠 下部Explanation of the symbols of the drawings 10 Semiconductor substrate 11 Main surface 12 Lined with silicon oxide layer 14 Lined with silicon nitride layer 15 Photoresist layer 17 Open V 20 Deep trench 21 Side wall 22 Bottom surface 25 Ring-shaped α 32 Silicon nitride protective layer 33 Silicon nitride Mask 34 Ring silicon nitride layer 42 Thermal silicon oxide layer 50 Lower part of deep trench
第14頁Page 14
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW92125401A TWI225680B (en) | 2003-09-15 | 2003-09-15 | Method of fabricating a bottle shaped deep trench for trench capacitor dram devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW92125401A TWI225680B (en) | 2003-09-15 | 2003-09-15 | Method of fabricating a bottle shaped deep trench for trench capacitor dram devices |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI225680B true TWI225680B (en) | 2004-12-21 |
TW200511492A TW200511492A (en) | 2005-03-16 |
Family
ID=34588317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW92125401A TWI225680B (en) | 2003-09-15 | 2003-09-15 | Method of fabricating a bottle shaped deep trench for trench capacitor dram devices |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI225680B (en) |
-
2003
- 2003-09-15 TW TW92125401A patent/TWI225680B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW200511492A (en) | 2005-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7439128B2 (en) | Method of creating deep trench capacitor using a P+ metal electrode | |
TW426940B (en) | Manufacturing method of MOS field effect transistor | |
JP2000150817A (en) | Semiconductor device and its fabrication | |
US8173515B2 (en) | Method for manufacturing semiconductor device | |
TW544867B (en) | Integrated circuit fabrication | |
US6846744B1 (en) | Method of fabricating a bottle shaped deep trench for trench capacitor DRAM devices | |
KR20050052005A (en) | Semiconductor device with trench type isolation and method for making the same | |
US7943474B2 (en) | EDRAM including metal plates | |
TW466684B (en) | Method for forming deep trench capacitor under shallow trench isolation structure | |
TW511248B (en) | Method to produce capacitor-electrodes | |
WO2022160625A1 (en) | Semiconductor structure and manufacturing method for semiconductor structure | |
TW454247B (en) | Ionized metal plasma Ta, TaNx, W, and WNx liners for gate electrode applications | |
TWI225680B (en) | Method of fabricating a bottle shaped deep trench for trench capacitor dram devices | |
WO2022001592A1 (en) | Semiconductor structure and manufacturing method therefor | |
TW399287B (en) | Structure of bottle-shaped deep trench and its manufacturing method | |
US6835641B1 (en) | Method of forming single sided conductor and semiconductor device having the same | |
TW583746B (en) | Method of forming a bottle trench | |
KR20070065482A (en) | Method of manufacturing a floating gate in non-volatile memory device | |
KR100429421B1 (en) | Shallow Trench Forming Method for Semiconductor Isolation | |
US11817484B2 (en) | Method for manufacturing an electronic device | |
TWI239047B (en) | Use of masks made from metal oxides for the treatment of surfaces during the fabrication of microchips | |
CN114005737B (en) | Semiconductor structure and semiconductor structure manufacturing method | |
CN113937054B (en) | Semiconductor structure and manufacturing method thereof | |
JP7527381B2 (en) | Semiconductor structure and method of manufacture thereof | |
TW447040B (en) | Method for preventing high-density plasma damage during a shallow trench isolation process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |