TWI223841B - BiCMOS process utilizing emitter poly-silicon etching mask for contact implantation - Google Patents

Abstract

A P+ contact implantation process of BiCMOS device is disclosed. The BiCMOS device is made on a semiconductor substrate and consists of NMOS transistor, PMOS transistor and bipolar transistor. The method comprises the following the steps of first using an emitter poly-silicon etching mask to define PR pattern on the substrate to cover the emitter poly-silicon connected by the bipolar transistor; and executing the P+ contact implantation, wherein the source and drain areas of the NMOS and PMOS transistors and the base poly-silicon of the bipolar transistor are exposed to the P+ plug implantation environment.

Description

1223841 V. Description of the invention (1), Field of invention: This invention relates to a BICMOS process that combines a bipolar transistor and a complementary metal-oxide-semiconductor (CMOS), especially an application of an emitter polycrystal BIC Μ 0 S manufacturing process of contact masking (c ο ntactimp 1 ant) by Shi Xixing engraved photomask. The previous technology has been widely used as “convenience and practical technology”. And, speaking, applying benefits and digitization of valence electronics, making traditional stoves and coffee-making remote control information products as an example, and using stronger and better values to continue to develop new generation appliances such as coffee pots or Internet Products, such as the development and progress of various services. In addition, in order to provide consumer information appliances, combined products, such as televisions and small appliances, can be used to control the functions of appliances. Computer and personal digital processing The function of wireless transmission and service content. Therefore, for the target body and software, it is often determined that various electricity consumers are better new software refrigerators, or a computer and a computer. In addition, electronic devices and scans are used to carry out pre-electronic operations and hardware of the product sub-product. It is a bake network, a wide range of devices, and digital transmission products. In order to provide better radio frequency (RF) and microwave communication performance for these communication components, it has a B i C Μ 0 S driven by south speed and south current. Components are widely used. Especially with the progress of the integrated circuit manufacturing process, the new generation BiCMOS device has the advantages of high frequency bandwidth and low noise, and has become the mainstream of manufacturing communication components. However, in order to continuously improve the execution speed and operation functions of electronic products,

Page 5 1223841 V. Description of the invention (2) Further improving the high-frequency operation performance of BiCMOS elements (increasing the bandwidth and reducing noise) and reducing the base resistance of the bipolar transistor have become the efforts of various manufacturers. direction. In order to improve the high-frequency performance of BiCMOS devices, in the current integrated circuit manufacturing process, quite a few methods have been used to reduce the base resistance, such as increasing the bipolar transistor (B i ρ 〇 1 ar) base polycrystalline silicon. Dopant dose for ion implantation, or increase the ion dose in the doped base region to reduce the base resistance as much as possible. However, when these methods are used to improve the base resistance value, many marginal effects are often generated, and the performance of the device cannot be optimized, or the frequency is reduced. Please refer to the first figure. Taking a typical CMOS device manufacturing process as an example, after defining NMOS device 10 and PM0S device 12 on the semiconductor substrate 14, several layers will be deposited next. The insulating layer 16 is formed on the NM0S element 1 0 and the pmos element 12 and the contact hole is defined by the lithography process. 8 and 2 〇 on the insulating layer 6

Then, the source / drain regions 22 and 2 4 ′ of the NMOS element 10 and the PM0S element 12 are exposed, respectively, and then metal materials are filled in the contact holes 18 and 20 to form conductive plugs. Generally speaking, in order to improve the conductivity of the source / drain region 2 2 or 24, a contact implantation process is performed before the conductive plug is defined, and a silicided metal is produced at the source. Surfaces of the pole / drain regions 22, 24. It is worth noting that the pM〇s

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1223841

V. Description of the invention (3) The P + contact implantation of the source / > and the electrode region 24 of the element 12 is a blanket ion implantation procedure. That is, as shown in the first figure, when the ^ contact implantation procedure 26 is performed, no additional photoresist is used to shield the NM0s element 10, so the source / non-electrode region 22 is implanted at the P + contact. Program 26 will show * full exposure. & Although in traditional CMOS device fabrication, blanket p-type implantation procedures are used to dop the source / drain region 24 of the PM0S device 12, do you want to use a combination When the CM0s is connected to the BiCM0s element of the transistor (bottom = BiP0lar), it will be completely exposed to the blanket p + contact cloth because of the Bipou n type and Umitter. Plant environment. In order to change the conductivity of the N-type emitter,

BiCMOS cannot meet the specifications. In the current BiMOS PM0S element made by the casual clothes, the source / not to overcome the problem of N-type emitter characteristics change, the King of Spears often uses a PSD mask to perform the above-mentioned polar region (S / D). p + contact implantation procedure. Please refer to the second figure.

In addition to the component 10 and the PM0S component 12, the above-mentioned NM0S component 28 will also be used in the vehicle. This Blp0Ur yuan f cattle system. The N-type emitter region 32 located on the upper surface, and the N-type emitter region 30 and the N-type buried layer 34 below, and the surrounding n soil electrode region 30 pass through the potential region 30 and the emitter region. Above 32, and 82: a: Zhi, 36 links. In the base and knife, do n’t mean the base polycrystalline silicon 3 8

1223841 V. Description of the invention (4) In addition, the contact holes 4 2 are also made on each of the 4 and 6 so that the pole polycrystalline stone 3 8 and the emitter polycrystalline stone 40 are used as electrodes above the electrodes. , 4 4 The subsequent metal connection process. 々The photoresist 48 shown in the second figure is defined when the P + contact implantation procedure is performed using the PSD mask. This photoresistor 48 will cover the entire Bip0ar element 28 and the NMOS device 10, and only the source / drain region 24 of the pM0s element 12 will be exposed, so that the P + contact implantation process is applied continuously. At 50, only the p-type source / drain region 24 will be ion-implanted, and it will not be susceptible to an electric current of the emitter polycrystalline silicon = 4 =. However, it is performed using a photomask. Contact cloth: = ^ NMOS το The source / drain region 22 of the piece 10 is also ambiguous from the photoresist 48. _ The components will not match the specifications in the traditional process (see the method in the figure). Module ί :: 3 Information of chip design industry that is gradually moving towards standardization and standardization;: Production: 5 component specifications cannot be related to this expenditure. Therefore, if it can be ^, it will cause the design industry to have additional β-na component specifications In the case of "same: formula", the resistance value performance under the traditional South frequency operation is dictated. 〇31 " Based on operating efficiency, and promotes the development of the overall body circuit generation that can further improve the circuit components. Summary of the invention: In order to improve the high-frequency operation efficiency of the bipolar silicon-based polycrystalline silicon 8 pages 1223841 V. Description of the invention (5) Yes, the present invention provides a method for reducing the base silicon resistance value through the p + contact implantation process. In addition, the present invention also provides a method for CM in the BiCM0s process. 〇s yuan, ϊ ϊ 覆 Overlay p + contact implantation program, and it does not affect the characteristics of the dual-carrier connection electric sun and solar body.. The present invention provides a kind of BicMOS element? + Contact implantation program in one The method includes at least the following steps: 'Firstly, a βιS element body is fabricated, and its CMOS element includes a NMOS transistor doped with ":", and a transistor is connected to a pair of carriers. Then, a layer is formed on the double layer. The emitter is connected to the emitter region of the transistor.: Use the emitter polycrystalline silicon etching mask to define the first photoresist on the polycrystalline silicon layer. Emission: ί etched doped polycrystalline silicon layer to define the body located on the upper surface of the emitter region: Xi: Then, an insulating layer is deposited on the semiconductor substrate = electricity and a number of contact holes are defined in the insulating layer to expose the collector region… = pole…, base…, and resistance in the Fengdao #, _ 人 用 电极Polycrystalline silicon etch mask, defining the second Look at == connect ::; live-emitter poly-crystal, holding PM " ta ^ ^ 'NM〇S f ^ ^ ^ the base / drain region of the transistor, and the double-carrier connection in the plant environment. White + Ion cloth according to the ρ + contact implantation procedure 1223841 V. Description of the invention (6) Implementation method: Please refer to the third figure, as mentioned above, in the manufacturing process of BiCMOS devices, semiconductor substrates 14 and 14 will be separately manufactured and included. A CMOS element of the NMOS transistor 1 10 and the PMOS transistor 1 12 and an NPN type bipolar junction transistor 128 (Bipolar). Among them, the fabricated NMOS transistor 110 includes a gate 111 on the upper surface of the semiconductor substrate 114 and source / inverted regions 1 22 on both sides. Similarly, the PM0S transistor 11 2 adjacent to the NMOS transistor 1 1 0 also includes the gate electrode located on the upper surface of the semiconductor substrate 4 and the source electrodes 3 on both sides; and the electrode region 1 2 4. As for the N M 0 S transistor 1 1 0, ρ μs transistor 112, and the bipolar element 128, a field oxide block (1? (^) 1 2 5 is used to isolate it. As for the produced B The i po 1 ar element 1 2 8 includes a P-type base region 130 defined on the upper surface of the semiconductor substrate 114, and is defined at the center of the base region 1301 surface using an ion doping procedure to define— N-type emitter region 132. That is, when viewed from above the semiconductor substrate 114, the base region 130 is just around the emitter region 132. At the peripheral position of the base region 130, ϋα is re-doped High-concentration bases

The regions 13, ,, and are connected to the subsequent base electrodes. Below the base region η, a N-type buried layer (buried 2 body left extension '❼) is connected to the N-type collector region 136 which is also defined on the semiconductor substrate; 1 is connected to the N-type collector region 136 on the left side of the region 130, as shown in the second figure No. Between the base region 130 and the collector region 136

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The collector conductive plugs of the rods J, 4, and $ generate better electrical connection, and can be doped with ions of 1 ^ + = \ degrees, while forming an N ++ concentrated dopant on the surface of the collector region 136. Miscellaneous area 137. ―After this, the base region 13 0 and the emitter region 13 2 are followed, and then a conductive plug made of base polycrystalline silicon and emitter polycrystalline silicon will be produced on the surface of the miscellaneous region. Generate a link. First, an IPur ^ 115 can be deposited on the semiconductor substrate 114 to cover the source / drain regions 1 2 2 and 1 2 4 of the NM0S transistor Λ transistor B 1 2 and cover N 2 + + Collector; Chen doped region 丨 3 7. Then, a polycrystalline silicon layer, a dielectric layer 117, and a polycrystalline silicon layer 141 are deposited on the semiconductor substrate 114 in order, and the above-mentioned protective layer 115 and the bipolar element 128 are duplicated. Next, a ^ mask (a mask used to define the emitter poly pattern) can be used to define a photoresist 1 50 on the polycrystalline silicon layer 1 4 1 and cover the emitter region 1 3 \ ', and then perform the plasma etching process to remove the unnecessary polycrystalline silicon layer 1 4 1, and define the required emitter polycrystalline silicon 丨 4, as shown in the fourth figure. After the emission of polycrystalline silicon 1 4 0, a lithographic etching process can be performed again to etch the dielectric layer 1 1 7 and the polycrystalline silicon layer 1 3 9 to define the base polycrystalline silicon required for k 3 8 pattern. . Please refer to the fourth figure, by using the BPLY mask (that is, the mask used to define the base poly pattern) 'define the photoresist 1 5 1 to the emitter poly 1 4 0 and the dielectric layer 1 1 7 , And then perform the # engraving procedure to remove unnecessary dielectric layers 1 1 7, polycrystalline silicon layers 1 3 9 and protective layers

Page 11 1223841 V. Description of the invention (8) and Table 115 above it define the residual dielectric layer 11h of the base polycrystalline silicon surface 38 in the figure, as shown in the fifth figure. Two ί: 2〉 Insulation layer formed by stacking several dielectric materials 1 1 6 ^ ,,, 1 day = 110, PM0S transistor 112 and Bipolar element 128, = then enter a lithography process The contact holes are defined in the insulating layer 1 1 6. Its Lei Yue # and 120 will expose NMOS transistor 11 () and PMOS source / drain regions 122 and 124, respectively. As for the contact holes 142, 144, and 1 46, which are located in Bipok, there will be respectively Exposing the base # =, the emitter polycrystalline silicon 14o, and the collector very heavily doped region 137, and the combination 2 points out that 'the part of the bottom of the hole exposed by the engraving process of defining the contact hole 142 is exposed. The residual dielectric layer 11 7a is removed, and the upper surface of a portion of the base polycrystalline silicon 138 is exposed. In the Yuancheng Micro-Shadow famous insect carved shoe library, you are extremely poor. After the silicon ordering, as shown in the fifth figure, the defined base 125: the upper surface domain 131 'is facing the top of the field oxidation block pole area. surface. ：：：： The crystal 4V is just made in the base. It is the base polycrystalline buckle 8. Both are ::; 』= Polycrystalline 14 ° or better conductivity. Bai Yue's way of ion doping 'makes it have a later conductive insertion: ί: ί 幵: J 二 极 触 4 :: 电 性' in the making ... belongs to the core surface of the source / drain region == and the first Page 121223841 V. Description of the invention (9) In the present invention, the above-mentioned P + contact implantation procedure is performed using the above-mentioned EpLY mask defined by the emitter polycrystalline silicon pattern. Please refer to the sixth figure. By using the EPLY mask, the photoresistor 152 shown in the figure can be defined. This photoresist 152 only covers the emitter polycrystalline silicon 14 of the bipolar element 128, and exposes the source / drain regions 124 and 122 of the PM0S το element 112 and the NM0S element 110, and the base polycrystalline silicon 138 and the collector. Thickly doped regions 3-7. After the photoresistor · 152 is defined, a p + contact implantation procedure 54 is performed to improve the conductivity of the "electron transistor" _ 1 1 2 and its source / non-electrode region 1 2 4.

It should be particularly noted that during the p + contact implantation process, 5 and 4, p and doped ions will also be doped through the contact hole 142 to the surface of the electrically conductive p-type polycrystalline silicon 138, which in turn reaches The effect of improving the conductivity of the base polycrystalline silicon 138. To the force, for the extremely densely doped region 13 with N-type conductivity, because its N + + ion doping has a relatively high concentration, compared with the concentration of the p + process is W times higher than i, so even though the set The extremely thick and rich impurity domain 1 3 7 is also directly exposed to the environment of p + contact implantation program 5 4, but its conductive characteristics will not be affected. In addition, because of the NM0S element ιι〇 '= pole / drain The area 22 is also exposed to the ring of the P + contact implantation process 154, so the CMOS device produced will conform to the current process specifications ^

The method provided by the present invention has many advantages for p + contact implantation: ^ (2) Since the existing EPLY photomask is used for implantation, it is necessary to add an additional photomask and manufacturing process. Complete the p + contact implantation process,

Page 13 1238441 V. Description of the invention (ίο) In addition to saving production costs, it can also provide better operating performance of the BiCM0s components produced; (2) P + contact implantation procedures using EPLY masks can be increased The conductivity of the base polycrystalline stone effectively improves the Z base resistance of the BiCM0s device under high frequency operation; (3) Since the source / drain region of the NMOS transistor is also exposed to the p + contact, In the implantation sequence, the CMOS device produced will conform to the current process vision, and can provide a considerable degree of convenience for circuit designers. (4) In the P + contact implantation process, the exposed polycrystalline silicon is incidentally Ion implantation on the surface can improve the conductivity of the base polycrystalline silicon, and the marginal effects common in traditional processes will not occur; (5) Take the current BiCMOS process of 0.35 micron 3 · 3/5 volt as an example. When the P + contact implantation procedure is performed using the above PSD mask, the obtained base polycrystalline silicon has a resistance value of about 131 ohms, and a resistance value of about 436 ohms is generated under high-frequency operation. However, if the method disclosed in the present invention is used to perform P + contact implantation with an EpLY mask, the base polycrystalline stone will have a resistance value of about 88 ohms, and will have about 3 9 ohms under high-frequency operation. Ohm resistance. Obviously, the method of the present invention can indeed improve the conductivity of the base polycrystalline silicon, and is beneficial to the operation mode of the high-frequency environment. Although the present invention is explained above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. Modifications made by those skilled in the art without departing from the spirit and scope of the present invention should be included in the scope of patent application described below.

Page 14! 223841 Brief description of the diagrams-By combining the following detailed descriptions with the attached drawings, the above content and the many advantages of this invention will be available. Among them, Λ, understand, and the figure is a cross-sectional view of a semiconductor wafer. Shows the current situation of the P + contact implantation process for CMOS devices in the current manufacturing method / T The cross-sectional view of the semiconductor wafer is shown in the first figure of the blanket, and the P + contact implantation is shown in the PSD mask; Cone ^ A picture is a cross-sectional view of a semiconductor wafer, showing the steps of connecting an transistor with an emitter polycrystalline silicon pattern using an EpLY light 1 A semiconductor carrier; The fourth image is a cross-sectional view of a semiconductor wafer, showing the use of a semiconductor wafer The step of connecting the transistor to the base polycrystalline silicon pattern; the shield conductor] ί T is a cross-sectional view of a semiconductor wafer, showing the step of forming a contact hole on the semiconductor substrate; and “the figure shows the cross-section of a semiconductor wafer” Figure showing the P + contact implantation procedure using an EPLY mask.

Drawing number comparison table: NM0S element 10 semiconductor substrate 1 4 contact hole 1, 8, 2 〇 + contact implantation procedure 2 6 ρ-type base region 30 N-type buried layer 34 base polycrystalline silicon 3 8 contact hole 42, 44, W PM0S element 12 Insulation layer 1 6 Source / drain region 22, 24 Diode-connected transistor element 2 8 N-type emitter region 3 2 N-type collector region 3 6 Emitter polycrystalline stone 4 0 Photoresist 48

Page 15 1238441 Schematic illustration of P + contact implantation procedure 5 0 Gate 11 1 Gate 11 3 Protective layer 11 5 Dielectric layer 117, 117a Source / drain region 1 22, 1 24 Field oxidation block 1 2 7 P-type base region 1 3 0 N-type emitter region 1 3 2 N-type collector region 1 3 6 Base polycrystalline silicon 1 3 8 Emitter polycrystalline silicon 1 4 0 Photoresistor 1 5 0, 1 5 1 Photoresistor 1 5 2 NMOS transistor 1 10 PMOS transistor 1 12 Semiconductor substrate 114 Insulating layer 1 1 6 Contact hole 1 1 8, 1 2 0 Field oxide block 1 2 5 Diode-connected transistor element 1 2 8 Very thick base Doped region 1 3 1 N-type buried layer 1 3 4 N + + collector extremely doped region 1 3 7 Polycrystalline silicon layer 1 3 9 Polycrystalline silicon layer 1 4 1 Contact holes 142, 144, 146 P + contact implantation procedure 154

Claims (1)

1223841 VI. Application Patent Scope 1. A kind of port + contact implantation of BiCMOS device. The BiCMOS device is made of a semiconductor including: 0S transistor, simple transistor, and bi-connected transistor. Bipolar), beta method includes at least the following steps: Use an emitter polycrystalline silicon to etch the mask definition to cover the following steps: # 工, * 心 我 尤The crystal is made of polycrystalline silicon. And, for the simple element in P + contact implantation, the source / drain region of the crystal and the PMMOS transistor are two or two. The NM0S is connected to the base of the multi-source transistor and / or the polar region of the transistor, and is implanted in an ion implantation environment. 'Yue Yue Shi Xi is exposed to the P + contact cloth 2. According to the method in the scope of patent application No. 1, t, f in the pot, and the crystal system is an NPN type bipolar transistor. / 、 ； 1. Carrier chain 3. If the square planting procedure of item 1 of the scope of patent application can improve the M characteristics of the base resistive core under the P + contact cloth in the base polycrystalline silicon eight, and reduce the high frequency Operation 4. The original use of the photomask in the remaining * A t Shi Xi as described in item 1 of the scope of patent application is to fix the emitter polycrystalline pattern. Shi Biyi This bipolar connection transistor 5 · — a kind of P to A in BiCMOS elements The method of the program, the Tswan method includes at least the following steps: 1223841 6. Apply for a patent to make a BlCM0s element on a semiconductor substrate, where the BiCM0S element includes a NMOS transistor, a PMOS transistor, and A bicarrier is connected to the transistor; an insulating layer is deposited on the semiconductor substrate to cover the BiCM0S element; a plurality of contact holes are defined in the insulating layer t to expose the source / drain region of the MOS transistor, the The source / drain region of the PM0S transistor, the base polycrystalline silicon, the emitter polycrystalline silicon, and the collector region that are connected to the transistor; a special hybrid ί defines a mask of the emitter polycrystalline silicon pattern, and defines a photoresistor in the On the half-V substrate, to cover the emitter polycrystalline silicon; and let ’s say, several fBlCM0S are subjected to the P + contact implantation process, where the NMOS drain region and the source of the PMOS transistor / The drain region, the base polycrystalline stone that touches the transistor, are Exposure to the ion implantation environment of the p " contact cloth implantation sequence. 6 · If the method of the scope of the patent application No. 5 is applied, the interceptor transistor system is one type, a type of double carrier transistor. The middle and upper carriers are connected 7. If the 5th planting procedure of the scope of the patent application can improve the conductivity of this base and the base spar spar under the p + contact cloth mentioned above, and reduce high-frequency operation 1 8 · If you apply for a patent, the edge layer is on the semiconductor substrate; in the deposition process described above, the steps include the following steps: Page 18: A heteropoly dream layer in the emitter region of the bipolar-connected transistor: a second photoresist on the doped polycrystalline silicon layer; a pattern; and a mask of the polysilicon pattern of the polar emitter defines the second light The "resistive crystal" method is a method of engraving the mask, and the method of implanting the contacts into the device is implemented by a CMOS element crystal and a bipolar connector package ir: 0S7t on a semiconductor substrate. μ electric transistor-ca crystal, _ Liaodian domain; forming a doped polycrystalline silicon layer on the double In the emitter region of the carrier-connected transistor, a person uses an emitter polycrystalline stone to etch the polycrystalline silicon layer; y is etched to the photomask, meaning that the first photoresist is on the upper surface of the emitter region. The doped polycrystalline silicon layer is engraved to define the pole polycrystalline stone; an insulating layer is laminated on the semiconductor substrate to cover the Bi CM0s element .: A plurality of contact holes are defined in the insulating layer towel to expose The _s electric crystal ^ ^ ^ the source / drain region of the flying solar heliosphere, the emitter polycrystalline silicon, the base polycrystalline silicon, and the collector region connected to the "transistor" transistor; and / ' Page 19 1223841 VI. Application scope Fengdao i: The second use of the emitter polycrystalline silicon etching mask, defines a second photoresist on the conductor substrate to cover the emitter polycrystalline silicon; and the HiiCM0s element The ^ contact implantation procedure was performed, in which the two sources of the MOS porosity heliosolar source / drain region, the m2 2 ^ transistor base polycrystalline silicon, were exposed to The p + contact implantation program is in an ion implantation environment. 10. According to the method of item 9 in the scope of the patent application, wherein the above-mentioned double-carrier and power-connecting crystal system is an NPN-type double-carrier transistor. 11. The method of item 9 in the patent scope, wherein the above-mentioned P + contact planting order can improve the conductive characteristics of the base polycrystalline silicon, and reduce the base resistance value under high frequency operation. * Page 20