TWI223351B - Method for discharging wafer after dry etching metal layer - Google Patents
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1223351 五、發明說明(1) 發明所屬之技術領域 本發明係有關於一種釋放晶圓上殘留電荷之方法,特 別係有關於一種於乾蝕刻金屬層後,釋放晶圓上殘留電荷 的方法。 先前技 案定義 完成( ~貫程中 再利用 離子轟 壁產生 (正電 接 聚合殘 需利用 商名) 而,由 與金屬 effect 物的清 reac t i 陽極: 術 般而言, 及之後的 i ns i t u p ,係先以 電漿轟擊 除,然而 聚合殘留 荷40 ,負 下來若僅 留物更難 一清洗液 寻溶液^ 於晶圓上 層相連的 )的影響 洗步驟時 on ): Ψ + 80H-- 現今半導體製程中,蝕刻金屬層以完成圖 光阻圖案去除皆可以在同一個製程腔體中 rocess ),如第1 A〜1 B圖所示,在這樣的 電梁鍅刻法1 5 #刻基底ΓΌ上之金-屬層2Q ~, 3 5光阻圖案3 0以使光阻圖案3 〇被高能量的 ,在經過上述製程後,很容易在金屬層側 物60 (polymer residues )及電荷累積 電荷5 0 )而影響後續製程之進行。 進行灰化步驟,只能去除光阻且將使上述 以去除。因此,傳統上在灰化步驟之後, ,例如ACT9 3 5 ( ACT為廠商名)或EKC (廠 進行一清洗步驟來去除聚合殘留物,然 累積有因電聚製程殘留下來的電荷,使得 鎢插塞會受到”電荷效應’’ (c h a r g i n g 而被離子化’並在進行之後去除聚合殘留 與清洗液發生伽凡尼反應(G a 1 v a n i c ---------〉W 042- + 4 M +6e— 1 if IS 1111 I iiliilil i II 1 IHilif 1 〇503-9547TWf(Nl) ; TSMC2002-1103;david.ptd 第6頁 1223351 五、發明說明(2) 陰極:5 02 + 3 H2 0 + 6 e_----> 6 Ο H~ 伽凡尼反應:W+ + 40H—----> W02 + 4e~ + 2H201223351 V. Description of the invention (1) Technical field of the invention The present invention relates to a method for releasing residual charges on a wafer, and in particular to a method for releasing residual charges on a wafer after dry etching a metal layer. The definition of the previous project is completed (~ the ion bombardment wall is used in the process (positive electrical polymerization needs to use the trade name), and the anode with the metallic effect is cleared ac anode: technically speaking, and later i ns Itup, it is first removed by plasma bombardment, but the polymerization residual charge is 40, and if it is left down, it is more difficult to leave only a cleaning solution (the solution is connected to the upper layer of the wafer). The effect of the washing step is on): Ψ + 80H-- In the current semiconductor process, etching the metal layer to complete the removal of the photoresist pattern can be done in the same process cavity.) As shown in Figures 1A to 1B, in this electrical beam engraving method 1 5 # 刻The gold-metal layer 2Q ~, 3 5 on the substrate Γ 光 is a photoresist pattern 3 0 so that the photoresist pattern 30 is high energy. After the above process, it is easy to place polymer residues 60 and charges on the metal layer side. The accumulated charge 50) affects the progress of subsequent processes. When performing the ashing step, only the photoresist can be removed and the above will be removed. Therefore, traditionally, after the ashing step, for example, ACT9 3 5 (ACT is the manufacturer's name) or EKC (the factory performs a cleaning step to remove the polymerization residues, but accumulates the charge remaining due to the electropolymerization process, which makes tungsten insert The plug will be subject to "charging effect" (charging and ionized) and after the removal of polymerization residues, a Galvanic reaction with the cleaning solution (G a 1 vanic ---------> W 042- + 4 M + 6e— 1 if IS 1111 I iiliilil i II 1 IHilif 1 〇503-9547TWf (Nl); TSMC2002-1103; david.ptd Page 6 1223351 V. Description of the invention (2) Cathode: 5 02 + 3 H2 0 + 6 e _---- > 6 Ο H ~ Galvanic reaction: W + + 40H —---- > W02 + 4e ~ + 2H20
而使得鐫插塞被侵I虫掉,產生斷路的現象(如第2圖中符 號65所示),在1998 年 3rd International Symposium on Plasma Process-Induced Damage 會議中也有相關的文 獻提及此現象-The Corrosion of Tungsten Due to Plasma Charging in a Metal Plasma Etcher ° 目前解決 此鎢插塞腐蝕問題的方法有美國專利第6, 387, 7 23號中揭 露了利用在低壓下通入富含氮氣的惰性氣體來對晶圓進行 一放電的程序,藉以清除累積在晶圓上的電荷,或是將鎢 插塞浸入在低pH值的溶液,如稀釋過的氮酸(n丨t f ^ ac i d )使其鈍化’或是利用電子束來對具有此鎢插塞的金 屬結構進行放電。 & 無法提供足 效且穩定的 然而,上述的放電程序在實際製程中仍然 夠且穩定的可靠度’因此需要繼續研發更為有 放電方法。 發明内容 因此,本發明之主要目的係提供一種用於 層後之晶圓放電方法,藉由在乾蝕刻金屬層後,,刻^, 射頻功率(RF POWER)下通人適量的高溫水装在=== 因電漿製程所殘留在晶圓上的電荷。 …、L 1人释1As a result, the plug was cut off by the invaded I insect, resulting in a disconnection (as indicated by symbol 65 in Figure 2). This phenomenon was also mentioned in the relevant literature at the 3rd International Symposium on Plasma Process-Induced Damage conference in 1998- The Corrosion of Tungsten Due to Plasma Charging in a Metal Plasma Etcher ° The current method to solve the corrosion problem of tungsten plugs is disclosed in U.S. Patent No. 6,387,7 23 Utilizing inert gas rich in nitrogen at low pressure To perform a discharge process on the wafer to remove the accumulated charge on the wafer, or to immerse the tungsten plug in a low pH solution, such as diluted nitric acid (n 丨 tf ^ ac id) Passivation 'or using an electron beam to discharge a metal structure with this tungsten plug. & Can't provide sufficient and stable. However, the above-mentioned discharge procedure is still sufficient and stable reliability in actual manufacturing process', so it is necessary to continue to develop more discharge methods. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for wafer discharge after a layer. After dry-etching a metal layer, engraving, an appropriate amount of high-temperature water is filled under radio frequency power (RF POWER). === The charge remaining on the wafer due to the plasma process. ..., L 1 person releases 1
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之晶圓放電方法,藉由在去除光阻圖案及聚合殘留物之製 程中通入適量的高溫水氣,藉此可使去除光阻圖案、去除 聚合殘留物及釋放晶圓電荷三道製程於同一製程腔體中一 次完成’縮短製程時間、提高生產效率。Wafer discharge method, by passing an appropriate amount of high-temperature water gas in the process of removing the photoresist pattern and the polymerization residue, thereby enabling the three processes of removing the photoresist pattern, removing the polymerization residue and releasing the wafer charge Completed in the same process cavity at a time 'reduces process time and improves production efficiency.
根據上述目的,本發明係提供一種用於乾蝕刻金屬居 後之晶圓放電方法。首先,提供一具有圖案化金屬層之^ 底’且,圖案化金屬層表面覆蓋有一圖案化光阻層。接土 =,以乾蝕刻法去除該圖案化光阻層,然後在射頻功率為 零下通入水蒸氣以釋放因形成該圖案化金屬層及乾蝕刻該 圖案化光阻層而殘留在該基底—上之電荷。 .、彳?:之其它目的及諸多優點將藉由下列較佳實施例 之评、,.田况明,及參照所附圖示,而被完全的揭露。 實施方式 本务明的一些實施例會詳細描述如下,其,— 不同部份並沒有依照實際尺寸繪製。某些尺度與盆: 相關的尺?比係被誇張的表示以提供更清楚的描述以; 熟悉此技蟄的相關人士瞭解本發明。同時, 佳實施例並非用以限定本發明之申請專利範圍/ = = 2According to the above object, the present invention provides a wafer discharge method for dry etching a metal behind. First, a substrate with a patterned metal layer is provided, and the surface of the patterned metal layer is covered with a patterned photoresist layer. Then, the patterned photoresist layer is removed by dry etching, and then water vapor is passed in at a radio frequency power of zero to release the patterned metal layer and the patterned photoresist layer remaining on the substrate—by dry etching Of its charge. ., Eh? : The other purposes and many advantages will be fully disclosed by the evaluation of the following preferred embodiments, Tian Mingming, and with reference to the attached drawings. Embodiments Some embodiments of the present invention will be described in detail as follows, in which-different parts are not drawn according to actual dimensions. Certain scales and basins: Related rulers? It is more exaggerated to provide a clearer description; those skilled in the art understand the present invention. At the same time, the preferred embodiment is not intended to limit the scope of patent application of the present invention / = = 2
脫離本發明所揭示之精神下所完成之等效改變飾, 應包含在下述之申請專利範圍内。 / > 1 實施例 示意圖與第4圖 具有一下層金屬 請同時參照第3A圖到3D圖之製程剖面 之流程圖。如第3A圖所示,首先,提供一Equivalent alterations made without departing from the spirit disclosed by the present invention should be included in the scope of patent application described below. / > 1 Example Schematic diagram and Figure 4 with lower layer of metal Please refer to the flow chart of the process cross section of Figures 3A to 3D at the same time. As shown in FIG. 3A, first, a
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層110之半導體基底100 (S300),下層金屬層110之材質 例如為鋁、銅或前述之組合,在此為鋁銅合金,半導體、 底1 0 0例如為一矽基底。一金屬層間介電層丨2 〇形成於下^ 金屬層1 1 0上,金屬層間介電層1 2 0之較佳結構為一由高二 度電漿法沉積之氟矽玻璃層(HDP-FSG)、增強式電浆法1@ 積之ll矽玻璃層(PE-FSG)以及增強式電漿法沉積之無換 氧化矽層(PE-USG)依序所構成之堆疊層,其他材質亦可: 如四乙氧基矽烷(TEOS )等。 '為 於金屬層間介電層1 2 0中形成一以電性連接上、下 案化金屬層110、Γ30之栓塞140,材質例如為鋁、銅、回 鎢、鈦氮或前述之組合,在此為鎢。接著,沉積一上層6 屬層1 3 0於金屬層間介電層1 2 〇上,材質例如為鋁或鋁合 金,在此為鋁合金,並形成一圖案化光阻層15〇於上層°金 屬層1 3 0上。將含上述結構之基底丨〇 〇置於蝕刻機台例如 RIE機台中,進行一蝕刻步驟,其以圖案化光阻層15〇為二 罩幕刻上層金屬層1 3 0,而得到一圖案化之上層金 層 130。The semiconductor substrate 100 of the layer 110 (S300), and the material of the lower metal layer 110 is, for example, aluminum, copper, or a combination of the foregoing. Here, it is an aluminum-copper alloy. The semiconductor and the substrate 100 are, for example, a silicon substrate. A metal interlayer dielectric layer is formed on the lower metal layer 1 10. The preferred structure of the metal interlayer dielectric layer 12 is a fluorosilicone glass layer (HDP-FSG) deposited by a high-degree plasma method. ) 、 Enhanced plasma method 1 @ Jizhill silica glass layer (PE-FSG) and stacked plasma layer deposited by enhanced plasma method without exchange oxide layer (PE-USG), other materials can also be : Such as tetraethoxysilane (TEOS). 'To form a plug 140 electrically connecting the upper and lower metallized layers 110 and Γ30 in the metal interlayer dielectric layer 120. The material is, for example, aluminum, copper, tungsten back, titanium nitrogen, or a combination of the foregoing. This is tungsten. Next, an upper layer 6 of the metal layer 130 is deposited on the interlayer dielectric layer 120. The material is, for example, aluminum or an aluminum alloy, here is an aluminum alloy, and a patterned photoresist layer 15 is formed on the upper layer of the metal. Layer 1 3 0. The substrate containing the above structure is placed in an etching machine, such as a RIE machine, and an etching step is performed. The patterned photoresist layer 150 is used as the second mask to etch the upper metal layer 130 to obtain a pattern.上层 金 层 130。 The upper layer of gold 130.
接下來,先通入一水蒸氣(DI water),約5〜6〇秒 使電漿蝕刻系統達到一穩定的狀態,在此為3 〇秒;製程 力約為卜3托耳,在此為2托耳;射頻功率為零,製程溫 約為20 0〜3 0 0 °C,在此為25(TC ;水蒸氣流量約5 50〜 方公分/分鐘,在此為6 5 0立方公分/分鐘。 然後,麥見第3B圖,進行一第—電漿乾蝕刻製程丨9( (S310 )以去除圖案化光阻層15〇,蝕刻來源為水蒸氣、Next, first pass in DI water for about 5 ~ 60 seconds to make the plasma etching system reach a stable state, which is 30 seconds; the process force is about 3 Torr, here is 2 Torr; RF power is zero, process temperature is about 20 0 ~ 300 ° C, here is 25 (TC; water vapor flow is about 5 50 ~ cm3 / min, here is 6 50 cm3 / Then, seeing Figure 3B, Mai performed a first-plasma dry etching process 9 ((S310)) to remove the patterned photoresist layer 150. The etching source was water vapor,
1223351 五、發明說明(5) 氧氣、高純度氮氣或前述之組合,在此為氮氣:水蒸氣: 氧氣之組合’比例為1 : 1 · 4 : 1 6 ;在此流量約為2 〇 〇立 方公分/分鐘:3 0 0立方公分/分鐘:3500立方公分/分鐘, 比例分別約1 : 1 · 5 : 1 7 ;時間約為1 5秒;製程壓力約1〜3 托耳’在此為2托耳;射頻功率約1 〇 〇 〇瓦〜2 〇 〇 〇瓦,在此為 1 40 0瓦;製程溫度約2〇〇。〇3〇〇。(:,在此為250 °C。 2〇〇(^313Λ圖Λ示’接著再進行一第二電漿乾1虫刻製程 200 (S310)以去除附著在本 1 8 0,蝕刻來源為水蒸氣,日士 v肢基底1 0 0上之聚合殘留物 製程壓力约l·〜3·托耳,在此=間約5〜3 0秒,在此為2 0秒; 〜20 0 0瓦,在此為丨40 0瓦· 托耳;射頻功率約1 0 0 0瓦 此為25(TC ;水蒸氣流量約程溫度約為2〇〇。〇3〇〇。〇,在 分/分鐘,在此為6 50立方八5八0立方公分/分鐘〜7 50立方公 及第二電漿蝕刻製程,在此刀/分鐘。接著反覆數次第一 刻製程S3 2 0。 接下來,如第3 D圖所示, 電程序S3 30,藉由在不施加 為反覆2次第一及第二電漿蝕 對半導體基底1 0 0進行一放 通入一水蒸氣21〇以釋放因谁射頻功率(RF P0WER = 〇)下 在半導體基底1〇〇上之電朽進行上述電聚蝕刻製程而殘留 其中,水蒸氣之流量約電荷160、負電荷17〇), 分鐘,在此為為65 0立方公;方公分/分鐘〜750立方公分/ 值,不隨通入時間而改t =分鐘;製程壓力為一固定 〜3 0 0 °c,在此為為2 7 0 °c1223351 V. Description of the invention (5) Oxygen, high-purity nitrogen, or a combination thereof, which is a combination of nitrogen: water vapor: oxygen; the ratio is 1: 1; 4: 16; the flow rate here is about 200 cubic meters Cm / min: 300 cm3 / min: 3500 cm3 / min, the ratios are about 1: 1 · 5: 17; the time is about 15 seconds; the process pressure is about 1 ~ 3 Torr 'here is 2 Torr; RF power is about 1,000 watts to 2,000 watts, here is 1400 watts; process temperature is about 2,000. 〇3〇〇. (:, Here is 250 ° C. 〇〇 (^ 313Λ 图 Λshows' Next, a second plasma drying 1 insect engraving process 200 (S310) to remove the adhesion to the 180, etching source is water Vapor, the process pressure of the polymer residue on the limb base 100 of Japan is about l · ~ 3 · Tor, here is about 5 ~ 30 seconds, here is 20 seconds; ~ 200,000 watts, Here it is 400 watts · Torr; RF power is about 1000 watts and this is 25 (TC; water vapor flow range temperature is about 20000. 0300. 00, in minutes / minutes, at This is 6 50 cubic meters, 850 cubic meters per minute to 7,50 cubic meters and the second plasma etching process, here knife / minute. Then repeat the first engraving process S3 2 0 several times. Next, as shown in Figure 3 D As shown in the figure, the electrical program S3 30 is performed by repeatedly applying the first and second plasma etching to the semiconductor substrate 100 without repeatedly applying water vapor 21 to release the RF power (RF P0WER). = 〇) on the semiconductor substrate 100 ℃ under the electro-etching process described above and left in it, the flow of water vapor is about 160 charges, 17), in minutes, here is 65 0 cubic meters; square Cm / min ~ 750 mcm / value, does not change with the access time t = minutes; the process pressure is a fixed ~ 3 0 0 ° c, here is 2 7 0 ° c
程温度亦為一固定值,不ρ 'Έ 1〜3托耳,在此為2托耳;製 〇 Π Π 〇r 如i 4 见通入時間而改變,約2 0 0 〇C &外’可視製程需要額外再通The process temperature is also a fixed value, not ρ 'Έ 1 ~ 3 Torr, here it is 2 Torr; the system ΠΠ Π 〇r such as i 4 varies depending on the access time, about 2 0 〇C & outside 'Visual processes require additional reopening
0503-9547TWf(Nl) ; TSMC2002-1103;david.ptd 第100503-9547TWf (Nl); TSMC2002-1103; david.ptd 10th
頁 1223351 五、發明說明(6) 入一高純度氮氣(N 2 - S ) S 3 4 0約5秒鐘,流量約2 0 0立方公 分/分鐘,射頻功率為零,製程溫度約2 5 0 t:,並配合進行 一抽氣步驟S 3 4 0以進一步將上述製程中所產生的殘餘物質 及懸浮微粒清除乾淨。 為了證明本發明之方法確實有效,特別設計一個具有 80萬個插塞(via、簡稱為Rc〇_8 0 0k )的電路圖案,若其 中有任何一個插塞在經過弱鹼液(在此係使用EKC (廠商 名)溶液)浸泡後,因電荷未被完全釋放而與弱鹼液發生 伽凡尼反應、產生侵蝕現象而發生斷路時,則rc〇_ 8 0 0 k的 阻值會1菱高(> 1 5歐姆)。 第5A(a)與5 A(b)圖中顯示,採用乾蝕刻製程以去除光 阻層及聚合殘留物,再經過EKC溶液處理後,所測得之 Rc0_80 Ok在1 5歐姆時(橫坐標)之百分比為仍然有95 %到 97 %,亦即仍有約3 %到5 %的Rc值大於15歐姆。第5B(a) 與5 B ( b )圖則是在採用本發明之用於乾蝕刻金屬層後之晶 圓放電方法後’同樣再經過EKC溶液處理,所測得之 Rc0_80 Ok在15歐姆時之百分比為1〇〇%,亦即go萬個插塞 中沒有一個插塞的阻值超過1 5歐姆。由此可知,本發明確 實可將晶圓完全放電,避免了在後續EKC溶液處理中發生 伽凡尼反應而引起阻值上升的問題。 第6圖係習知乾蝕刻製程與本發明之RC〇_80 0K失敗率 比較圖。由圖中可看出,在採用習知製程時,其rc〇_8 00K 失敗率之曲線高低起伏不定,非常不穩定,而在採用本發 明(6 0 1 )後,R c 0 一 8 0 0 K失敗率整個降到〇 %,其中,橫坐標Page 1223351 V. Description of the invention (6) Inject a high-purity nitrogen (N 2-S) S 3 4 0 for about 5 seconds, the flow rate is about 200 cm 3 / min, the RF power is zero, and the process temperature is about 2 5 0 t: and cooperate with an extraction step S 340 to further remove the residual substances and suspended particles generated in the above process. In order to prove that the method of the present invention is indeed effective, a circuit pattern with 800,000 plugs (via, abbreviated as Rc0_8 0 0k) is specially designed. If any of the plugs pass through a weak alkaline solution (in this system When EKC (manufacturer's name) solution is used for immersion, a galvanic reaction with a weak alkaline solution occurs due to incomplete charge release, and an open circuit occurs due to erosion, the resistance value of rc0_8 0 0 k will be 1 diamond. High (> 1 5 ohm). Figures 5A (a) and 5 A (b) show that the Rc0_80 Ok measured at 15 ohms (abscissa) after the dry etching process is used to remove the photoresist layer and the polymerization residue, and then treated with the EKC solution. ) The percentage is still 95% to 97%, that is, about 3% to 5% still has an Rc value greater than 15 ohms. Figures 5B (a) and 5B (b) are after the wafer discharge method of the present invention for dry-etching a metal layer is used, and then treated with an EKC solution. The Rc0_80 Ok measured at 15 ohms The percentage is 100%, that is, the resistance value of none of the 10,000 plugs exceeds 15 ohms. It can be seen from the above that the present invention can completely discharge the wafer, and avoids the problem of resistance increase caused by the Galvanic reaction in the subsequent processing of the EKC solution. FIG. 6 is a comparison chart of the conventional dry etching process and the RC0_80 0K failure rate of the present invention. It can be seen from the figure that when the conventional process is adopted, the curve of the rc0_00 00K failure rate fluctuates up and down and is very unstable. However, after using the present invention (6 0 1), R c 0-8 0 The 0 K failure rate drops to 0%, where the abscissa
0503-9547TWf(Nl) * TSMC2002-1103;david.ptd 第11頁 1223351 五、發明說明(7) (W239 )所對應 之 R c 0 __ 8 Ο Ο K 失貝1 第7A〜7C圖{ 偏差(standard 中,習知之標準 中,習知之標準 中,習知之標準 本發明在製程可 雖然本發明 以限定本發明, 之精神及範圍内 範圍當視後附之 到的點係改採習知製裎( 602 ),故其測得 率又升高。 ;為習知標準製程與本發明之良率及標準 dev^Uon, STDEV)比較圖。在第以圖 偏產值為2. 09,本發明為1.61 ;第7B圖 ==:.74 ’本發明為1〇2 ;在第 ί扁差值為171,士&。 瓜你 本么明為1 · 0 3,由此證明 罪度上確實且η ,、有良好的提升能力。 已以一較伟每& ,, ία只例揭露如上,然其並非用 (壬何热知此技術 m ,當可做更動盘门奋不脫離本發明 "青專利範圍所3飾此本發明之保護 视固所界定者為準。 1223351 圖式簡單說明 第1 A〜1 B圖係為顯示習知金屬蝕刻製程之剖面示意 圖 第2圖係為顯示習知金屬導線結構之電子顯微鏡圖; 第3 A〜3D圖係為顯示本發明實施例製造流程之剖面示 意圖 第4圖係為顯示本發明實施例之流程示意圖; 第5A〜5B圖係為顯示用以驗證本發明實施例之 RcO —8 0 0K測試之電阻對百分比之關係圖; 第6圖係為顯示本發明與習知製程之RcO_80 0K測試失 敗率關係圖;及 第7 A〜7C圖係為顯示習知標準製程與本發明之良率及 標準偏差(standard deviation, STDEV)比較圖。 符號說明 1 5電漿蝕刻法; 3 0光阻圖案; 4 0正電荷; 6 0聚合殘留物; 100半導體基底; 120金屬層間介電層; 140插塞; 1 6 0正電荷; 1 8 0聚合殘留物; 2 0 0第二電漿蝕刻製程 10基底; 2 0金屬層; 3 5電漿轟擊; 5 0負電荷; 6 5被侵钱之鎮插塞; 1 1 0下圖案化金屬層; 1 3 0上圖案化金屬層; 1 5 0圖案化光阻層; 1 7 0負電荷; 1 9 0第一電漿蝕刻製程;0503-9547TWf (Nl) * TSMC2002-1103; david.ptd Page 11 1223351 V. Description of the invention (7) (W239) R c 0 __ 8 Ο Ο K Losbei 1 Figures 7A ~ 7C {Deviation ( In the standard, the standard of knowledge, the standard of knowledge, the standard of the present invention can be used in the manufacturing process. Although the present invention defines the present invention, the spirit and scope of the scope of the present invention should be changed to the point of reference. (602), so its measurement rate is increased again. It is a comparison chart of the conventional standard process and the yield rate and standard dev ^ Uon (STDEV) of the present invention. In the figure, the partial production value is 2.09, and the present invention is 1.61; Figure 7B == :. 74 ′ The invention is 102; in the first flat difference value is 171, Shi &. The melon is 1.03, which proves that the degree of sin is true and η, and that it has a good ability to improve. It has been disclosed as above with a better example, but it is not used. (However, he knows this technology m, and he can make changes to the door without departing from the scope of the invention.) The protection of the invention depends on the definition of the solid. 1223351 Brief description of the drawings 1A ~ 1B are schematic cross-sectional diagrams showing the conventional metal etching process; Figure 2 is an electron microscope diagram showing the structure of the conventional metal wire; Figures 3A to 3D are schematic cross-sectional diagrams showing the manufacturing process of the embodiment of the present invention. Figure 4 is a schematic diagram of the process flow of the embodiment of the present invention; Figures 5A to 5B are RcO showing the embodiment of the present invention to verify- 8 0K test resistance vs. percentage diagram; Figure 6 is a graph showing the relationship between the RcO_80 0K test failure rate of the present invention and the conventional process; and Figures 7 A to 7C are the standard process and the present invention of the conventional process Comparison of yield and standard deviation (STDEV). Symbol Description 15 Plasma Etching; 30 Photoresist Pattern; 40 Positive Charge; 60 Polymer Residue; 100 Semiconductor Substrate; 120 Interlayer Dielectric Layer; 140 plugs; 1 60 positive charge; 1 8 polymer residue; 2 0 second plasma etching process; 10 substrates; 2 metal layers; 3 5 plasma bombardment; 5 0 negative charges; 6 5 plugs being invaded by money ; Patterned metal layer below 110; patterned metal layer above 130; patterned photoresist layer of 150; negative charge of 170; first plasma etching process of 190;
0503-9547TWf(Nl) ; TSMC2002-1103;david.ptd 第13頁 1223351 圖式簡單說明 210不施加射頻功率(RF POWER = 0)下通入一水蒸 氣 6 0 1通入水蒸氣烘烤; 6 0 2無水蒸氣烘烤; S300提供一具有下圖案化金屬層之基底; S 3 1 0以第一電漿乾蝕刻製程去除圖案化光阻層,並以 第二電漿乾蝕刻製程去除附著在圖案化金屬層及基底上之 聚合殘留物; S3 2 0反覆第一及第二電漿乾蝕刻製程; S 3 3 0通入一射頻功率為零之水蒸氣以進行放電程序; S 3 4 0通入氮氣及進行板氣步驟。0503-9547TWf (Nl); TSMC2002-1103; david.ptd Page 13 1223351 Brief description of the diagram 210 Water vapor is passed in without RF power (RF POWER = 0) 6 0 1 Water vapor is passed in to bake; 6 0 2 steamless baking; S300 provides a substrate with a lower patterned metal layer; S 3 10 removes the patterned photoresist layer with a first plasma dry etching process, and removes the adhesion to the pattern with a second plasma dry etching process Polymerized residue on the metal layer and the substrate; S3 2 0 repeats the first and second plasma dry etching processes; S 3 3 0 passes a water vapor with zero RF power to perform the discharge process; S 3 4 0 Introduce nitrogen and carry out the plate gas step.
0503-9547TWf(Nl) ; TSMC2002-1103;david.ptd 第14頁0503-9547TWf (Nl); TSMC2002-1103; david.ptd page 14
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