TWI223159B - Data transmission method using I2C bus as interface and electronic system thereof - Google Patents

Data transmission method using I2C bus as interface and electronic system thereof Download PDF

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Publication number
TWI223159B
TWI223159B TW92105177A TW92105177A TWI223159B TW I223159 B TWI223159 B TW I223159B TW 92105177 A TW92105177 A TW 92105177A TW 92105177 A TW92105177 A TW 92105177A TW I223159 B TWI223159 B TW I223159B
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integrated circuit
bus
coupled
data
slave
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TW92105177A
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TW200417871A (en
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Rung-Jeng Li
Wen-De Chen
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Accton Technology Corp
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Abstract

An electronic system using the Inter-integrated circuit (I2C) bus as interface comprises an I2C bus; multiple slave devices coupled to the I2C bus and providing an identical I2C address; a master control device coupled to the I2C bus for receiving and transmitting information; and a selector coupled to the I2C bus and the master control device, and providing multiple output terminals to couple with the multiple slave devices and selecting one of the multiple slave devices in cooperation with the master control device for data transmission.

Description

1223159 五、發明說明(2)1223159 V. Description of the invention (2)

進行資料傳輸的電子系統,當主控元件1 1 〇欲和從屬元件 120藉由I2C介面150進行資料傳輸時,主控元件11〇會產生 一個啟始狀態,將I2C啟始信號(start)送到資料信號線 SDA上所有的從屬元件120、130及140。為了回應啟始信 號’從屬元件1 2 0、1 3 0及1 4 0會聽從本身各別的位址。於 啟始狀態後之下一個時脈週期開始,主控元件丨丨〇傳輸一 個位址信號(含有支持I2c介面協定之從屬元件12〇之唯一 位址)。於是沒有被上述位址信號所指名到的從屬元件j 3 〇 及140都/會閒滯,同時被指名到的從屬元件12〇發出一確認 位元信號於資料信號線SDA上,告知主控元件11 〇可以傳輸 為料#號了 ’並開始等待資料。 從屬元件1 2 0於每次接收完1位元組之資料信號後,會 於資料信號線SDA上輸出一個確認信號(ackn〇wUdge),^ 知主控元件1 1 0資料已經收到。一旦pc資料訊息已經完 成二主控兀件11 0產生一停止狀態並傳送停止信號沿著資 料k號線SDA至所有的從屬元件12〇、13〇及14〇。當所 積體電路連線匯流排的從屬元件120 Ί 3〇及140接收 ,争f信號後,立即開始監視資料匯流排是否有下。個啟 啟始狀態’就是當T#丸古、、住 由高準位變為低準位nm:準位時’sda信號線 成低準位;而停止狀離_號線經一小段時間後會變 SCL ^ ^ i ^ 〜、,就是當SDA信號線為低準位時, L L· t 5虎線由低準位變士 + 間亦變成高準位。成同準位 DA信號線經—小段時The electronic system for data transmission. When the master control element 1 1 0 and the slave element 120 want to transmit data through the I2C interface 150, the master control element 11 will generate a start state and send the I2C start signal (start). To all the slave components 120, 130 and 140 on the data signal line SDA. In response to the initial signal, the slave elements 120, 130, and 140 will listen to their respective addresses. After the start of the next clock cycle after the start state, the master control element transmits an address signal (containing the unique address of the slave element 12 which supports the I2c interface protocol). Therefore, the slave components j 3 0 and 140 that are not named by the above address signal are idle. At the same time, the designated slave component 120 sends a confirmation bit signal on the data signal line SDA to inform the master control component. 11 〇 Can be transmitted as material ## 'and start waiting for data. The slave component 120 will output a confirmation signal (ackn0wUdge) on the data signal line SDA after receiving a data signal of 1 byte each time, and know that the data of the master component 1 1 0 has been received. Once the pc data message has been completed, the two master control units 110 generate a stop state and send a stop signal along the data k line SDA to all slave components 120, 130, and 140. When the slave components 120 的 30 and 140 of the integrated circuit connection bus receive the signal, they immediately start to monitor whether the data bus is down. The beginning state is when the T # Maru, and the residence change from a high level to a low level nm: when the level, the sda signal line becomes a low level; after stopping for a short time from the _ line, It will change SCL ^ ^ i ^ ~, that is, when the SDA signal line is at a low level, the LL · t 5 tiger line changes from a low level to a high level. At the same level DA signal line warp—for a short period

1223159 五、發明說明(3) 然而’若所有的從屬元件12〇、13〇及14〇於出廠時已 具相同I2C位址,主控元件110將同時啟動所有從屬元件 120、130及140進行資料傳輸,因此,將造成主控元件ιι〇 無法與積體電路連線匯流排15〇上的從屬元件12〇、13〇及 140進行資料傳輸。 然而’若所有的從屬元件於出廠時已具相同p C位址 時,主控兀件一次將會啟動一個以上的從屬元件進行資料 傳輸,因此,將造成主控元件無法與積體電路連線匯流排 上的從屬元件進行資料傳輸。或者是說,必須要使用多組 的匯k排來为離具有相同12 c位址之從屬元件,但這樣又 會造成成本的增加。 ’ 【發明内容】 有鑑於此,本發明之首要目的,在於提供一種使用積 體電路連線匯流排介面來資料傳輸的電子系統,其中主控 元件可以與具有相同I2 C位址之複數從屬元件進行資料傳 輸0 此外,本發明之另一目的係在於,提供一種主控裝置 與複數具有相同I2 C位址之電子裝置的資料傳輸方法。1223159 V. Description of the invention (3) However, 'If all the slave components 120, 13 and 14 have the same I2C address when they leave the factory, the master component 110 will start all the slave components 120, 130, and 140 for data at the same time. Transmission, therefore, will cause the master control component ιι0 to be unable to connect to the integrated circuit 1550 on the slave components 120, 13 and 140 for data transmission. However, 'If all the slave components have the same PC address when they are delivered from the factory, the master control element will start more than one slave component for data transmission at a time, so the master control element cannot be connected to the integrated circuit. Slave components on the bus transfer data. In other words, it is necessary to use multiple sets of sinks k for slave components with the same 12 c address, but this will increase the cost. '[Summary of the Invention] In view of this, the primary object of the present invention is to provide an electronic system for data transmission using an integrated circuit connection bus interface, in which the master control element can be a plurality of slave elements with the same I2C address Data transmission 0 In addition, another object of the present invention is to provide a data transmission method for a master control device and a plurality of electronic devices with the same I 2 C address.

本發明提供一種使用積體電路連線匯流排為介面之電 子系統’包括一積體電路連線匯流排;複數從屬裝置,耦 接至積體電路連線匯流排,並且複數從屬裝置具有相同之 一 I2 C位址,一主控裝置,耦接至積體電路連線匯流排, 用以接收及發出資料;以及一選擇器,耦接積體電路連線 匯流排及主控裝置’並具有複數輸出端分別耦接至複數從The present invention provides an electronic system using an integrated circuit connection bus as an interface, including an integrated circuit connection bus; a plurality of slave devices coupled to the integrated circuit connection bus, and the plurality of slave devices having the same An I2C address, a master control device, coupled to the integrated circuit connection bus for receiving and transmitting data; and a selector, coupled to the integrated circuit connection bus and the master control device 'and having The plural output terminals are respectively coupled to the plural slaves.

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主控裝置欲進行資料傳輸時 至選擇器之第二端,以及一 排之上。最後,選擇器係依 複數從屬裝置之一者與主控 【實施方式】 ’主控裝置會輸出一選擇信號 啟始信號至積體電路連線匯流 據選擇信號及啟始信號,選擇 裝置進行資料傳輸。 請參考第2圖所示,本發明係提供一個藉由主控裝置 差由積體電路連線匯流排介面與具有相同p c位址之複數 從屬裝置進行資料傳輸的電子系統。When the master device wants to transmit data, it goes to the second end of the selector and above the row. Finally, the selector is based on one of the plurality of slave devices and the master. [Embodiment] 'The master control device will output a selection signal start signal to the integrated circuit connection bus according to the selection signal and start signal, and select the device for data. transmission. Please refer to FIG. 2, the present invention provides an electronic system for transmitting data through a master control device, a bus interface connected to an integrated circuit and a plurality of slave devices having the same pc address.

於電子系統中,複數從屬裝置20 —丨〜2〇一4,係耦接至 積體電路連線匯流排10,並且複數從屬裝置w — m4皆 具有相同之第一 I2C位址,例如1111〇〇〇h。另外,積體電 路連線匯流排係由一資料信號線SDA及一時脈信號線SCL所 組成。I2C主控裝置30係耦接至積體電路連線匯流排1〇, 用以接收及發出資料。選擇器4〇,係耦接到積體電路連線 匯流排10及I2C主控裝置30,具有複數輸出端SCL1〜SCU分 別耦接至複數從屬裝置20-— 4,以選出複數從屬裝置 20-1〜2 0-4之任一者,配合pc主控裝置30以進行資料傳 輸0 其中,當I2C主控裝置30進行資料傳輸時,PC主控裝 置3 0會輸出一啟始信號於積體電路連線匯流排丨〇之上及一 _ 選擇信號SS至選擇器40。因此,選擇器4〇會依據選擇信 號’於複數從屬裝置20 - 1〜2〇 -4中選出任一者,來接收啟 始信號並與I2C主控裝置3 〇進行資料傳輸。 請參考第2圖及第3圖,選擇器40係由一解多工器4〇1In the electronic system, a plurality of slave devices 20 — 丨 ~ 20-4 are coupled to the integrated circuit connection bus 10, and the plurality of slave devices w — m4 all have the same first I2C address, such as 1111. 〇〇h. In addition, the integrated circuit connection bus is composed of a data signal line SDA and a clock signal line SCL. The I2C master control device 30 is coupled to the integrated circuit connection bus 10 for receiving and sending data. The selector 40 is coupled to the integrated circuit connection bus 10 and the I2C master control device 30, and has a plurality of output terminals SCL1 to SCU respectively coupled to the plurality of slave devices 20-4, so as to select the plurality of slave devices 20- Any of 1 ~ 2 0-4, cooperate with the PC main control device 30 for data transmission 0 Among them, when the I2C main control device 30 performs data transmission, the PC main control device 30 will output a start signal to the product Above the circuit connection bus 丨 〇 and a _ select signal SS to the selector 40. Therefore, the selector 40 selects any one of the plurality of slave devices 20-1 to 2-4 according to the selection signal ′, receives the start signal and performs data transmission with the I2C master device 3 0. Please refer to Fig. 2 and Fig. 3. The selector 40 is a demultiplexer 401.

0739-9121twf(nl);91P032;DENNIS.ptd 第8頁 1223159 五、發明說明(7) =者會接收到κ主控裝置3()輸出 控裝置3〇進行資二 也就疋說,複數或閘之輸出端的準位中,σ 狀態’因而只有接收;;啟:狀ϊ 之攸屬裝置會啟動。被啟動之從屬裝置會聽 二4置30曰傳輸一個位址信號(1丨丨1〇〇〇 :動=裝置會發出一確認位元信號於資料信號線疋二 ;um控裝置3〇 1已經準備好接收資料了,並 開口專待貝料。接著PC主控裝置30便開始傳輸資料信 號。 ° 資料提! 一種使用積體電路連線匯流排為介面之 ,專輸方法,適用於一 PC主控裝置與複數具有相同丨2C 位址之從屬裝置,其中I2C主控裝置30,具有一第一端、 ς第da二u端《分^耦接至一積體電路連線匯流排10之資料信號線 S 及時脈信號線SCL,且每個從屬裝置20-1〜20-4均具 以及一第二端,④中每個第一端係耦接至匯流 排10之資料信號線SDA。 本發明之資料傳輸方法,包括首&,提供一選擇号 二二二有複數輸出端SCL1 ~SCL4分別輕接至複數從屬裝置 號線SCL· 4之第一端,一輸入端耦接至匯流排1 0之時脈信 &私t者,當主控裝置3〇欲進行資料傳輸時,主控裝置30 會輸出一選擇信號%至選擇器4〇之控制端(ai〇、aii),以 0739-9121twf(nl);9lP〇32;DENNIS.ptd 第10頁 1223159 五、發明說明(8) 及一啟始#號至積體電路連線匯流排1 〇之上。 最後,選擇器40係根據上述選擇信號ss及啟始信號, 於複數從屬裝置20-1〜20-4中選出之一者,與主控裝置 進行資料傳輸。由於選擇器4〇會將複數從屬裝置 20-1〜20-4中,未被選擇到的三個從屬裝置之第二端上的 準位保持在高準位。故只有被選到的從屬裝置之第二端上 的準位,可以隨著積體電路連線匯流排之時脈信號線變 化,因此’當I2c主控單元30先拉低資料信號線SDA的準 位’接著再拉低時脈信號線sa的準位,以作為輸出 體電路連線匯流排10上之啟始信號時,複數從屬裝置 20-1〜20-4只有一者會接收到一啟始信 置30進行資料傳輸。 〃王控聚 =,在本發明所提供之電子系統中,pc主控元件 址:體電路連線匯流排介面’與具有相同K位 :之:數攸屬元件進行資料傳輸。且不用如習知技術一 同I2c位in # J # 線匯流排來分離複數具有相 位址之仗屬裝置,因此系統之成本亦可以降低。 限制ίΠ f::較佳實施例揭露如上,然其並非用以 制士七月,任何熟習此項技藝者,在不脫離本發 '當ΐ IΞ:申ΐ::口動與潤飾,因此本發明之保護範; 後附之申印專利乾圍所界定者為準。0739-9121twf (nl); 91P032; DENNIS.ptd Page 8 1223159 V. Description of the invention (7) = The person will receive the κ master control device 3 () and the output control device 30 for the second time. In the level of the output terminal of the gate, the σ state 'has only received it; Kai: the state-affected devices will start. The activated slave device will listen to the transmission of an address signal (1 丨 丨 10000: motion = the device will send a confirmation bit signal to the data signal line 22); the um control device 3001 has been Ready to receive the data, and open up to wait for the material. Then the PC main control device 30 starts to transmit data signals. ° Data extraction! A method of using integrated circuit to connect the bus to the interface, a dedicated input method, suitable for a PC The master device and the slave device having the same 2C address, among which the I2C master device 30 has a first terminal, a da terminal and a second terminal, which are separately coupled to a integrated circuit connection bus 10 The data signal line S and the clock signal line SCL, and each of the slave devices 20-1 to 20-4 have a second end, and each of the first ends of ④ is coupled to the data signal line SDA of the bus 10. The data transmission method of the present invention includes a first & providing a selection number two two two having a plurality of output terminals SCL1 to SCL4 which are respectively lightly connected to the first terminal of the plurality of slave device number lines SCL · 4, and an input terminal is coupled to the bus The clock 10 & private person who ranked 10, when the master device 30 wants to perform data During input, the main control device 30 will output a selection signal% to the control terminals (ai0, aii) of the selector 40, with 0739-9121twf (nl); 9lP〇32; DENNIS.ptd Page 10 1223159 V. Invention Explanation (8) and a start ## to the integrated circuit connection bus 1 0. Finally, the selector 40 is based on the selection signal ss and the start signal in the plural slave devices 20-1 ~ 20-4 One of the selected ones transmits data with the master control device. As the selector 40 will place the level of the second slave end of the three slave devices among the plurality of slave devices 20-1 to 20-4 on the second end. Keep the high level. Therefore, only the level on the second end of the selected slave device can change with the clock signal line of the integrated circuit connection bus, so 'when the I2c master control unit 30 pulls first The level of the low data signal line SDA 'is then pulled down to the level of the clock signal line sa as the start signal on the output body circuit connection bus 10, the plurality of slave devices 20-1 to 20-4 only have One will receive an initial trust 30 for data transmission. 〃 王 控 聚 =, in the electronic system provided by the present invention In the PC, the main control component address: the body circuit connection bus interface 'has the same K-bits: of: several components are used for data transmission. It is not necessary to separate the I2c bit in # J # line bus together with the conventional technology The plural number has a phase address, which is a device, so the cost of the system can also be reduced. Limitations f :: The preferred embodiment is disclosed above, but it is not used to make a master in July. Anyone who is familiar with this skill will not depart from this. '' 当 ΐ IΞ: 申 ΐ :: Mouth movement and retouching, therefore the scope of protection of the present invention; as defined in the enclosed application for patent protection.

1223159 圖式簡單說明 第1圖,用以說明使用積體電路連線匯流排介面來進 行資料傳輸的電子系統(習知技術)。 第2圖係為本發明之電子系統之示意圖。 第3圖係為本發明中選擇器之示意圖。 第4圖係為本發明中選擇器之另一示意圖。 【符號說明】 1 0 :積體電路連線匯流排; 20-1〜20-4 ·· I2C從屬裝置; 30 : I2C主控裝置; 40 :選擇器; 401 :解多工器; OR卜0R4 :或閘; 41 1 : TTL 邏輯閘 74 1 39 ; 41 2 : TTL 邏輯閘 743 2。1223159 Brief Description of the Drawings Figure 1 is used to illustrate the electronic system (conventional technology) that uses the integrated circuit to connect the bus interface for data transmission. FIG. 2 is a schematic diagram of the electronic system of the present invention. Figure 3 is a schematic diagram of a selector in the present invention. FIG. 4 is another schematic diagram of the selector in the present invention. [Symbol description] 1 0: integrated circuit connection bus; 20-1 ~ 20-4 ·· I2C slave device; 30: I2C master device; 40: selector; 401: demultiplexer; OR BU 0R4 : OR gate; 41 1: TTL logic gate 74 1 39; 41 2: TTL logic gate 743 2.

0739-9121twf(nl);91P032;DENNIS.ptd 第12頁0739-9121twf (nl); 91P032; DENNIS.ptd Page 12

Claims (1)

1223159 六 申δ月專利範圍 1 · 一種使用積體電路連線匯流 藉由一主控裝置與具有相同I2C位址二;ί面之電子系統, 資料傳輸,包括·· 之设數從屬裝置進行 一積體電路連線匯流排; 複數從屬装置,耦接至上述積 述複數從屬裝置均具有相同位址路連線匯流排,上 主控裝置,搞接至上述積體啻 接收及發出資料;以及 、電路連線匯流排,用以 一選擇器,耦接至上述積體電 + 控裝置’具有複數輸出端分 5、她Ί士述主 用以從上述複數從屬裝置中選出任ί”慮置, 裝置進行資料傳輸。 者,來配合上述主控 2 ·如申請專利範圍第1 流排為介面之電子系統,Α、 使-用積體電路連線匯 主控穿置於出 二 ^ 田人進行資料傳輪時,上述 上,以及-選擇信號至;;體2連線匯流排之 述選擇信號,於上述複數從屬15'係依據上 收上述啟始们虎,並;-者,來接 〇 ^ ^ ^ 、上述主控I置進行資料傳輸。 流排A入@ Γ f利範圍第2項所述之使用積體電路連線匯 有一時啼括Γ 其中上積體電路連線匯流排具 可脈k號、、泉及一資料信號線。 、六:t如申明專利範圍第3項所述之使用積體電路連線匯 ▲排f介,之,子系統,其中上述選擇器包括: 解多工為’具有複數輸入端耦接至上述選擇信號, 第13頁 0739-912ltwf(nl);91P032;DENNIS.i 1223159 ;以及 ,各具有一第一輸入端耦接至上述解多工器 之一者,一第二輸入端耦接至上述積體電路 時脈信號線,以及一輸出端耦接至上述複數 一者。 專利範圍第4項所述之使用積體電路連線匯 電子系統,其中上述解多工器係藉由一TTL 〇 專利範圍第4項所述之使用積體電路連線匯 電子系統,其中上述複數或閘係藉由一TTL 六、申請專利範圍 及複數輸出端 複數或閘 之複數輸出端 連線匯流排之 從屬裝置中之 5. 如申請 流排為介面之 邏輯閘來實現 6. 如申請 流排為介面之 邏輯閘來實現。 主控裝 输,包 積體電 線; 數從屬 置均具 上述匯 主控裝 路連線 選擇器 第二端 7. —種使用積體電路連線匯流排為介面之電子系統 藉由一主控裝置與具有相同I2 C位址之複數從屬元件進行 資料傳 脈信號 複 從屬裝 柄接至 積體電 裝置之 線; 括: 路連線匯流排,具有一資料信號線以及一時 裝置,均具有相同之一 I2 C位址,上述每個 有一第一端以及一第二端,其中上述第一端 流排之貧料號線, 置,具有一第一端、第二端分別耦接至上述 匯流排之資料信號線以及時脈信號線; ,具有複數輸出端分別耦接至上述複數從屬 ,一輸入端耦接至上述匯流排之時脈信號1223159 Six months of patent application1. Scope of the use of integrated circuit connection. A master control device and the same I2C address two; electronic system, data transmission, including ... Integrated circuit connection bus; a plurality of slave devices coupled to the above-mentioned plurality of slave devices all have the same address path connection bus, go to the master control device, and connect to the above-mentioned integrated unit to receive and send data; and The circuit connection bus is used for a selector to be coupled to the above-mentioned integrated electric + control device. It has a plurality of output terminals. 5. She states that the master is used to select any of the above-mentioned slave devices. The device performs data transmission. In order to cooperate with the above-mentioned main control 2 · For the electronic system with the first streamline as the interface in the scope of the patent application, A, make use of integrated circuit connection and the main control is placed in the second place. When the data transfer is performed, the above and the -selection signal to; the selection signal of the connection bus of the body 2 is received on the basis of the above plural slave 15 ', and the- 〇 ^ ^ ^ The above-mentioned main control I is set for data transmission. Streamer A enters @ Γ f The profit range item 2 uses the integrated circuit connection sink for a while and includes Γ where the upper integrated circuit connection bus tool The pulse number k,, spring, and a data signal line can be pulsed. Six: t Use the integrated circuit connection sink as described in item 3 of the declared patent scope ▲ row f medium, and the subsystem, where the above selector includes: Demultiplexing is' having a complex input terminal coupled to the selection signal, page 13 0739-912ltwf (nl); 91P032; DENNIS.i 1223159; and each having a first input terminal coupled to the demultiplexer. For one, a second input terminal is coupled to the integrated circuit clock signal line, and an output terminal is coupled to the above plural one. The integrated circuit is used to connect sink electronics as described in item 4 of the patent scope. System, in which the above-mentioned demultiplexer is connected to an electronic system using integrated circuits as described in item 4 of the TTL 0 patent scope, wherein the above-mentioned plural or gate system is through a TTL VI. Patent scope and complex output The multiple output terminals or the multiple output terminals are connected to the bus 5. In the slave device, if it is applied for the logic gate of the interface to implement. 6. If it is applied for the logic gate of the interface to implement. Master control equipment, including the integrated wire; The second end of the installation connection selector 7. — An electronic system using integrated circuit connection bus as an interface. A master control device and a plurality of slave components with the same I2 C address are used for data transmission. The wire attached to the integrated electrical device; including: a road connection bus, which has a data signal line and a time device, all have the same I2C address, each of which has a first end and a second end Wherein, the lean material number line of the first end bus is provided with a first end and a second end respectively coupled to the data signal line and the clock signal line of the bus; and a plurality of output ends are respectively coupled. To the above plural slaves, an input terminal is coupled to the clock signal of the above bus 0739-9121twf(nl);91P032;DENNIS.ptd 第14頁 1223159 六、申請專利範圚 其中當上述主和壯罢A 置會輸出—選;:…人進行資料傳輸時,上述主控掌 先拉低上逑資料“ 2選擇器,並且上述主控裝置會 線的準位,而μ +表的準位,接著再拉低上述時脈作萨 述複數從屬^選擇㈣、依據上述選擇信號,選擇出^ 屬裝置之第者,並且拉低上述被選㈣之複數從 上述主控的準位,幻吏上述被選擇到之從屬… 8 衣置進行資料傳輸。 只 流排為範圍第7項所述之使用積體電路連線匯 一又电子糸統,其中上述選擇器包括·· 及複;輸=器以^有複數輸入端輕接上述選擇信號,以 之複數輪之有:Ϊ一輸入端耦接至上述解多工界 連線匯流排:日心::—第二輸入端耦接至上述積體電: 從Μ P W rb t脈^唬線,以及一輸出端耦接至上述# 伙屬衣置中之一者之第二端。 上述硬數 产排9為t巾請專利範圍第8項所述之使用積體電路連崎「 非為;丨面之電子系統,其中上'、泉匯 邏輯閘來實現。 的係猎由—Tu 浐排人如申請專利範圍第8項所述之使用積體電路連@ 邏輯閘來實現。 及閉係猎由—Tu 一鳊分別耦0739-9121twf (nl); 91P032; DENNIS.ptd Page 14 1223159 VI. Application for patents: When the above master and Zhuang A A will output-select; ... when the person is transmitting data, the above master control pulls first Low-up data "2 selectors, and the level of the above master control device will be on line, and the level of μ + table, and then pull down the clock to make Sasser complex slave ^ select ㈣, according to the above selection signal, select The ^ belongs to the device, and lowers the level of the selected plural from the above-mentioned master, and the selected slave to the above ... 8 The equipment is used for data transmission. Only the stream is in the seventh place in the scope. The integrated circuit described above is connected to an electronic system, in which the selector includes ... and a complex; the input device is connected to the above selection signal with a complex input terminal, and the complex wheels include: a input Terminal is coupled to the above-mentioned demultiplexing industry connection bus: heliocentric ::-the second input terminal is coupled to the above-mentioned integrated circuit: from the MPW rb t pulse line, and an output terminal is coupled to the above # The second end of one of the members of the clothing set. The integrated circuit described in item 8 of the scope is used to implement the non-electrical system of the above, which is implemented by the above, and the Quanhui logic gate. The described use of integrated circuit and @ Logic gate to achieve. And closed system hunting by-Tu one coupled separately 0739-9121twf(ni);91p〇32;DENNIS.ptd 11. 一種使用積體電路連線匯流排為介面之 / ,適用於一主控裝置與複數具有相同Pc 、少專輪 裝置,其中上述主控裝[具有一第—y、c= 之從屬 第15頁 1223159 六、申請專利範圍 接至一積體電路連線匯流排之資料信號線以及時脈信號 線,上述每個從屬裝置均具有一第一端以及一第二端,上 述第一端耦接至上述匯流排之資料信號線,上述資料傳輸 方法,包括: 提供一選擇器,具有複數輸出端分別耦接至上述複數 從屬裝置之第二端,一輸入端耦接至上述匯流排之時脈信 號線,以及一控制端; 當上述主控裝置欲進行資料傳輸時,上述主控裝置會 輸出一選擇信號至上述選擇器之控制端,以及一啟始信號 至上述積體電路連線匯流排之上;以及 上述選擇器係依據上述選擇信號及上述啟始信號,從 上述複數從屬裝置中選出任一者與上述主控裝置進行資料 傳輸。 1 2.如申請專利範圍第1 1項所述之使用積體電路連線 匯流排為介面之資料傳輸方法,其中上述主控單元係先拉 低上述資料信號線的準位,接著再拉低上述時脈信號線的 準位,以作為輸出至上述積體電路連線匯流排上之上述啟 始信號。0739-9121twf (ni); 91p〇32; DENNIS.ptd 11. A type of integrated bus connection interface / /, suitable for a master control device and plural devices with the same Pc, less special wheel device, where the above main Control device [has a slave of —y, c = Page 15 1223159 6. Patent application scope Data signal line and clock signal line connected to a integrated circuit connection bus, each of the above-mentioned slave devices has a A first end and a second end, the first end is coupled to the data signal line of the bus, and the data transmission method includes: providing a selector having a plurality of output ends respectively coupled to the first of the plurality of slave devices; Two terminals, an input terminal is coupled to the clock signal line of the bus, and a control terminal; when the main control device wants to transmit data, the main control device outputs a selection signal to the control terminal of the selector And a start signal on the integrated circuit connection bus; and the selector is selected from the plurality of slave devices according to the selection signal and the start signal. For the above-described data transmission by the master device. 1 2. The data transmission method using integrated circuit connection bus as interface described in item 11 of the scope of patent application, wherein the main control unit first pulls down the level of the data signal line, and then pulls down The level of the clock signal line is used as the start signal output to the integrated circuit connection bus. 0739-9121twf(nl);91P032;DENNIS.ptd 第16頁0739-9121twf (nl); 91P032; DENNIS.ptd page 16
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI402678B (en) * 2008-12-25 2013-07-21 Mitsubishi Electric Corp Data communication system and data communication device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI402678B (en) * 2008-12-25 2013-07-21 Mitsubishi Electric Corp Data communication system and data communication device

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