1222751 玫、發明說明： 【發明所屬之技術領域】 本發明係關於驅動 MOSFET(Metal-Oxide-Silicon Field Effect Transistor ;金屬氧化物矽場效電晶體）、IGBT (Insulated Gate Bipolar Transistor :絕緣閘雙極性電晶體） 等之閘極之閘極驅動電路。 【先前技術】 為了使MOSFET等半導體開關元件施行開關動作，需要使 用閘極驅動電路。圖5係表示以往之閘極驅動電路之例之電 路圖。圖5之閘極驅動電路係構成單片方式，如圖所示，例 如具有5個NPNi電晶體11、12、13、14及15。電晶體11及 12採用達林頓式連接方式，電晶體14及15也採用達林頓式 連接方式。 電晶體11係用於放大由未圖示之控制部供應之控制訊號 SC。電晶體12係依據電晶體11所放大之控制訊號，使電源 端子T1與M0SFET1之閘極之間通電或斷電。又，電源電壓 係被供應至電源端子T1。 電晶體13係用於產生相當於使控制訊號sc之相位反轉之 訊號之控制訊號SC/。 電晶體14係用於放大控制訊號SC/。電晶體15係依據電晶 體14所放大之控制訊號sc/，使接地端子gnd與M0SFET1 之閘極之間通電或斷電。 在圖5之閘極驅動電路中，控制部使控制訊號sc成為高位 準（以下稱”H”）時，可使基極被供應控制訊號sc之電晶體11 1222751 、通電。集極連接於電源端子以之電晶將控制訊號 SC放大而供應至電晶體12之基極。其結果，使電晶體咖 電，而將電源端子TmM0SFET1之閘極電性連接。因此， M0SFET1之閘極被驅動成為” H”，而使m〇sfeti通電。 在電晶體13通電之期間，電晶體13之集極電壓下降，使 控制訊號SC/成為低位準（以下稱"L”）。使基極連接於電晶體 13之集極之電晶體14斷電，並使電晶體15也斷電。 控制部使控制訊號SC成為”L，，時，可使基極被供應控制訊 號SC之電晶體11、1 3斷電。利用電晶體丨丨之斷電，使電晶 體12斷電’而J字M0SFET1之閘極由電源端子T1電性切離。 相對地，利用電晶體丨3之斷電，電晶體丨3之集極電壓藉 電流源16而上升，使控制訊號sc/成為"H"。集極連接於 M0SFET1之閘極之電晶體14將控制訊號sc/放大而供應至 電晶體15之基極。被供應放大之控制訊號sc/之電晶體15通 電’將M0SFET1之閘極連接於接地端子，因此，M0SFET1 之閘極成為，，L"，使M0SFET1斷電。 【發明所欲解決之問題】 但’在圖5之閘極驅動電路卻有如下之問題。即，有時被 認定在驅動對象之M0SF]ETi之閘極與源極之間，如圖所示 ’有寄生電容20，並連接著配線圖案等所形成之電感21。 在此情形下，M0SFET1斷電時，電感21會產生感應電壓， 而使電流以繞道方式經由寄生電容20而流通於M0SFET1之 閘極、源極之間。此電流會使MOSFET1之閘極電壓下降， 並使電晶體14之集極電位低於射極電位，而使寄生於電晶 1222751 體14之寄生電晶體23啟動。 圖6係寄生電晶體23之構成之說明圖。在半導體基板上形 成NPN型電晶體14時，例如在p型基板24之表面形成構成集 極之局雜質濃度之n +型之埋入層25，在基板24上形成之低 雜質濃度之η—型之磊晶層26，施行元件分離後，在磊晶層 26内形成ρ型之基極27、η +型之射極28、與連接於集極（埋 入層25)之插塞29。寄生電晶體23係以電晶體14之基極27作 為射極，以構成電晶體14之集極之埋入層25作為基極，以 構成接地端子之基板24作為集極之ρΝρ型電晶體。 寄生电日日體23通電時，使預備供應至電晶體丨4之基極之 控制λ號sc/流通至接地端子。因此，電晶體14斷電而不再 將基極電机供應至電晶體丨5之基極，故本來應通電之電晶 體15成為斷電狀態。而，在M0SFET1之閘極電壓進一步低 於接地電壓時，以雷。曰辦^j 。 ^ a體14及15之集極層作為射極之npn 型寄生電晶體3 0成Λ ϋ雪处& , ^ 一 风馮通電狀恶。此寄生電晶體30之集極係 同一晶片上之磊晶層26，合導屮i丨而 θ V出其他PNP型電晶體之基極電 及其他NPN型電晶體之隼極 木位冤/爪等，因此，圖5之閘極驅 動電路引起錯誤動作之可能性相當大。 【發明内容】 本發明係為消除此種以往^ ^ ^ ^ ^ ^ ^ 楹桠π +、 仕之問碭而设計者，其目的在於 故供可充分防止錯誤動作 、 切吓之閘極驅動電路。 為了達成上述目的，本發 ^ M ^ . ^ ^ ^ χ月之弟一硯點之閘極驅動電路 < W徵在於包含： 開關電路40，其係依據 工制戒號，使驅動對象之電晶體 1222751 之閘極與第一電壓源之間通電或斷電者； 驅動用雙極性電晶體51，其係形成於半導體 含弟一電極、第二電極、及控制電極^ 匕 放大供應至該控制電極之訊號而由該第控制訊號 μ 乐一電極輸出去· 整流元件53,其係連接於前述閑極與前述第_電極之 二妨礙寄生於前述驅動用雙極性電晶體51之寄生電晶體 通電，防止前述訊號繞道前述驅動 曰曰执 制電極者；及 U 曰㈣之控 開關用雙極性電晶體52，其係形成於前料導體基板上 ，包含連接於前述第二電極之栌制带 土 m枚V、， 控制电極、連接於前述閘極 被放：之° : #於第二電壓源之第四電極，依據前述 被=大之《，與前述開關電路4〇互補地使該間極與該第 一電壓源之間通電或斷電者。 :用此種構成時’開關電路可使驅動對象之電晶 極與第一電壓源之間iS雷七I + 間通電或斷電，開關用雙極性電晶體可 與開關電路互補地使第二電遷 电i嫁興閘極之間通電或斷電。 在此’在開關電路切換閑極與第一電堡源之間通電或斷電 整流几件也可妨礙寄生電晶體通電，故開關用雙極 :電晶體可使第二電㈣與閉極之間確實地通電或斷電， 藉以防止錯誤動作。 又’ f述開關電路40也可形成於前述半導體基板上。 ，又前述驅動用雙極性電晶體51之周圍也可被形成於前 述半導體基板上之插塞69所包圍。 又，前述開關用雙極性電晶體52與前述整流元扣之周 1222751 圍也可被前述半導體基板上之磊晶生長層66所包圍，該磊 晶生長層6 6可被特定電壓所偏壓。 又，前述開關用雙極性電晶體52之周圍也可被形成於前 述半導體基板上之插塞89所包圍。 又，七述第一電壓源也可為供應電源電壓之電壓源，前 述第二電壓源也可為供應接地電壓之電壓源。 【實施方式】 以下，參照圖式說明有關本發明之實施形態之閘極驅動 電路。 圖1係表示有關本發明之實施形態之閘極驅動電路之構 成圖。此閘極驅動電路係用於驅動圖1所示之M〇sfet (Metal-Oxide-Silicon Field Effect Transist〇r)1之電路。 此閘極驅動電路係包含第一開關電路4〇、第二開關電路 5〇、及控制訊號變壓電路6〇。此等3個電路係形成於共通之 半導體基板上。 第開關電路40係使電源電壓Vcc之供應源與MOSFET1 之閘極之間通電或斷電之電路，具有被達林頓式連接之2個 NPN型私日日體41及42。電晶體41及42之集極連接於電源電壓 Vcc之供應源。電晶體41之基極被供應來自未圖示之控制部 之抆制訊號SC。電晶體41之射極連接於電晶體42之基極。 電晶體42之射極連接於mosfETI之閘極。 第一開關電路50係用於與第一開關電路4〇互補地 (eomplementarily)使接地端子與m〇sfeti之閘極之間通電 或斷電之電路。第二開關電路5〇具有被達林頓式連接之2個 1222751 NPN型電晶體51、52與二極體53。NPN型電晶體5 1之隽極連 接於二極體53之陰極。二極體53之陽極與電晶體52之集極 連接於M0SFET1之閘極。電晶體51之射極連接於電晶體52 之基極。電晶體52之射極連接於接地端子。 笔晶體5 1及二極體5 3具體上例如如圖2所示，係形成於半 導體基板上。即，如圖所示，在P型基板64之表面形成構成 集極之高雜質濃度之n+型之埋入層65，在基板64上形成之 低雜質濃度之η—型之磊晶層66，施行元件分離後，在磊晶 層66内形成ρ型之基極67、η +型之射極68、與連接於集極 (埋入層65)之插塞69。又，如圖所示，在磊晶層％内形=有 成為二極體53之陽極之ρ型半導體層71，在半導體層71内形 成有成為二極體53之陰極之η型半導體層72。 在電晶體51，與圖6之構成之電晶體14同樣地，寄生著寄 生電晶體23。又，在圖！之構成之電路中，也與，之構成 同樣地寄生著以電晶體5丨及52之集極層作為射極之ΝρΝ型 之寄生電晶體30。 寄生於採取圖2之構成之電晶體5丨之寄生電晶體2 3係以 電晶體51之基極67作為射極，以構成電晶體“之集極之埋 入層65作為基極，以構成接地端子之基板料作為集極之 型電晶體。為了降低圖2之構成之寄生電晶體23之放大率， 如圖所示，插塞69係以包圍電晶體51之周邊之方式形成。 又’在圖2之構成中’為了降低寄生電晶體23之放大率， 二極體53及電晶體52係被配置成與其他元件之間保持一定 量以上之距離之狀態。 -10- 1222751 又，在圖2之構成中，如圖所示，二極體53係構成周圍被 磊晶層66包圍之狀態。又，電晶體52也構成周圍被磊晶層 66包圍之狀態。而，磊晶層66則被電源電壓Vcc或其他適合 於降低寄生電晶體30之放大率之適當電壓所偏壓。 控制訊號變壓電路60係施行控制訊號％之變壓之電路。 控制訊號變壓電路60包含一端連接於電源電壓Vcc之供應 源之定電流源6 1、與集極連接於定電流源6丨之他端之NpN 型電晶體62。電晶體62之基極被供應控制訊號sc。電晶體 62之射極連接於接地端子。電晶體62之集極連接於第二開 關電路50之電晶體51之基極。而，電晶體62之集極成為輸 出反轉控制訊號SC之相位之控制訊號SC/之端。 又’如圖1所示，在驅動對象之MOSFET1之閘極與添趣 間存在有寄生電容20。又，在M〇SFET1之源極與接地端子 之間連接形成配線等之電感2 1。 其次’說明本實施形態之閘極驅動電路之動作。 控制部使控制訊號SC成為高位準（以下稱”η，，）時，可使基 極被供應控制訊號S C之電晶體41、6 2通電。集極被供應電 源電壓Vcc之電晶體41將控制訊號SC放大而供應至電晶體 42之基極。於是，使電晶體42通電，而將電源電壓Vcc供應 至MOSFET1之閘極。其結果，MOSFET1之閘極被驅動成 為”H’f而使MOSFET1通電。 在電晶體62通電之期間，電晶體62之集極電壓下降，使 控制訊號SC/成為低位準（以下稱”L”）。因此，使基極連接於 電晶體62之集極之電晶體51斷電，並使電晶體52也斷電。 -11 - 1222751 控制部使控制訊號SC成為”L”時，可使基極被供應控制訊 號SC之電晶體41及62斷電。 利用電晶體41之斷電，使電晶體42也斷電，其結果，將 M0SFET1之閘極由電源電壓Vcc之供應源電性切離。 相對地，使電晶體62斷電時，定電流源61使電晶體62之 集極電壓上升，使控制訊號SC/成為ΠΗ”。電晶體5 1將此控 制訊號SC/放大而供應至電晶體52之基極。被供應放大之控 制訊號SC/之電晶體52通電，將M0SFET1之閘極連接於接地 端子，其結果，M0SFET1之閘極成為 ，使M0SFET1斷 電。 又，M0SFET1斷電時，電感21會產生感應電壓，而使電 流以繞道方式經由寄生電容20而流通於M0SFET1之閘極、 源極之間。此電流會使MOSFET1之閘極電壓下降。但，因 MOSFET1之閘極與電晶體51之集極之間連接有二極體53， 故可妨礙寄生電晶體23通電。其結果，可防止供應至電晶 體5 1之基極之控制訊號SC/流至接地端子，確實將基極電流 供應至電晶體52。由於電晶體52之集極之電位低於電晶體 52之射極之電位，可使電晶體52施行反放大率動作（反電晶 體動作），而使基極電流之放大率倍之電流流至電晶體52之 集極一射極間。 在圖1之閘極驅動電路之動作中，如圖3所示，電晶體52 施行反放大率動作時（TERM1)，MOSFET1之閘極電壓V不會 低於電晶體52之飽和電壓VCE(SAT)，因此，寄生電晶體30 也不會通電。另外，由於採行將寄生電晶體30之電流放大 1222751 故可防止其他PNP型電晶體之錯 率極力抑制在低值之設計， 誤動作。 又，因電晶體51之集極與M0SFET1之閘極之間連接有一 極體53，電晶體5丨之基極電流不會流至接地端子。因此， 可確實將電晶體51之基極電流供應至電晶體52之基極，使 電晶體52確實通電。 ° 又，因電晶體51被插塞所包圍，可將寄生電晶體23之放 大率保持於低值，因此，此插塞也有使電晶體”之基極電 流難以流過接地端子之機能。 又’電晶體52之周圍受到被施加偏壓之i晶層所包圍， 其結果，可將寄生電晶體3〇之電流放大率保持於低值，因 此，圖1之閘極驅動電路因寄生電晶體3〇之通電而 動作之危險性較低。 —又，在實施本發明之際，可考慮採行種種㈣，並不限 定於上述實施形態。例如，在圖i之閘極驅動電路中，也可 將NPN型電晶體變更為⑽型電晶體，且可使二極體53之極 性及電源電壓Vcc之極性反轉。又，圖i之閘極驅動電路也 可利用IGBT作為驅動對象之電晶體，以取代m〇sfet。 又，如圖4所示，電晶體52也可被插塞所包圍。電晶體^ 採用此種構成時，可將寄生電晶㈣之放大率保持於低值 。又，圖4所示之電晶體52係由形成於p型基板64表面之n + 型之埋入層85形成之集極、在元件分離後形成於基板“上 之上述磊晶層66内之p型之基極87、及n+型之射極Μ所構 成。而，如圖所示，插塞89係以包圍電晶體52之周邊之方 -13- 1222751 式形成。 【發明之效果】 如以上所詳述，依據本發明，可實現充分防止錯誤動作 之閘極驅動電路。 【圖式簡單說明】 圖1係表示有關本發明之實施形態 成之電路圖。 之閘極驅動電路之構 圖2係電晶體及二極體之剖面圖。 圖3係圖1之閘極驅動電路之動作之說明圖 圖4係電晶體之變形例之剖面圖。 回 圖5係以往之閘極 圖6係寄生電晶體 圖式代表符號說明 驅動電路之電路圖。 之構成說明用之剖面 圖。 16 20 21 30 40 50 51 52 53 60 MOSFET 電流源 寄生電容 電感 ΝΡΝ型寄生電晶體 第一開關電路 第二開關電路 驅動用電晶體 開關用雙極性電晶體 二極體 控制訊號變塵電路 -14- 611222751 66 71 11-15 、 41， 42 23, 30 24, 27, 64 25, 65, 851222751 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a driving MOSFET (Metal-Oxide-Silicon Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor) Transistor) and other gate drive circuits. [Prior Art] In order to perform switching operation of a semiconductor switching element such as a MOSFET, a gate driving circuit is required. Fig. 5 is a circuit diagram showing an example of a conventional gate driving circuit. The gate driving circuit of FIG. 5 is configured in a monolithic manner, as shown in the figure, for example, it has five NPNi transistors 11, 12, 13, 14, and 15. Transistors 11 and 12 use Darlington connection, and transistors 14 and 15 also use Darlington connection. The transistor 11 is used to amplify a control signal SC supplied from a control section (not shown). Transistor 12 is based on the control signal amplified by transistor 11 to energize or de-energize power terminal T1 and the gate of MOSFET1. The power supply voltage is supplied to the power supply terminal T1. The transistor 13 is used to generate a control signal SC / which is equivalent to a signal which reverses the phase of the control signal sc. The transistor 14 is used to amplify the control signal SC /. The transistor 15 is based on the control signal sc / amplified by the transistor 14, so that the ground terminal gnd and the gate of the MOSFET1 are energized or de-energized. In the gate driving circuit of FIG. 5, when the control section sets the control signal sc to a high level (hereinafter referred to as “H”), the base 11 can be supplied with the transistor 11 1222751 of the control signal sc and energized. The collector is connected to the power terminal, and the transistor amplifies the control signal SC and supplies it to the base of the transistor 12. As a result, the transistor is electrically connected, and the gate of the power supply terminal TmM0SFET1 is electrically connected. Therefore, the gate of M0SFET1 is driven to "H", and m0sfeti is energized. During the period when the transistor 13 is energized, the collector voltage of the transistor 13 decreases, so that the control signal SC / becomes a low level (hereinafter referred to as " L "). The transistor 14 having the base connected to the collector of the transistor 13 is turned off. The power is also turned off, and the transistor 15 is also turned off. When the control unit sets the control signal SC to "L", the transistors 11, 1 and 3 to which the base is supplied with the control signal SC are turned off. The power of the transistor 丨 丨 is used to power off the transistor 12 'and the gate of the J-shaped MOSFET 1 is electrically cut off by the power terminal T1. In contrast, with the power off of the transistor 3, the collector voltage of the transistor 3 rises by the current source 16, so that the control signal sc / becomes " H ". The transistor 14 whose collector is connected to the gate of the MOSFET 1 supplies the control signal sc / amplified to the base of the transistor 15. The transistor 15 supplied with the amplified control signal sc / is powered on 'to connect the gate of M0SFET1 to the ground terminal. Therefore, the gate of M0SFET1 becomes, "L", to power off M0SFET1. [Problems to be Solved by the Invention] However, the gate driving circuit in FIG. 5 has the following problems. That is, it may be considered that between the gate and the source of the driving target M0SF] ETi, there is a parasitic capacitance 20 as shown in the figure, and an inductance 21 formed by a wiring pattern or the like is connected. In this case, when M0SFET1 is powered off, the inductor 21 will generate an induced voltage, and the current will flow between the gate and the source of M0SFET1 via the parasitic capacitor 20 in a detour manner. This current causes the gate voltage of the MOSFET 1 to drop, and causes the collector potential of the transistor 14 to be lower than the emitter potential, and causes the parasitic transistor 23 parasitic to the transistor 1222751 body 14 to start. FIG. 6 is an explanatory diagram of the structure of the parasitic transistor 23. When forming an NPN-type transistor 14 on a semiconductor substrate, for example, an n + -type buried layer 25 constituting a local impurity concentration of the collector is formed on the surface of the p-type substrate 24, and a low impurity concentration η-is formed on the substrate 24. In the epitaxial layer 26 of the type, after the element is separated, a p-type base 27, an n + type emitter 28, and a plug 29 connected to the collector (embedded layer 25) are formed in the epitaxial layer 26. The parasitic transistor 23 is a pn type transistor with the base 27 of the transistor 14 as the emitter, the buried layer 25 constituting the collector of the transistor 14 as the base, and the substrate 24 constituting the ground terminal as the collector. When the parasitic electric sun body 23 is energized, the control lambda sc / which is to be supplied to the base of the transistor 4 is distributed to the ground terminal. Therefore, the transistor 14 is de-energized and the base motor is no longer supplied to the base of the transistor 5, so the transistor 15 which should have been energized becomes a de-energized state. However, when the gate voltage of M0SFET1 is further lower than the ground voltage, the lightning is applied. Said to do ^ j. ^ The collector layers of a body 14 and 15 are npn-type parasitic transistors 30 as emitters, which are Λ ϋ ϋ snow place & The collector of this parasitic transistor 30 is the epitaxial layer 26 on the same wafer, which is combined with 屮 i 丨 and θ V is the base of other PNP transistors and the poles of other NPN transistors. Therefore, there is a high possibility that the gate driving circuit of FIG. 5 may cause an erroneous operation. [Summary of the invention] The present invention is designed to eliminate such past ^ ^ ^ ^ ^ ^ 楹 桠 π +, the official question, the purpose is to provide a gate drive that can fully prevent erroneous actions and scare Circuit. In order to achieve the above-mentioned purpose, the present invention ^ M ^. ^ ^ ^ The gate driving circuit of the brother of the month 砚 is characterized by including: a switching circuit 40, which is based on the working system ring to make the electric power of the driving object The transistor 1227551 is powered on or off between the gate and the first voltage source; the driving bipolar transistor 51 is formed on the semiconductor including the first electrode, the second electrode, and the control electrode. The signal of the electrode is output by the first control signal μ. A rectifying element 53 is connected to the second electrode and the second electrode to prevent the parasitic transistor parasitic on the driving bipolar transistor 51 from being energized. To prevent the aforementioned signals from detouring the aforementioned driving electrodes; and the bipolar transistor 52 for the U-control switch, which is formed on the pre-conductor substrate, and includes a strip of soil connected to the aforementioned second electrode. The m V, control electrodes, connected to the foregoing gate are placed: °: # to the fourth electrode of the second voltage source, according to the foregoing == big, and complementary to the aforementioned switching circuit 40. Pole with the first voltage Power-off or between those. : With this structure, the 'switch circuit can turn on or off iS thunder I + between the electric target of the drive object and the first voltage source, and the bipolar transistor for the switch can make the second circuit complementary to the switch circuit. The power supply is switched on or off between the gates. Here, switching on or off the switch circuit between the idle pole and the first electric source can also prevent the parasitic transistor from being energized, so the switch is bipolar: the transistor can make the In order to prevent malfunction, ensure that the power is switched on or off. The switch circuit 40 may be formed on the semiconductor substrate. The periphery of the driving bipolar transistor 51 may be surrounded by the plug 69 formed on the semiconductor substrate. In addition, the periphery of the bipolar transistor 52 for switching and the rectifier element buckle 1222751 may also be surrounded by an epitaxial growth layer 66 on the semiconductor substrate, and the epitaxial growth layer 66 may be biased by a specific voltage. The periphery of the switching bipolar transistor 52 may be surrounded by a plug 89 formed on the semiconductor substrate. In addition, the first voltage source described in the seventh may also be a voltage source supplying a power supply voltage, and the second voltage source may also be a voltage source supplying a ground voltage. [Embodiment] Hereinafter, a gate driving circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a gate driving circuit according to an embodiment of the present invention. This gate driving circuit is a circuit for driving Mosfet (Metal-Oxide-Silicon Field Effect Transistor) 1 shown in FIG. 1. The gate driving circuit includes a first switching circuit 40, a second switching circuit 50, and a control signal transformer circuit 60. These three circuits are formed on a common semiconductor substrate. The second switch circuit 40 is a circuit for energizing or de-energizing the supply source of the power supply voltage Vcc and the gate of the MOSFET1, and has two NPN-type private solar bodies 41 and 42 connected by Darlington. The collectors of the transistors 41 and 42 are connected to a supply source of the power voltage Vcc. The base of the transistor 41 is supplied with a control signal SC from a control section (not shown). The emitter of the transistor 41 is connected to the base of the transistor 42. The emitter of transistor 42 is connected to the gate of mosfETI. The first switch circuit 50 is a circuit that is used to electrically connect or disconnect between the ground terminal and the gate of the mosfeti complementary to the first switch circuit 40. The second switching circuit 50 has two 1222751 NPN type transistors 51 and 52 and a diode 53 connected by Darlington type. The cathode of the NPN transistor 51 is connected to the cathode of the diode 53. The anode of diode 53 and the collector of transistor 52 are connected to the gate of MOSFET1. The emitter of the transistor 51 is connected to the base of the transistor 52. The emitter of the transistor 52 is connected to a ground terminal. Specifically, the pen crystal 51 and the diode 53 are formed on a semiconductor substrate, as shown in FIG. 2, for example. That is, as shown in the figure, an n + -type buried layer 65 with a high impurity concentration constituting a collector is formed on the surface of the P-type substrate 64, and an η-type epitaxial layer 66 with a low impurity concentration is formed on the substrate 64. After the element is separated, a p-type base 67, an n + -type emitter 68, and a plug 69 connected to the collector (buried layer 65) are formed in the epitaxial layer 66. As shown in the figure, in the epitaxial layer% internal shape = a p-type semiconductor layer 71 serving as the anode of the diode 53 and an n-type semiconductor layer 72 serving as the cathode of the diode 53 is formed in the semiconductor layer 71 . The transistor 51 is parasitic to a parasitic transistor 23 in the same manner as the transistor 14 of the structure shown in FIG. Again, in the figure! In the circuit having the same structure, the parasitic transistor 30 of the NρN type having the collector layers of the transistors 5 and 52 as the emitters is also parasitic in the same manner as in the structure. The parasitic transistor 2 3 parasitized in the transistor 5 of the structure shown in FIG. 2 uses the base 67 of the transistor 51 as the emitter, and the buried layer 65 constituting the collector of the transistor as the base to constitute The substrate material of the ground terminal is used as a collector-type transistor. In order to reduce the magnification of the parasitic transistor 23 configured as shown in FIG. 2, as shown in the figure, the plug 69 is formed so as to surround the periphery of the transistor 51. In the structure of FIG. 2 'in order to reduce the magnification of the parasitic transistor 23, the diode 53 and the transistor 52 are arranged to maintain a distance of a certain amount or more from other elements. -10- 1222751 In the configuration of FIG. 2, as shown in the figure, the diode 53 constitutes a state surrounded by the epitaxial layer 66. The transistor 52 also constitutes a state surrounded by the epitaxial layer 66. The epitaxial layer 66 It is biased by the power supply voltage Vcc or other appropriate voltages suitable for reducing the amplification of the parasitic transistor 30. The control signal transformer circuit 60 is a circuit which performs a control signal% transformation. The control signal transformer circuit 60 includes one end connection Determination of the source of supply voltage Vcc Current source 6 1. NpN transistor 62 connected to the other end of the constant current source 6 with the collector. The base of transistor 62 is supplied with the control signal sc. The emitter of transistor 62 is connected to the ground terminal. Transistor The collector of 62 is connected to the base of transistor 51 of the second switching circuit 50. The collector of transistor 62 becomes the terminal of the control signal SC / which outputs the phase of the inverted control signal SC. Also shown in FIG. It is shown that there is a parasitic capacitance 20 between the gate of the MOSFET 1 to be driven and Timing. Furthermore, an inductance 21 is formed between the source of the MOSFET 1 and the ground terminal to form a wiring or the like. Next, the description of the present embodiment will be described. The operation of the gate driving circuit. When the control unit sets the control signal SC to a high level (hereinafter referred to as "η,"), the transistors 41 and 62 that supply the control signal SC to the base can be energized. The transistor 41 whose collector is supplied with the power supply voltage Vcc amplifies the control signal SC and supplies it to the base of the transistor 42. Then, the transistor 42 is energized, and the power source voltage Vcc is supplied to the gate of the MOSFET1. As a result, the gate of MOSFET1 is driven to "H'f" and MOSFET1 is energized. While transistor 62 is energized, the collector voltage of transistor 62 decreases and the control signal SC / goes to a low level (hereinafter referred to as "L"). ). Therefore, the transistor 51 whose base is connected to the collector of the transistor 62 is turned off, and the transistor 52 is also turned off. -11-1222751 When the control section makes the control signal SC "L", the base can be turned on. The transistors 41 and 62 which are supplied with the control signal SC are de-energized. The transistor 42 is also de-energized by the power-off of the transistor 41. As a result, the gate of M0SFET1 is electrically disconnected from the supply source of the power voltage Vcc On the other hand, when the transistor 62 is powered off, the constant current source 61 raises the collector voltage of the transistor 62 so that the control signal SC / becomes ΠΗ ". The transistor 51 supplies this control signal SC / amplified to the base of the transistor 52. The transistor 52 supplied with the amplified control signal SC / is energized, and the gate of M0SFET1 is connected to the ground terminal. As a result, the gate of M0SFET1 becomes and powers down M0SFET1. In addition, when the M0SFET1 is powered off, an induced voltage is generated in the inductor 21, and a current is passed between the gate and the source of the M0SFET1 via a parasitic capacitor 20 in a detour manner. This current causes the gate voltage of MOSFET1 to drop. However, since the diode 53 is connected between the gate of the MOSFET 1 and the collector of the transistor 51, the parasitic transistor 23 can be prevented from being energized. As a result, the control signal SC / supplied to the base of the transistor 51 can be prevented from flowing to the ground terminal, and the base current can be surely supplied to the transistor 52. Since the potential of the collector of the transistor 52 is lower than the potential of the emitter of the transistor 52, the transistor 52 can perform an inverse magnification operation (anti-transistor operation), and a current that is twice the magnification of the base current flows to The collector-emitter of the transistor 52. In the operation of the gate driving circuit of FIG. 1, as shown in FIG. 3, when the transistor 52 performs an inverse amplification operation (TERM1), the gate voltage V of the MOSFET1 will not be lower than the saturation voltage VCE (SAT of the transistor 52). ), Therefore, the parasitic transistor 30 is also not energized. In addition, because the current of the parasitic transistor 30 is amplified by 1222751, it can prevent the design of the error rate of other PNP transistors to be kept at a low value and malfunction. In addition, since a collector 53 is connected between the collector of the transistor 51 and the gate of the MOSFET1, the base current of the transistor 5 does not flow to the ground terminal. Therefore, the base current of the transistor 51 can be surely supplied to the base of the transistor 52, and the transistor 52 can be surely energized. ° Also, because the transistor 51 is surrounded by a plug, the magnification of the parasitic transistor 23 can be kept at a low value. Therefore, this plug also has the function of making it difficult for the base current of the transistor to flow through the ground terminal. 'The periphery of the transistor 52 is surrounded by a biased i-crystal layer. As a result, the current amplification factor of the parasitic transistor 30 can be kept at a low value. Therefore, the gate driving circuit of FIG. 1 due to the parasitic transistor The danger of operating at 30 is low.-Also, in the implementation of the present invention, it is possible to consider various methods and is not limited to the above embodiment. For example, in the gate driving circuit of FIG. The NPN-type transistor can be changed to a ⑽-type transistor, and the polarity of the diode 53 and the polarity of the power supply voltage Vcc can be reversed. In addition, the gate driving circuit of Fig. I can also use an IGBT as the driving transistor. In order to replace m0sfet. Also, as shown in FIG. 4, the transistor 52 can also be surrounded by a plug. When the transistor ^ adopts this structure, the magnification of the parasitic transistor can be kept at a low value. The transistor 52 shown in FIG. 4 is formed by a p-type substrate 64 Surface of n + -type collector buried layer 85 is formed of the electrode, the device isolation is formed on the p-type epitaxial layer 66 within the above-described substrate on the "base electrode 87 and n + -type emission is extremely Μ constituted. As shown in the figure, the plug 89 is formed so as to surround the periphery of the transistor 52 -13-1222751. [Effects of the Invention] As described in detail above, according to the present invention, a gate driving circuit capable of sufficiently preventing an erroneous operation can be realized. [Brief Description of the Drawings] Fig. 1 is a circuit diagram showing an embodiment of the present invention. Structure of the gate drive circuit Figure 2 is a cross-sectional view of a transistor and a diode. Fig. 3 is an explanatory diagram of the operation of the gate driving circuit of Fig. 1. Fig. 4 is a sectional view of a modified example of the transistor. Back Figure 5 is a conventional gate Figure 6 is a parasitic transistor A cross-sectional view for explaining the structure. 16 20 21 30 40 50 51 52 53 60 MOSFET current source parasitic capacitance inductance PN parasitic transistor first switching circuit second switching circuit driving transistor switch bipolar transistor diode control signal dust changing circuit-14- 611222751 66 71 11-15, 41, 42 23, 30 24, 27, 64 25, 65, 85
26, 66 28, 68, 88 29, 89 51，52, 62 67, 87 GND sc，SC/ T126, 66 28, 68, 88 29, 89 51, 52, 62 67, 87 GND sc, SC / T1
Vcc 定電流源 蠢晶生長層 半導體層 NPN型電晶體 寄生電晶體 P型基板 n +型之埋入層 η-型之蠢晶層 η+型之射極 插塞 電晶體 Ρ型之基極 接地端子 控制訊號 電源端子 電源電壓Vcc Constant current source Stupid crystal growth layer Semiconductor layer NPN type transistor Parasitic transistor P-type substrate n + type buried layer η-type stupid layer η + type emitter plug transistor P-type base ground Terminal control signal Power supply voltage
-15--15-