TWI222527B - Apparatus and method for inspecting array substrate - Google Patents

Abstract

The present invention provides an apparatus and a method for inspecting an array substrate at high speed, wherein an electric charge is written to auxiliary capacitors 52 employing the electric charge written to a parasitic capacitor 48a after writing an electric charge to the parasitic capacitor 48a of a signal line 44a, and the electric charge is read after writing an electric charge to the parasitic capacitor 48a of the signal line 44a employing the electric charge written to the auxiliary capacitors 52.

Description

1222527 — V. Description of the invention (1) Field of the invention The present invention relates to a method for inspecting a taboo. Background of the invention of the device for running the array substrate = the polycrystalline stone liquid crystal display shown in FIG. 5 (the __ array substrate is arranged in an eight-way array to include a 'pixel-pixel' portion 14 and a peripheral circuit portion 2 In FIG. 5, the pixel portion 14 includes a plurality of control lines 42a, 42b, and 42i in the lateral direction (longitude side), and a plurality of signal lines 44a that intersect with each other in an electric shock type and have no contact between the control lines 42a, 42b, and 42i. , 4 cents and 44 j, and the pixel 54 placed at the intersection of each control line and signal line. The pixel 54 includes a first switching element 50 and an auxiliary capacitor 52. Compared to the first switch 50, The first terminal is connected to a control line, the second terminal is connected to a signal line, and the third terminal is connected to an auxiliary capacitor 52. Dangdi: The switching element 50 is a thin film transistor (TFT) or the like. The terminal element is day guard, the first terminal is a gate, the second terminal is a source, and the third terminal is an electrode.

The peripheral circuit part includes a first driver 38 for sending a signal to each control line 42a, 42b and 42i to turn on the first switching element 50, and a second switching element 46a connected to each signal line 44a, 44b, and 44j. 46b, 46j, and a second driver 40 for sending a signal to turn on the second switching elements 46a, 46b, and 46j. Each of the signal lines 44a, 44b, and 44j is connected to a signal terminal 32 through the second switching elements 46a, 46b, and 4 6 j.

Page 5 1222527 5. Description of the invention (2) For example, the second switching elements 46a, 46b, and 46j are three-terminal elements such as metal oxide semiconductor field effect transistors (FETs). The first driving state 38 and the second driver 40 are shift registers. In general, detection of defects such as charging characteristics and holding properties of the auxiliary capacitor 52 and the first switching element 50, and short circuit and open circuit of each wiring are performed. Detection device (test is electrically connected to the array substrate 12 as shown in FIG. 5 for detection. ^ = The device 60 includes a write capacitor and an auxiliary capacitor 52, — continued # f _ 冩 入 彳 a 唬 到 female auxiliary capacitor 52 The electric power y °, the way 20 is read from the write signal and is stacked on the auxiliary number to the-driver 38 to send two-way 24-the timing signal signal to the second drive 4 one 1 1 day guard circuit 2 2 for sending A timing driver terminal 36. The second driver &% circuit 24 is connected to the first driver terminal 34. In addition, the _ ^ δ ^ circuit 22 is connected to the driver-switch 26 and the second binary circuit 16 and -The read circuits 20 each have a switching element such as a MOSFET tube.

Vd is explained below with the opening detection device 60. -Write signal to signal terminal 32. The mode of the second switch 26 is entered from the writing circuit 16 to «η to the-driver 40. Pulse signal—input, No. 1222527 V. Description of the invention (3) The second driver 40 inputs a high level signal to the second switching element 46a to turn on the switching element 46a. In addition, the first timing circuit 24 generates a pulse signal to input the signal to the first driver 38. The first switching element 5 0 belonging to the first control line 4 2 a is activated by inputting a high level signal to the first control line 4 2 a. As described above, the first switching element 50 and the second switching element 46a belonging to the first control line 4 2 a are activated, and then a write signal is input to the auxiliary capacitor 52 to write (store) the electric charge. When the second switching element 46a is turned on, the first driver 38 sequentially inputs a high level signal to the control lines 42b and 421, and a pulse signal is continuously generated from the first timing circuit, so that the charges can be continuously written to the auxiliary capacitor 52. After the electric charge is written into the auxiliary capacitor 52 in the pixel 54 belonging to the first signal line 44a, the first switch 26 is turned off and the second switch 30 is turned on. At the same time, Nanping signal is maintained on the first signal line 4 4 a. A pulse signal is continuously generated from the first timing circuit 24 to be input to the first driver 38. The first drivers 38 are sequentially input to the control lines 42a, 42b, and 42i as high-level signals. In this way, the first switching element 50 is sequentially turned on, and the electric charges written in the auxiliary capacitor 52 are continuously read out by the reading circuit 20. The detection of the auxiliary capacitor 52 in the pixel 54 of the first signal line 44a is performed by

Page 7 izzzyz / 5. Description of the invention (4) The above procedures are completed. After the process of inputting the pulse to% from the circuit 22 is completed, the pixel 54 of the second timing signal line 44b, a driver 40, and the above process are repeated to perform the second signal detection of the image capacitor 52 belonging to the signal line. More specifically, after the detection of the auxiliary capacitor 52 in the input r ^ of the timing circuit 22 is completed, the detection of the auxiliary capacitor 52 belonging to the second driver 40 is performed every time from the image ′54 of the second signal line in the second driver 40. Assuming that the charge is written to about 30 megawatts (micro-, and mother: auxiliary capacitor 52 (write time), the time required for cementing the capacitor is determined by the impedance of the wire and the test system. RCtester must be taken into account in the auxiliary capacitor 52 within the time: the appropriate writing time is calculated by adding the time required to often charge the electric charge written in the auxiliary capacitor 52 to this "", ",, # s' is similar to the writing time, but the reading time is determined by adding the time constant Rctester in addition to the writing time. In the array substrate of the "Chiyi" amorphous silicon LCD, each signal terminal 32 can be parallel Connection detection device 60, since all signal lines 44a ^ 4 4b and 44j each have a signal terminal 32 as required. An array substrate 12 of polycrystalline silicon 1 (: 1) placed in a second driver 40 (shift register) The structure of the signal terminal 32 is not provided on all the signal lines 44a, 44b, and 44j. In this way, there is a disadvantage in the connection of the colored soil 1 to the sufficient detection device 60, resulting in the need for detection of the old 7 ^^ — = x The object of the present invention is to provide a method for inspecting an array substrate operating at high speed. Device

Page 8 1222527 V. Description of the invention (5) and its method. SUMMARY OF THE INVENTION The device for inspecting an array substrate of the present invention includes: a device for writing a charge to a parasitic capacitor of a preset signal line; and a device for writing a charge by exclusively replacing the charge in a parasitic capacitor written to a preset signal line To the capacitor in the pixel unit associated with the selected control line; a device for writing the charge to the corresponding capacitor in the pixel to clear the charge stored in the parasitic capacitor of the signal line; a device for converting the A charge to the signal line, a wiring capacitance to write the charge to the signal line; and a device for detecting the charge in the parasitic capacitor written to the signal line. _ The method for inspecting an array substrate provided by the present invention includes the steps of: writing a charge into a parasitic capacitor of a preset signal line; and writing a charge by converting the charge written in the parasitic capacitor of the preset signal line to a capacitor of a pixel To the capacitor in the pixel unit associated with the selected control line; to remove the charge in the parasitic capacitor remaining in the signal line, and to convert the charge written into the capacitor to the signal line and write the charge to the parasitic capacitor in the signal line; and Read the charge in the parasitic capacitor written to the signal line. According to the present invention, the charge is written to the auxiliary capacitor in a manner not used in the conventional technique, and the capacitor stored in the auxiliary capacitor is used to read the charge stored in the auxiliary capacitor using a signal line parasitic capacitor, which can complete the detection of the array substrate in a short time. This makes it possible to inspect a plurality of array substrates in a short time.

1222527

Detailed description of the invention—Comparative examples of the device and method for detecting a high-speed array substrate according to the present invention are described in detail below with reference to the accompanying drawings. ~ :: The two substrates and the array substrate to be detected are a polycrystalline liquid crystal display σσ and include a pixel portion 14 and a peripheral circuit portion. The pixel portion 14 includes a plurality of control lines 423, 4213, and 421. The plurality of lines, 44a, 44b, and 44j are electrically contacted but do not touch the control lines 42/42 \ and 4 2 1, +, and a pixel 5 4 This pixel 54 is placed in the phase parent between the control line and the signal line.卩 分. The pixel 54 includes a first switching element 50 and an auxiliary capacitor 52. At each terminal of the first switching element 50, the first terminal (control terminal) is connected, a control line, the second terminal (first current carrying terminal) is connected to a signal, and the first terminal (the first current carrying terminal) is connected. End) Connect the auxiliary capacitor to cry $ 2. When the switching element 50 is a three-terminal element, the first terminal is a == 5, the second is a source, and the third terminal is a drain.

The peripheral device part includes a first driver 38 for sending a signal to each of the lines 42a, 42b and 42i to turn on the first switching element 50 ° / connected to each of the signal lines 44a, 44b and 44j. Two switching elements 46a, 46b, and 4 6 j, and a second driver 40 for sending a signal to turn on the second switching elements 46a, 46b, and 46j. The signal lines 44a, 44b, and 44j are connected to the signal terminal 32 via the switching elements 46a, 46b, and 46j, respectively. The first driver 38 and the second driver 40 are connected to the first driver terminal 36 and the second driver terminal 34, respectively.

Page 10 1222527 V. Description of the invention (7) The second switching elements 46a, 46b, and 46j are three-terminal elements such as MOSFETs. The first driver 38 and the second driver 40 are shift registers. The detection device 10 for detecting the array substrate 12 includes: a writing circuit 16 for parasitic capacitors 4 8 a 4 8b and 48 j for generating a signal to write a charge to the signal line, and a clear circuit to clear the remaining The electric power in the parasitic capacitors 48a, 48b, and 48j of the signal line is taken from the circuit 20, and the electric charges accumulated in the signal line capacitors 48a, 48b, and 48j are read. A driver 38 and a second timing circuit 22 input a pulse to the second driver 40.

Further, the writing circuit 16, the reading circuit 20, and the erasing circuit 18 are connected to the second switching elements 46a, 46b, and 46j via the first switch 26, the second switch 30, and the third switch 28, respectively. The first switch 26 controls the connection between the writing circuit 16 and the second switching elements 4 6 a, 4 6 b and 4 6 j. The second switch 30 controls the connection between the read circuit 20 and the second switching elements 46a, 46b, and 46j. The third switch 28 controls the connection between the clear circuit 18 and the second switching elements 46a, 46b, and 46. The first switch 26, the second switch 30, and the third switch 28 can be configured as MOSFETs or the like. Another possibility is to integrate the first switch 26, the second switch 30, and the second switch 28 in the write circuit 6, the read circuit 20, and the clear circuit 18, respectively.

1222527 V. Description of the invention (8) A method for detecting the array substrate 2 using a detection device in FIG. 2 will now be described. It is assumed that there are i roots in the control line, [] roots in the signal line, and pixels 5 4 in the parent part of each phase. First, the first switch 26 is turned on, and the writing circuit 16 and the second switching elements 4 6 a, 4 6 b, and 4 6 j are connected to each other. A pulse signal is input from the first timing circuit 24 to the first driver 38. The first driver 38 inputs a signal for turning on the first switching element 50 to the first control line 42a. The first switching element 50 belonging to the first control line 42a is turned on by this signal. The pulse signal is input from the second timing circuit 22 to the second driver 40 at a predetermined interval. As soon as a pulse signal is input, a signal is input to the second driver 40 to turn on the second switching elements 4 6 a, 4 6 b, and 4 6 j in sequence. For example, the electric charge is written into the parasitic capacitor 48a in such a manner that a write signal vd is sent from the writing circuit 16 into the parasitic capacitor 48a, thereby generating a voltage between the writing circuit 16 and the first signal line 44a as shown in FIG. connection. Since the second switching elements 46a, 46b, and 46j are sequentially turned on, the charges are also written into the parasitic capacitors 48a, 48b, and 48j of the plurality of signal lines one by one. When the charge in the parasitic capacitors 48a, 48b, and 48j written to the signal line is expressed as 9_11, the capacity of the parasitic capacitors 48 &, 481), and 48: | is expressed as (: 1 ^, and the write signal voltage is expressed as Vd, You can get the following Equation 1. When the time required to write charges to the capacitors 48a, 48b, and 48j is expressed as Teffect_sw2, the square spear king type Te " ect_sw2 —Reffect-sw2 X Cbus is established as Reffect-sw2 is 1 〇k Ω, Cbus is 100pF, then Teffe ... sw2 = 1 (microseconds). In fact, it is impossible to ignore the time constant RCtestei_ of the measurement system (detection device 1 0), so

Page 12 1222527 V. Description of Invention (9) To use Equation 2 below.

Qbus-wi = C5us x Vd (Equation 1)

Teffect-sw2 = Reffect-sw2 X CbliS + RCtester (Equation 2) The first switching element 5 0 belonging to the first control line 4 2 a is turned on, so that the parasitic capacitor 48a and the auxiliary capacitor 52 can be included as shown in FIG. A circuit with internal resistance 5 8 of a switching element. The electric charges written in the parasitic capacitor 4 8 a are located in the auxiliary capacitor 5 2 of the pixel 5 4 at the intersection of the first control line 42a and the first signal line 44a. Although the control line is turned on when the electric charge is written into the parasitic capacitor, the electric charge written into the parasitic capacitor is due to the high internal impedance of the first switching element 58 and the large constant of the auxiliary capacitor, so that no electric charge is written into the auxiliary capacitor. When the second switching element is turned off after the charge is written to the parasitic capacitor, the circuit structure at this time is shown in FIG. 4, so that the charge is written into the auxiliary capacitor by the parasitic capacitor used as a power source. When the voltage across the parasitic capacitor 48a and the auxiliary capacitor 52 is Vd_w2 after the electric charge is written into the auxiliary capacitor 52, the equation 3 ° Cs can be obtained as the capacitance of the auxiliary capacitor 52. For example, when the capacitances of the parasitic capacitor 48a and the auxiliary capacitor 52 are 100 pF and 0 · lpF, respectively, Cbus X Vd_w2 is much larger than Cs X Vd_w2, so that Equation 3 is more similar to Equation 4. Correspondingly, Vd_w2 is approximately Vd, which is almost the same when the charge is written into the auxiliary capacitor 52 when the write signal voltage is Vd.

Page 13 1222527 V. Description of the invention (10)

Qbus-wl = Cbus X Vd_w2 + Cs X Vd-w2 (Equation 3)

Qbus-Wl and Cbus X Vd_w2 (Equation 4) When the internal impedance 58 of the first switching element 50 is represented as Reffect_swl, the time (time constant) Teffect_swl required to write the charge to the auxiliary capacitor 52 is determined by Equation 5. That is, when Reffect_swl is 30 0 Ω and Cs is 0 · lpF, the write time is 30 / z s.

Tef fect-swl — Reffect-swl X Cs (Equation 5)

Even after the second switching element 46 j connected to the j-th signal line 44 j jumps from ON to OFF, the first driver 38 keeps inputting the signal that turns on the first switching element 50 to the first control Line 4 2 a. Thus, even after the second switching element 46 j connected to the j-th signal line 44 j is turned off, the first switching element 50 belonging to the first control line 42 a remains on for a preset time. In this predetermined time, the charge is written into the auxiliary capacitor 52 using the charge written in the parasitic capacitor 48j. It is also possible to write the charge into the auxiliary capacitor 52 by setting the time as shown in Equation 5.

σ • As soon as the charge is written into the parasitic capacitors 4 4 8b and 48 in a short time], the charge is written into the auxiliary capacitor 52. Since the time required to write to the auxiliary capacitor 52 is longer than the time required to write to 48a, 48b, and 48j, the charge ^ is auxiliary in the auxiliary device 52. Therefore, the completion of the present invention = the time required is shorter than conventional Method. 'Eight to policy Iguchi

$ 14 pages 1222527 V. Description of the invention (11) The charge remaining in the parasitic capacitors 48a, 48b and 48j is now cleared by the clear circuit 18. The time required to clear the charge is expressed as the clear time. The third switch 2 8 is turned on to connect the clear circuit 1 § to each of the second switching elements 4 6 a, 4 6 b, and 4 6 j. A pulse signal is transmitted from the second timing circuit 22 to the second driver 40 within a predetermined interval. The second driver 4 sequentially inputs signals for turning on the second switching elements 46a, 46b, and 46j. The switching elements 46a, 46b, and 46j are turned on in sequence. When the second switching elements 46a, 46b, and 46j are turned on, the parasitic capacitors 4 8a, 4 8b, and 48 j are connected to the clearing circuit via the switching elements 46a, 46b, and 46 j to clear as mentioned above and to be described below. The reason for clearing the parasitic capacitor after reading the charge stored in the auxiliary capacitor is that the charge cannot be accurately detected, that is, when the charge is written to the auxiliary capacitor and the charge stored in the auxiliary capacitor is read, the charge is written to the parasitic Capacitors and charges remain in the parasitic capacitor, making the test results inaccurate. The clearing time is calculated by Equation 2. The third switch 28 is connected to the second signal element 4 6 j of the first signal line 4 4 j and jumps from on to off or closes at the same time. The above-described process is repeated after the writing of the radio waves to the parasitic capacitors 48a, 48b, and 48j and the auxiliary capacitor 52 is completed, and the charges remaining in the parasitic capacitors 48a, 48b, and 48j are cleaned. When repeating, one input pulse signal

Page 15 1222527 V. Explanation of the invention (12) From the input of the first day-to-day circuit 24 to the first driver 38, a signal for turning on the 70th switch is input to the second control line adjacent to the-control line 42a Yidiyicai line 4 2 a 〇 That is, every time the above process is repeated ^ the control line that inputs the signal to turn on the first switching element is sequentially switched. Therefore, the number of control lines repeated in the above / mentioned process makes it possible to accumulate charges in all auxiliary capacitors 52 by inputting a signal for turning on the switch το to all control lines 42 & 42b and 421. Evening φ Ϊ = After the accumulation of the auxiliary capacitors 52, how does the electricity retained by each auxiliary capacitor 52 pass through a so-called "associated day # ΡΗέ 球 * Preservation of the Retention time (0 days) item time , The charges rd ~ r 1 wide 1 accumulated in the auxiliary capacitor 5 2 The following Equation 6 determines that when the two poles of the auxiliary capacitor 52 are repeatedly

Qcs-rl = CS X Vd. Rl (Equation 6) = Self-timing circuit 24 turns to the first driver 3 ^ 2 to turn on the signal from the switching element to the first switching element 50 belonging to the control line 42a. As shown in Figure 4, the parasitic lightning current of the auxiliary electric capacitor μ μ connected to the PM capacitor 52 and the first switching element 50 of the heart and the parasitic lightning of the 仏 line 44a is accumulated on the auxiliary capacitor 52 / 48a + 仃connection. Thus, 48a. How to write charge to parasitic capacitors

Page 16 1222527 V. Description of the invention (13) As shown in Equation 6, the charge stored in the auxiliary capacitor 52 is turned on as shown in Equation 7 when the first switching element 50 is turned on. Vd-r2 is a voltage placed on the parasitic capacitor 48 and the auxiliary capacitor 50. The first part of the equation 7 is the charge accumulated in the parasitic capacitor 4 8 a and the second part is the charge remaining in the auxiliary capacitor 52. For example, the auxiliary capacitor 52 and the parasitic capacitor 48a are respectively 〇ιιιι and 〇〇〇pF, and the expression 〇 ^ X Vd-r2 is much larger than ◦ X Vd_r2, so that Equation 7 is closer to Equation 8 . The charge stored in the auxiliary capacitor 52 can be transferred to the parasitic capacitor 48a.

Qcs-rl = Cbus X Vd.r2 + CS X Vd Qcs-rl ~ Cbus X Vd_r2 (Equation 7) (Equation 8)

After the charge stored in the auxiliary capacitor 52 is converted to the parasitic capacitor 48a, more specifically, after the signal for turning on the first switching element is input from the first driver 38 to the first control line 42a. And after a preset time, the 'second switch 30 is turned on to connect the reading circuit 20 and the second switching elements 46a, 46b and 46j. At the same time, a pulse signal is input from the second timing circuit 22 to the second driver 40 within a preset time interval. The second driver 40 inputs a sign to sequentially turn on the second switching elements 4 6 a, 4 6 b, and 4 6 j. Thus, the plurality of elements 46a, 46b, and 46j are sequentially turned on. Since the switching elements 46a, 46b, and 46j are turned on one after another, the reading circuit 20 is connected to the parasitic capacitors 4 8 a, 4 8 b, and 48 j in this order. At the same time, the charges accumulated on the parasitic capacitors 48 &, 48b, and 48j are read. The reading of the voltage of the parasitic capacitors 48a, 48b and 48j 'replaces the reading of the charge.

Page 17 1222527 V. Description of the invention (14) After reading the charges stored in the parasitic capacitors 4 8 a, 4 8 b and 4 8 j, the signal to turn on the first switching element stops being input from the first driver 38 to the first Control line 42a. The second switch 30 is turned off. After that, the charges remaining in the parasitic capacitors 48a, 48b, and 48j are cleared. The clear circuit 18 is connected to the switching elements 46a, 46b and 46j by turning on the second switch 30. A pulse signal is input from the second timing circuit 22 to the second driver 40 within a preset time interval. The second driver 40 inputs a signal to turn on the second switching elements 4 6 a, 4 6 b, and 4 6 j one by one. The plurality of elements 46a, 46b and 46j are turned on in sequence and the clear circuit 18 is connected to the parasitic valleys Is 48a, 48b, and 48j in turn. Except for the cleaning work after the electric charges are written to the auxiliary capacitor 52, the electricity remaining in the capacitors 48a, 48b, and 48] must be removed. After completing the repetitive process of reading and storing the auxiliary capacitor 52 and the parasitic capacitors 48a, 48b, and 48j, assuming that a pulse signal is cleared from the first charge, the timer circuit 24 and the driver 38 are repeated to turn on the first switch The component signal is input to the 4th 2b, instead of being input adjacent to the control line 42a. That is, every time the above process is repeated, the control lines that are turned on are replaced in turn. Similarly, the above times. By turning on the signals 42b and 42i of the first switching element, it is possible to read the first control elements stored in all the auxiliary first switching elements. The process repeat control is input to all the control capacitors 52. This process. The number of signal lines input to the first control line line 42a controls the charge of the line 42a. 1222527

Piled up and retained in all auxiliary capacitors 5 2 Read. When the auxiliary capacitor 52 cannot be read ~ J The above process = The switching element 50 may be in a charging characteristic, the storage is a failure, and there is a problem with the connection, disconnection, and disconnection. 'Thus, after the array substrate 12 is stacked on the auxiliary: parasitic capacitors 48a, 48b and called, to read the charge (or voltage of the charge) accumulated on 48a, 48b, and 48j _ m Second power: converted from the auxiliary capacitor 52 To the parasitic electric energy, two or more auxiliary capacitors 52 are stacked at the same time r ^ l8? 48j? ^^^ 8a; 48b, 04sl; and switched to the auxiliary capacitor 52. This design reduces the time required to read the charge. For example, after reading the charge stored in the auxiliary capacitor M belonging to the i-th control line 42i, the charge stored in the parasitic capacitors 48a, 48b, and 4 8 j can be omitted.

In addition, 'the defects can be detected in the array substrate i 2 by dividing the substrate 12 into a plurality of regions and performing the above-mentioned entire process'. The explanation is based on the use of an array substrate 4 of a polycrystalline silicon liquid crystal display, as well as an array substrate of other electroluminescence displays.

Page 19

Lzzzyz /

As described above, according to the present invention, the method of the present invention is compared with the conventional method. The device and the parasitic capacitors on the train substrate can shorten the unused signal line W between the leaves in a shorter time. Inside detection array substrate. The example of Han Jiajia's example illustrates that the above inventions are based on the fact of invention & not to limit the invention, any practice: to help understand the scope of the person without departing from the spirit of the invention; Retouch. Tian J f changed slightly

Apparatus: ΐΐ; Example-for examining the core of high-speed arrays ^ ^ Zhi Yuquan explained the features and spirit more clearly. A =, I hope to cover various changes and equal arrangements in the scope of the patent scope of 4 inventors, it is not limited by the scope of the present invention, which is disclosed above. Therefore, the scope of the patent target filed by the inventor should be explained in the broadest terms according to the above description, so that it covers all possible changes and equal arrangements c

Page 20 1222527

The picture shows ΗΗ rr-k. The circuit of the array substrate of X and the device for inspecting the array substrate.

Figure 5 is a conventional circuit diagram. The method of inspecting the array substrate is as follows: 2. The electricity when the switching element is turned on. 1. The electricity technology when the switching element is turned on. Sketch map. Sketch map. The conventional device for checking the array substrate. Figure 6 is a conventional method for checking the timing chart diagram of the array substrate. Symbol description 1 0, 6 0 Inspection device 14 Pixel section 18 Clear circuit 22 Second timing circuit 24th —> Timing circuit 26 First switch 30 Second switch 34 Second horse driver terminal 36 First driver terminal 38th — Drivers 42a, 42b, 42c, 42i Control wires 44a, 44b, 44 j Signal wires 12 1620

40 Array substrate Write circuit Read circuit Third switch Signal terminal Second driver

4 6 a, 4 6 b, 4 6 j 2nd switching element 4 8 a, 4 8 b, 4 8 j Parasitic capacitor of signal line

Page 12 1222527

Page 22

Claims (1)

No. 1222527 M. Year 92. ¥ s 6. Application for Patent Scope 1 · A device for inspecting an array substrate, including: a plurality of control lines; 乂 a plurality of signal lines for delivery and the plurality of control lines, and a two-pixel unit placed in the control Line and the signal line, one of which is a pixel unit, which includes a switching element and 70 pieces, which has one of the control signal lines connected to a corresponding control line, and a current-carrying terminal, and the capacitor is connected to A second current-carrying terminal, the device is used to write a charge to a preset signal line 3S ασ, ^ a device is used to convert the charge written into the preset signal device, and the charge is inserted into J in the socket Λ A capacitor for controlling the early element is selected; a main coat is provided for writing a charge to the pixel unit two; the parasitic capacitor stored in the signal line is a device for writing into the capacitor by conversion = private The parasitic capacitor placed on the signal line is used to detect the signal written to the signal line; a capacitor terminal is connected to the cross section; and the switch is connected to a phase of one of the switching elements. Electricity The electrical appliances in the line phase of the capacity line; the electricity generated by the corresponding capacitor of the pixel generated by the parasitic capacitance; the + + devices for inspecting the array substrate loaded into the signal container, including a plurality of devices Control lines; f, L lines are provided for the control lines; a brother-switching element having a first terminal connected to a control line 1 1111 II Page 23 ___ 11 1222527 Positive replacement meal iiUs ξ QO Ί 1 〇 ^! Case No. 91122295 丨 '~ υ Another day _ «_ VI. Scope of patent application and connection to a second terminal of a signal line, the first A switching element is located at the intersection of the control line and a signal line; a capacitor is connected to a third terminal of the first switching element; a first driver provides a signal to the control line to turn on the first signal The terminal device in the line will finally accept each end of the line to connect the end of the load to the end of the line. The first line element enters the line and connects to the yuan. Write the second switch to open the second. The second number is stored in the first letter, and the first letter is stored in the first letter, and then the Qisheng removes and starts to produce the Qingyuan device for supply, for closing, the road device drive number, capacitor electricity, and the second letter into the electricity. ; The first sketch of the first Qing Qing Yuan yuan, one for one, one post, one electric line, one within the opening number; ·, The first and the second pass, the first to open the electricity, the first to the second, to No. No. 2 Line No. This device Xinxin and Herong Rongchong Road, the pulse pulse, electricity, electricity, one by one, take the product into the write-reading pile, the input, the supply, and the system for reading and reading. For the number of electricity, electricity, and power supply, the power supply is always closed. The meter is opened or received, and the number is 12 and the reading number is the first one, one by one, one by one; One The unit is afclPJ a £ lJ 1222527 Amendment VI. Application for a patent application 3. · A method for inspecting an array substrate, the array substrate having a plurality of control lines, a plurality of signal lines for crossing the plurality of control lines, and a pixel unit 'far pixel unit system At the intersection of a control line and a signal line, each of the pixel units includes a switching element and a capacitor, the switching element having a control terminal connected to a corresponding control line and a corresponding 彳 § number One of the first current-carrying terminals of the line, the capacitor is connected to the second current-carrying terminal of the first switching element, the method includes the steps of: writing a charge to a parasitic capacitor of a preset signal line; The charge written into the parasitic capacitor of the preset signal line is written into the capacitor of the pixel unit, and a charge is written into a capacitor in the pixel unit associated with a selected control line; the remaining in the signal is cleared The charge in the parasitic capacitor of the line is converted from the charge written in the capacitor to the signal line and a charge to the remote signal line. In the capacitor; and, ", read the charge in the parasitic capacitor written to the signal line. 4 · A method to secure a vertical substrate, the array line, and a number of signal lines for crossover The plurality of earth-controlling lines include: a number of control points, in which each pixel unit includes-the second one: the line to the cross section-the second switching element has a connection to-the corresponding two :: pieces-capacitors, And connected to one of the corresponding control lines, one of the first two two, the control terminal is connected to the first switch :: # 二流 流 终-第-Driver selectively drives the control two Pieces === 端 ， ^ 二 厶 〇 厶 I ^ 二 厶 〇 厶 I 丄 -MJt 91122295 ^ 6. Scope of patent application J 『-control terminal, first-current-carrying terminal, = one: should be connected to the signal line and the second driver system :; second-stream = one of the connected control terminals, set the king to violate The first current-carrying terminal of the second switching element, ', === is selectively connected to the second current-carrying element of the second switching element; finally: the first current-carrying element connected to the second switching element is cleared. 1 stream terminal, the: = 2 = the (a) the steps to hear the cricket with the first driver are: (b) connecting the second gate 2-the letter line; the circuit; # ㈤ 凡The remote brother of the piece—the current-carrying terminal to the write (c). The letter (TΛ '/ Λγ charge to the signal line by using the second moving order in turn) The two-generation capacitor, the electric charge in the pixel, the electric pre-m, the electric power and the selected control line have to cry ... a cry < 电容 the capacitor (e) in the pixel early Stop driving the selected control line · ⑴ Connect the first: current-carrying terminal circuit of the second switching element, control the load (g \ by using the second drive The system that drives the second switching element is finally known > The electrical (h) hunting stored in the parasitic capacitor of the signal line is removed by using the first driver to drive the control line selected by Jile Jile And related to the control line selected by the brother a switch element stored in the bathroom, team # Η The charge in the capacitor of the pixel unit is written into the parasitic capacitor of the signal line; (i) the first current-carrying terminal connected to the second switching element to the reading circuit; (j ) By using the second driver to sequentially drive the control terminal of the second switching element, the charge written in the parasitic capacitor of the signal line is read via the second switching element. 5 · The method according to item 4 of the scope of patent application, wherein after the step (g), the steps (a) to (g) are repeated by converting the selected control line to an adjacent control line. If the method described in item 5 of the scope of the patent application is repeated with steps (a) to (g), it further includes step (k) after reading the charge, removing the remaining in the capacitor of the signal line. Charge. 7. The method as described in item 6 of the scope of patent application, wherein after the step (k), repeat the steps (h) to (k) by converting the selected control line to an adjacent control line. 8. The method as described in any one of items 4 or 5 or 6 or 7 of the scope of patent application, wherein steps (a) to (j) are repeated by dividing the plurality of pixel units into a preset number. 4IBM0219TTV-Replacement-061404.ptc Page 27