1221025 五、發明說明（1) 【發明所屬之技術領域 ^本發明係有關於一種晶圓級晶片尺寸封裝結構，特別 係有關於一種具有彈性導接腳之晶圓級晶片尺寸封装结 構。 【先前技術】 曰曰圓曰日片尺寸封袋結構（wafer level chip scale package’ WLCSP)係為一種尺寸微小化之封裝結構，其封 裝尺寸係與晶片尺寸接近或相等’晶圓級晶片尺寸封裝结 程中係在晶圓型態進行封裝，常見的晶圓級晶 ί, ϋ Ϊ裝結構係以銲球作為外部電性導接點，如我國耱 _ : 了 i 97號「晶圓級尺寸封裝結構及其製程」所揭 Ξ刷電路板i!級晶片尺寸封裝結構内晶片與外部接合之 Sdt!不相匹配之熱膨脹係數差異，在接合後會 金屈痛^于或凸塊產生熱應力作用，甚至可能導致鲜球 . 有 曰日片 忒日曰片具有一形成有銲墊之 有一 i力键ί Ϊ晶片之主動區域與（第二）銲球之間係形成 衝層i要足糾層以吸收録球之作用應力，習知該應力緩 :之厚度(約1〇° _以上)方能產生適當之應力 、、打双禾，此一厚度將使得（第二）銲破斑古畲八蟪政 電铲、、、〃接々導接困難 ^積體電路晶圓製作技術如 緩衝層等等均：易形成垂直電性導通過該應力 銲球作為(/二件’故該專利前案係利用被密封之（第一） .、、、第銲球與下方重分配線路之導接，因此，若 12210251221025 V. Description of the invention (1) [Technical field to which the invention belongs ^ The present invention relates to a wafer-level wafer-size package structure, and particularly relates to a wafer-level wafer-size package structure having elastic lead pins. [Prior art] The wafer level chip scale package (WLCSP) is a miniaturized package structure whose package size is close to or equal to the wafer size. In the process of encapsulation, the wafer type is used for packaging. Common wafer-level crystals, the mounting structure uses solder balls as external electrical contact points, such as in China 耱 _: i 97 "wafer-level size "Packaging structure and its process" revealed in the printed circuit board i! Class chip size package structure inside the chip and external bonding Sdt! Mismatched thermal expansion coefficient difference, after the bonding will be painful ^ or thermal stress generated by the bump It may even cause fresh balls. There is a Japanese film and a Japanese film with a pad with an i-force bond. The active area of the wafer and the (second) solder ball form a punch layer i. Layer in order to absorb the stress of the ball, it is known that the stress is moderate: the thickness (about 10 ° _ or more) can produce appropriate stress, hit Shuanghe, this thickness will make (second) welding break ancient畲 八 蟪 government electric shovel ^ Integrated circuit wafer manufacturing technologies such as buffer layers and the like are easy to form vertical electrical conductivity through the stress solder ball (/ two pieces), so the pre-patent case uses the sealed (first). ,,, The connection between the first solder ball and the redistribution line below, so if 1221025
利用銲球或凸塊作為晶圓級晶片尺寸封裝結構之外部導 =丄吟須形成足夠厚度之應力緩衝層，並且製作高深度之 電子元件（第一銲球）亦相當困難。 【發明内容】 本發明之主要目的係在於提供一種晶圓級晶片尺 結構，利用複合式材料構成之複數個導接腳形成於一晶 2之複數個銲墊上，其包含有一線狀金屬層及一介電支撐 ’作為該晶圓級晶片尺寸封裝結構之外部接點，該導接 =t 2至該介電凸塊上之外端係以一金屬覆蓋層連接該線 =金屬層並包覆對應該介電支撐層之一端，使得該介電_ ^層作為該導接腳之外端之芯層（c〇re Uyer)，以增強該 $接腳外端之韌性結構與銲接特性，以取代習知之重分佈 線路層、應力緩衝層與銲球。 曰依本發明之一種晶圓級晶片尺寸封裝結構，包含有一 :片，該晶片之主動面上設有複數個介電凸塊及複數個導 腳’每一導接腳係包含有一線狀金屬層、一介電支撐層 金屬覆蓋層’該些導接腳具有一内端及一外端，該些 接腳之内端係連接對應該些銲墊，該些導接腳之外端係 對2向延伸至該些介電凸塊上，而該些介電支撐層係覆蓋 、應=線狀金屬層，該些金屬覆蓋層係形成於該些導接腳· =外端，該些金屬覆蓋層係電性連接該線狀金屬層並包覆 于應介電支撐層之一端，以取代習知之路層、應 力緩衝層與銲球。 【實施方式】The use of solder balls or bumps as an external guide for a wafer-level wafer-size package structure requires that a stress buffer layer of sufficient thickness be formed, and it is also quite difficult to make high-depth electronic components (first solder balls). [Summary of the Invention] The main object of the present invention is to provide a wafer-level wafer ruler structure. A plurality of lead pins made of a composite material are formed on a plurality of bonding pads of a crystal 2 and include a linear metal layer and A dielectric support is used as the external contact of the wafer-level chip-size package structure, and the lead = t 2 to the upper and outer ends of the dielectric bump is connected to the wire with a metal cover layer = metal layer and covered Corresponds to one end of the dielectric support layer, so that the dielectric layer is used as the core layer (core Uyer) of the outer end of the lead pin, in order to enhance the tough structure and welding characteristics of the outer end of the $ pin, in order to Replaces the conventional redistribution circuit layer, stress buffer layer and solder ball. A wafer-level chip-size package structure according to the present invention includes a sheet, and a plurality of dielectric bumps and a plurality of guide pins are provided on an active surface of the chip. Each of the lead pins includes a linear metal. Layer, a dielectric support layer, and a metal covering layer. The lead pins have an inner end and an outer end. The inner ends of the pins are connected to corresponding solder pads, and the outer ends of the lead pins are connected to It extends to the dielectric bumps in two directions, and the dielectric supporting layers cover and should be linear metal layers. The metal covering layers are formed on the lead pins. The outer ends are the metals. The cover layer is electrically connected to the linear metal layer and covers one end of the dielectric support layer to replace the conventional road layer, the stress buffer layer and the solder ball. [Embodiment]
第7頁 1221025 五、發明說明（3) 參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之一具體實施例，請參閱第1圖，一種晶圓 級晶片尺寸封裝結構1 00係包含有一晶片i i 〇，該晶片i i 0 係具有一形成有複數個銲墊11 2之主動面1 1 1，該主動面 111上設有複數個介電凸塊丨2〇及複數個導接腳丨3〇，該些 介電凸塊1 20係以網板印刷或照相顯影技術設置於該晶片 110之主動面111，該些介電凸塊12〇厚度係介於3〇〜5〇〇" m，較佳為介於60〜180 // m，在本實施例中，該些介電凸塊 120係為印刷形成之矽膠、橡膠或聚亞醯胺等介電膠島， 該些介電凸塊1 2 0係為矩陣排列並對應外部電路板之接合籲 點位置，以供該晶圓級晶片尺寸封裝結構丨〇 〇利用該些導 接腳130與外部電路板接合時之應力緩衝。 每一導接腳130係為一種可微機電（MEMS)製成之複合 式引腳，其係包含有一線狀金屬層1 31、一介電支撐層132 及一金屬覆蓋層133，且每一導接腳130具有一内端130a及 一外端130b ’該線狀金屬層131之製造方法係可在形成該 介電凸塊120之後，先形成一光阻層並顯影出預定形成該 線狀金屬層131之位置’利用濺鑛（sputtering)或蒸鍵 (evaporation)技術形成該線狀金屬層131，該線狀金屬層 131係可為銅、鐵、銘、金或其合金，該些導接腳13〇之内· 端130a以該線狀金屬層1 31電性連接對應該些銲墊1 12(如 第3圖所示），該些導接腳130之内端130a與中間部位以該 介電支撐層1 32覆蓋該些線狀金屬層131，該些導接腳1 30 之外端130b係位於該些介電凸塊120上，較佳地，該些導Page 7 1221025 V. Description of the invention (3) Referring to the attached drawings, the present invention will enumerate the following embodiments. According to a specific embodiment of the present invention, please refer to FIG. 1. A wafer-level wafer size package structure 100 includes a wafer II 0, and the wafer II 0 has an active surface formed with a plurality of solder pads 11 2. 1 1 1. The active surface 111 is provided with a plurality of dielectric bumps 丨 20 and a plurality of lead pins 丨 30. The dielectric bumps 1 20 are disposed on the screen by screen printing or photographic development technology. The active surface 111 of the chip 110, the thickness of the dielectric bumps 120 is between 30 and 500 m, preferably between 60 and 180 // m. In this embodiment, the dielectric The electric bump 120 is a dielectric rubber island such as silicone, rubber, or polyurethane formed by printing. The dielectric bumps 120 are arranged in a matrix and correspond to the positions of the joint points of the external circuit board. The wafer-level chip-size package structure uses the stress buffering when the lead pins 130 are bonded to an external circuit board. Each of the lead pins 130 is a micro-electromechanical (MEMS) -based composite pin, which includes a linear metal layer 1 31, a dielectric support layer 132, and a metal cover layer 133. The lead pin 130 has an inner end 130a and an outer end 130b. The manufacturing method of the linear metal layer 131 is that after the dielectric bump 120 is formed, a photoresist layer is first formed and developed to form the linear shape. The position of the metal layer 131 is formed by the sputtering or evaporation technology. The linear metal layer 131 may be copper, iron, metal, gold, or an alloy thereof. Within the pin 13, the end 130a is electrically connected to the pads 12 by the linear metal layer 1 31 (as shown in FIG. 3), and the inner end 130a of the lead pins 130 and the middle part are connected to The dielectric support layer 1 32 covers the linear metal layers 131, and the outer ends 130b of the conductive pins 1 30 are located on the dielectric bumps 120. Preferably, the conductive bumps 120
第8頁 1221025 五、發明說明（4) 接腳1 3 0之外端1 3 〇 b係斜向延伸呈懸空狀，以作為該晶圓 級晶片尺寸封裝結構1 0 0之外部接合端，請參閱第2圖，在 該些導接腳130之外端130b，該介電支撐層132之一端係局 部覆蓋該線狀金屬層1 3 1，並以該金屬覆蓋層1 3 3電性連接 該線狀金屬層1 3 1並包覆該介電支撐層1 32之該端，使得該 介電支撐層132可作為該些導接腳130之外端130b之芯層 (core layer)，以增強該些導接腳130外端130b之韌性結 構，該些導接腳130外端130b不易被應力或不當外力扯斷 又能保持細小外引腳之型態，故該些導接腳1 3 0同時具有 微線路分佈與導線架引腳之韌性結構，該些金屬覆蓋層 · 133係在該些介電支撐層132及金屬覆蓋層133形成後利用 電鍍或印刷形成，該些金屬覆蓋層1 33係為鎳、鈀、金、 錫、鉛或其合金，以增進銲接特性，利用該些導接腳丨30 與介電凸塊120取代習知之重分佈線路層、應力緩衝層與 鲜球。 本發明之保護範圍當視後附之申請專利範圍所界定者 為準，任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。 第9頁 1221025 圖式簡單說明 【圖式簡單說明】 第1 圖： 依據本發 明之一 具體實施 例， 一 種 晶圓級晶 片 尺 寸封裝結 構之截 面圖； 第2 圖· 依據本發 明之一 具體實施 例， 該 晶 圓級晶片 尺 寸 封裝結構 沿2 - 2之截面圖 ;及 第3 圖： 依據本發 明之一 具體實施 例， 該 晶 圓級晶片 尺 寸 封裝結構 沿3 - 3之截面圖< 0 元件 •符號簡單說明 I 100 晶 圓級晶片尺寸封裝結構 1 110 晶 片 111 主動面 112 銲墊 120 介 電凸塊 130 導 接腳 130a 内端 130b 外端 131 線 狀金屬層 132 介電支撐 層 133 金屬覆蓋層Page 8 1221025 V. Description of the invention (4) Pin 1 3 0 outer end 1 3 0b is obliquely extended to form a floating shape, as the external joint end of the wafer-level chip size package structure 1 0 0, please Referring to FIG. 2, at the outer ends 130 b of the lead pins 130, one end of the dielectric support layer 132 partially covers the linear metal layer 1 3 1, and is electrically connected to the metal cover layer 1 3 3 The linear metal layer 1 31 covers the end of the dielectric support layer 1 32, so that the dielectric support layer 132 can serve as a core layer for the outer ends 130b of the conductive pins 130 to enhance The ductile structure of the outer ends 130b of the lead pins 130, the outer ends 130b of the lead pins 130 are not easy to be broken by stress or improper external force, and can maintain the shape of the small outer pins. Therefore, the lead pins 1 3 0 At the same time, it has the ductile structure of micro-circuit distribution and lead frame pins. The metal cover layers 133 are formed by electroplating or printing after the dielectric support layer 132 and metal cover layer 133 are formed. The metal cover layers 1 33 It is nickel, palladium, gold, tin, lead or its alloy to improve soldering characteristics. Unsubstituted conventional bump 120 of the redistribution wiring layer, and the stress buffer layer of fresh ball. The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. . Page 9 1221025 Brief description of the drawings [Simplified description of the drawings] Figure 1: Sectional view of a wafer-level wafer-size package structure according to a specific embodiment of the present invention; Figure 2 · Implementation according to one of the present invention For example, a cross-sectional view of the wafer-level wafer-size package structure along the line 2-3; and FIG. 3: According to a specific embodiment of the present invention, a cross-sectional view of the wafer-level wafer-size package structure along the line 1-3 < 0 Simple explanation of components and symbols I 100 Wafer-level wafer size package structure 1 110 Wafer 111 Active surface 112 Solder pad 120 Dielectric bump 130 Lead pin 130a Inner end 130b Outer end 131 Linear metal layer 132 Dielectric support layer 133 Metal Overlay
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