TWI220769B - Planarization process - Google Patents

Planarization process Download PDF

Info

Publication number
TWI220769B
TWI220769B TW92119805A TW92119805A TWI220769B TW I220769 B TWI220769 B TW I220769B TW 92119805 A TW92119805 A TW 92119805A TW 92119805 A TW92119805 A TW 92119805A TW I220769 B TWI220769 B TW I220769B
Authority
TW
Taiwan
Prior art keywords
opening
film
deposition
item
flattening
Prior art date
Application number
TW92119805A
Other languages
Chinese (zh)
Other versions
TW200504852A (en
Inventor
Yi-Hao Ting
Sheng-Fen Chiu
Original Assignee
Promos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Promos Technologies Inc filed Critical Promos Technologies Inc
Priority to TW92119805A priority Critical patent/TWI220769B/en
Application granted granted Critical
Publication of TWI220769B publication Critical patent/TWI220769B/en
Publication of TW200504852A publication Critical patent/TW200504852A/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Magnetic Heads (AREA)

Abstract

A planarization process is described. A substrate having a film thereon is provided. A deposition process is performed for covering on the film and filling the opening with a deposition material. Then, a polishing process is performed to remove the partial material and remain other material in the opening and on the film. The deposition process is performed again to deposit the material on the material having been formed. The polishing process is performed again to remove the material until the surface of the film is exposed and also remain some material in the opening. If the surface of the material is not planar, repeating the deposition and the polishing processes until the surface of the material become planar. Since the planarization process includes repeating the deposition and the polishing processes, the issue that the surface of the material is not planar after polishing can be resolved.

Description

12207691220769

-----案號 92119805 五、發明說明(1) 技術領域 本發明是有關於一種半導體製程,且特別是 種平坦化製程。 了』疋β關於一 目前在超大型積體電路(VLSI)之回填開口的製程 利用化學氣相沈積(Chemical Vapor Dep〇sitiQL )來達成,然而此沈積方法仍無法將材料只填入铲吉 =2開口中,因此其必須先沈積一層厚度大於開口深乂二 辟二、’,再進行平坦化步驟將位於開口外的材料去除。^以 目别平坦化的技術來說,化學機械研磨法化學機 (Chemical Mechanical polishing,CMP)是現今n較研常磨法 之王面性平坦化(Global Planarization)的技術。一般而_ 言’在化學機械研磨的過程中,其係藉由具有懸浮研磨粒 子(abrasive particle)的研磨液(siurry)以及具有適當 的彈性(elasticity)與硬度(hardness)的之研磨塾,在晶 圓表面彼此進行相對運動以達成平坦化的目的。換言之, 當研磨墊以按壓的方式於晶圓上移動時,晶圓表面與研磨 液中的研磨粒子會彼此接觸產生摩擦使得晶圓表面產生耗 損,以使其表面逐漸平坦。 第1 A圖到第1 D圖為習知金屬鑲嵌製程的流程剖面示意圖, 此金屬鑲欲製程係為回填開口的其中一種應用。請參照第 1A圖,首先,提供一半導體基底1〇〇,在基底1〇〇中已形成_ 有部份半導體元件(未繪示)。接著,在基底1〇〇上方形成 介電層1 0 2。----- Case No. 92119805 V. Description of the invention (1) TECHNICAL FIELD The present invention relates to a semiconductor process, and in particular to a planarization process.疋 关于 β about a current process for filling backfill openings in very large scale integrated circuits (VLSI) is achieved using chemical vapor deposition (Chemical Vapor DepOsitiQL), but this deposition method still cannot fill the material only into the shovel = 2 opening, so it must first deposit a layer thicker than the depth of the opening, and then perform a planarization step to remove the material outside the opening. ^ For the purpose of flattening, chemical mechanical polishing (CMP) is the technology of global planarization that is the king of conventional grinding methods. Generally speaking, 'in the process of chemical mechanical grinding, it uses a slurry with suspended abrasive particles (siurry) and abrasives with appropriate elasticity and hardness, in The wafer surfaces are moved relative to each other to achieve the purpose of flattening. In other words, when the polishing pad is moved on the wafer in a pressing manner, the wafer surface and the abrasive particles in the polishing liquid will contact each other to cause friction, which causes wear and tear on the wafer surface, so that its surface is gradually flat. Figures 1A to 1D are schematic cross-sectional views showing the flow of a conventional metal inlaying process. The metal inlaying process is one of the applications for backfilling openings. Please refer to FIG. 1A. First, a semiconductor substrate 100 is provided. Some semiconductor elements (not shown) have been formed in the substrate 100. Next, a dielectric layer 102 is formed over the substrate 100.

11292twf1.ptc 第7頁 1220769 案號 92119805 Λ_a. 曰 修正 五、發明說明(2) 然後,請參照第1 B圖,以傳統的微影技術在介電層上1 〇 2 形成一層圖案化之光阻層(未繪示),之後,透過圖案化之 光阻層蝕刻介電層102,以形成圖案化之介電層l〇2a,且 此圖案化之介電層1 0 2 a具有開口 1 0 4。接著,將光阻層剝 除。 之後,請參照第1 C圖,進行一金屬沈積製程以在開口 1 〇 4. 中逐漸填入金屬層1 0 6。 接著,請參照第1 D圖,進行化學機械研磨法,去除開 口 104以外之金屬層106,而保留下為於開口 104内之金屬 層 1 0 6 a 〇 然而在上述的製程中由於開口 1 04較為寬大,當以CVD 形成金屬層1 0 6以填滿開口 1 0 4時,金屬膜層1 0 6之表面就 不會呈現平坦之表面,而後續在進行化學機械研磨時,由 於其研磨接觸面的受力無法均勻分布,因此將無法達到完 全平坦的效果,特別是在開口的部分在研磨後會金屬層 106a呈現淺碟型(dishing)(如第1D圖所示)。 另外,若所欲回填的開口較為窄小時,雖然針對單一 開口來說,在研磨完畢之後金屬層表面並不會出現淺碟型 的缺陷,然而對於連續之多個開口來說,仍會存在研磨不 均勻之情形(erosion)(如第2圖所示)。除此之外,現今元 件製程積集度越來越高,而晶圓表面所堆疊的層數也越來 越多,這些堆疊的圖案化膜層,會使得晶圓表面更加不平 整,而增加了完全平坦化研磨的的困難度。 發明内容11292twf1.ptc Page 7 1220769 Case No. 92119805 Λ_a. Revision V. Description of Invention (2) Then, referring to Figure 1B, a traditional photolithography technique is used to form a patterned light on the dielectric layer 〇2 A resist layer (not shown), and then the dielectric layer 102 is etched through a patterned photoresist layer to form a patterned dielectric layer 102a, and the patterned dielectric layer 1 0 2 a has an opening 1 0 4. Then, the photoresist layer is peeled. After that, referring to FIG. 1C, a metal deposition process is performed to gradually fill the metal layer 106 in the opening 104. Next, referring to FIG. 1D, a chemical mechanical polishing method is performed to remove the metal layer 106 other than the opening 104, and the metal layer 106 in the opening 104 is retained. However, in the above-mentioned process, because of the opening 104, It is relatively wide. When the metal layer 106 is formed by CVD to fill the opening 104, the surface of the metal film layer 106 will not show a flat surface. In the subsequent chemical mechanical polishing, due to its abrasive contact, The force on the surface cannot be evenly distributed, so the effect of complete flatness cannot be achieved. Especially, the metal layer 106a will appear in a shallow dish shape (as shown in FIG. 1D) after the opening is polished. In addition, if the opening to be backfilled is relatively narrow, although for a single opening, the surface of the metal layer will not have a shallow dish-type defect after grinding, there will still be grinding for multiple consecutive openings. Non-uniform erosion (as shown in Figure 2). In addition, the current accumulation of component processes is getting higher and higher, and the number of layers stacked on the wafer surface is increasing. These stacked patterned film layers will make the wafer surface more uneven and increase. Difficulty of completely flattening the polishing. Summary of the Invention

11292twf1.ptc 第8頁 1220769 _案號 92119805 五、發明說明(3) 曰 修正 有鑑於此,本發明的目的就是提供一種平坦化製程, 以解決習知無法達到完全平坦化的問題。11292twf1.ptc Page 8 1220769 _ Case number 92119805 V. Description of the invention (3) Revision In view of this, the object of the present invention is to provide a flattening process to solve the problem that conventional flattening cannot be achieved.

本發明提出一種平坦化製程,此製程係首先提供一基 底,此基底上已形成有薄膜,且此薄膜中已形成有至少一 開口。接著,進行沈積製程以沈積一材料覆蓋於薄膜上並 且填滿開口。之後,進行研磨製程以移除部分之材料,而 保留下位於開口内以及薄膜上之材料。然後,再次進行沈 積製程以於保留下來的材料上繼續沈積材料。接著,再次 進行研磨製程以移除材料直到薄膜的表面裸露出來,而保 留下位於開口内之材料。之後,若位於開口内之材料表面 尚未完全平坦,則重複進行材料之沈積與研磨直到材料表 面完全平坦。 由於本發明的平坦化製程係進行多次沈積與多次研磨 來取代習知技術中的單次沈積與單次研磨,藉由重複的沈 積與研磨以降低上述研磨不均勻之情形,而解決習知無法 達到完全平坦化之研磨的問題。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳 細說明如下: 實施方式 第3圖是繪示依照本發明一較佳實施例的一種平坦化 製程之流程圖,第4Α圖至第4Ε圖是繪示第3圖的一種平坦 _ 化之製程剖面示意圖。 請同時參照第3圖以及第4 Α圖,平坦化製程係首先進The present invention provides a planarization process. This process first provides a substrate, a film has been formed on the substrate, and at least one opening has been formed in the film. Next, a deposition process is performed to deposit a material on the film and fill the opening. Thereafter, a grinding process is performed to remove a portion of the material, while retaining the material located in the opening and on the film. Then, the deposition process is performed again to continue depositing the material on the remaining material. Next, the grinding process is performed again to remove the material until the surface of the film is exposed, leaving the material in the opening. After that, if the surface of the material in the opening is not completely flat, repeat the deposition and grinding of the material until the surface of the material is completely flat. Since the planarization process of the present invention performs multiple depositions and multiple grindings to replace single depositions and single grindings in the conventional technology, repeated depositions and grindings are used to reduce the above-mentioned non-uniform polishing situation, thereby solving the problem. It is known that the problem of polishing that cannot be completely flattened is known. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Embodiment 3 FIG. A flowchart of a planarization process according to a preferred embodiment of the present invention, and FIGS. 4A to 4E are schematic cross-sectional views illustrating a planarization process of FIG. 3. Please refer to Figure 3 and Figure 4A at the same time. The flattening process is first performed.

11292twf1.ptc 第9頁 1220769 曰 修正 =20,此步,〇係為提供一基底3〇〇,基底3 =溥膜3 0 2 ’且薄膜3 0 2中已形成有至少-開口 3 04。复已 :〇4係?叉接觸窗開口、溝渠或雙重鑲喪開口,而、 y 3 2例如疋"電層。值得一提的是,以下之說明係以 早一 f 口 f說明本發明,然而本發明並非只限用於單一開 口,忍即薄膜中若具有多數個開口亦可利用本發明來 平坦化的目的。 取 接著,凊同時參照第3圖以及第4 B圖,進行步驟2 〇 2 ; 此步驟2 0 2係為進行一沈積製程以沈積材料3〇6覆蓋於薄膜 3 0 2上且填滿開口 3 0 4。其中此沈積製程例如是化學氣相沈 積,其反應氣體端視所沈積之材料而定,而所沈積的材料 例如是介電材料、導體材料或半導體材料等,而且介電材 料更例如是二氧化矽、磷矽玻璃(PSG)、硼磷矽玻璃 (BPSG)、氮化矽等,導體材料例如是鎢、銅或多晶矽,半 =^材料例如是矽。其中若沈積的材料3 〇6係為一金屬材 料時,則在步驟2〇〇與步驟2 0 2之間更包括於薄膜以及開口 之表面形成阻障層(例如是鈦/氮化鈦)以防止金屬產生擴 散0 、11292twf1.ptc Page 9 1220769 said correction = 20, in this step, 0 is to provide a substrate 300, substrate 3 = diaphragm film 3 0 2 ′ and at least -opening 3 04 has been formed in the film 3 02. Recovery: 04 series? The fork contacts a window opening, a trench, or a double inlaid opening, and y 3 2 is, for example, an " electrical layer. It is worth mentioning that the following description explains the present invention with an earlier port f. However, the present invention is not limited to a single opening. For example, if there are a plurality of openings in a film, the present invention can be used for planarization purposes. . Then, referring to FIG. 3 and FIG. 4B at the same time, step 002 is performed; this step 202 is to perform a deposition process to deposit the material 306 on the film 3 02 and fill the opening 3 0 4. The deposition process is, for example, chemical vapor deposition, and the reaction gas end depends on the deposited material, and the deposited material is, for example, a dielectric material, a conductor material, or a semiconductor material, and the dielectric material is, for example, dioxide Silicon, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), silicon nitride, etc., the conductor material is, for example, tungsten, copper or polycrystalline silicon, and the semi-metal material is, for example, silicon. Wherein, if the deposited material 306 is a metal material, a barrier layer (such as titanium / titanium nitride) is formed on the surface of the film and the opening between step 2000 and step 202 to form Prevent metal from diffusing

之後,請同時參照第3圖以及第4C圖,進行步驟2〇4, ,步驟2 0 4係為進行研磨製程以移除部分之材料3〇6,而保 ,下位於開口304内以及薄膜302上之材料3〇6a,其中研磨 製程例,是化學機械研磨製程。在此步驟2 0 4中,由於開 口 3 0 4較為寬大,當以C V D沈積材料3 0 6以填滿開口 3 〇 4時, 材料306之表面就不會呈現平坦之表面(如第4B圖所示),After that, please refer to FIG. 3 and FIG. 4C at the same time, and perform step 204, step 204 is to perform a grinding process to remove a portion of the material 300, and the bottom is located in the opening 304 and the film 302. The above material 306a, of which the polishing process example is a chemical mechanical polishing process. In this step 204, since the opening 304 is relatively wide, when the material 306 is deposited by CVD to fill the opening 304, the surface of the material 306 will not appear flat (as shown in FIG. 4B). Show),

12207691220769

五、發明說明(5) 而後續在進行化學機械研磨時’由於研磨接觸面的受力無 法均勻分布,因此將無法達到完全平坦化的效果,特別^ 在開口 3 04的部分其材料3〇 6a表面會呈現淺碟型(dishing) 的開口308(如第4C圖所示)。V. Description of the invention (5) In the subsequent chemical mechanical polishing, 'the force on the grinding contact surface cannot be evenly distributed, so it will not be able to achieve a complete flattening effect, especially in the part of the opening 3 04 whose material is 306a The surface will present shallow openings 308 (as shown in Figure 4C).

然後,請同時參照第3圖以及第4D圖,進行步驟2 〇 6, 此步驟2 0 6係為再次進行沈積製程以於保留下來的材料 3 0 6 a上繼續沈積材料3 0 6b。其中沈積製程例如是化學氣相 沈積,其反應氣體端視所沈積之材料而定,而所沈積的材 料3 0 6 b與以沈積之材料3 〇 6 a係為相同之材料。在此步驟 2 0 6中可以藉由沈積材料3 〇 6 b將材料3 〇 6 a的淺碟型開口 3 〇 8 補滿(如第4 D圖所示)。 接著,請同時參照第3圖以及第4E圖,進行步驟2 0 8, 此步,2 0 8係為再次進行研磨製程以移除材料3 〇 6 a、3 〇 6 b 直,薄膜302的表面裸露出來,而保留下位於開口3〇4内之 3 0 6 c ’其中研磨製程例如是化學機械研磨製程。由於 f二驟2 0 8中,其材料3 0 6b係沈積於淺碟型開口 3 0 8中,此 型開σ 3 0 8比步驟2 0 0中的開口 3 0 4小很多,因此在進 之化學機械研磨時’其研磨接觸面之受力不均 1 問題可以獲得解決’所以可以達到完全平坦化的效 果(如第4E圖所示)。Then, referring to FIG. 3 and FIG. 4D at the same time, perform step 206. This step 206 is to perform a deposition process again to continue depositing material 3 6b on the remaining material 3 06 a. The deposition process is, for example, chemical vapor deposition, and the reaction gas end depends on the deposited material, and the deposited material 3 0 6 b is the same material as the deposited material 3 06 a. In this step 206, the shallow dish-shaped opening 3 0 8 of the material 3 6 a can be filled by depositing the material 3 0 6 b (as shown in FIG. 4D). Next, please refer to FIG. 3 and FIG. 4E at the same time, and perform step 208. At this step, 208 is the grinding process again to remove the materials 3 〇 6 a, 〇 6 b, straight, the surface of the film 302 The bare part is exposed, and the 3 06 c 'located in the opening 300 is retained, wherein the polishing process is, for example, a chemical mechanical polishing process. Since f 2 in step 2 0 8, the material 3 0 6b is deposited in the shallow dish-shaped opening 3 0 8. This type of opening σ 3 0 8 is much smaller than the opening 3 0 4 in step 2 0 0. When chemical mechanical polishing is performed, 'the problem of uneven force on the polishing contact surface 1 can be solved', so the effect of complete planarization can be achieved (as shown in Figure 4E).

例中之f ’請繼續參照第1 2圖以及第4E圖’在一較佳實施 口 3 〇4’可以選擇性地進行步驟21〇,在步驟210中若位於開F ′ in the example, please continue to refer to FIG. 12 and FIG. 4E. In a preferred embodiment, port 3 〇 04 ′ can be selectively performed in step 21o.

1 0 6之if材料3〇6(:表面尚未完全平坦’則重複進行步驟 2 何料沈積與步驟2 〇 8研磨直到材料表面完全平坦。 1220769 _案號 92119805 五、發明說明(6) 月 曰 修正 因此由上可知,在本發明中進行至少二次的沈積與研 磨步驟,藉由重複的沈積與研磨將材料表面的淺碟型開口 逐漸縮小以降低習知研磨不均勻之情形,所以利用本發明 可以達到完全平坦化的效果。 除此之外,本發明之多次沈積與多次研磨步驟亦可應 用於具有多個開口之平坦化製程中,使得多個開口中的各 個開口其所填入之材料具有極佳的平坦性。當然,本發明 之平坦製程更適用於現今高積集度之平坦化製程。1 0 6 的 材料 3〇6 (: The surface is not completely flat yet, then repeat step 2 What material deposition and step 2 08 grinding until the surface of the material is completely flat. 1220769 _ Case No. 92119805 5. Description of the invention (6) The correction is therefore known from the above. In the present invention, at least two deposition and grinding steps are performed. The shallow dish-shaped opening on the surface of the material is gradually reduced by repeated deposition and grinding to reduce the conventional grinding unevenness. The invention can achieve the effect of complete planarization. In addition, the multiple deposition and multiple polishing steps of the present invention can also be applied to a planarization process with multiple openings, so that each of the multiple openings is filled. The material has excellent flatness. Of course, the flattening process of the present invention is more suitable for today's high-leveling flattening processes.

雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍内,當可作些許之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

11292twf1.ptc 第12頁 1220769 案號 92119805 年月曰 修正 圖式簡單說明 第1 A圖到第1 D圖是習知一種金屬鑲嵌製程的流程剖面 不意圖, 第2圖是習知一種利用化學機械研磨法所得之結構剖 面示意圖; 第3圖是依照本發明一較佳實施例的一種平坦化之製 程流程圖;以及 . 第4 A圖至第4 E圖是第3圖的一種平坦化之流程剖面示 意圖。 . 圖式標記說明 1 00、3 0 0 :基底 1 02、102a :介電層 104 、 304 、 308 :開口 106、106a :金屬層 3 0 2 :薄膜 3 0 6、3 0 6 a、3 0 6 b、3 0 6 c :材料11292twf1.ptc Page 12 1220769 Case No. 92119805 Revised diagrams Brief description Figures 1A to 1D are not intended to be used to understand the flow profile of a metal damascene process. Figure 2 is a conventional method using chemical machinery A schematic cross-sectional view of the structure obtained by the grinding method; FIG. 3 is a flowchart of a planarization process according to a preferred embodiment of the present invention; and FIG. 4A to FIG. 4E are a planarization process of FIG. Schematic cross-section. Explanation of the graphical symbols 1 00, 3 0 0: substrate 10 02, 102a: dielectric layers 104, 304, 308: openings 106, 106a: metal layer 3 0 2: thin film 3 0 6, 3 0 6 a, 3 0 6 b, 3 0 6 c: material

11292twfl.ptc 第13頁11292twfl.ptc Page 13

Claims (1)

1220769 六 皇9805 修正 申請專利範圍 1 · 一種平垣化製糕,包括· (a)提供一基底,該基底上已形成一薄膜, 形成有至少一胡口; 这'4膜 p拟士士 /土、瓜” ,…"、儿碌薄 匕开/或有至少一開口, (b )進行一沈積製輊,以沈積一材料覆蓋於該 ,並且填滿該開口; 膜 (C )進行—研磨製程,以移除部分之該材料, 下位於該開口内以及該薄膜上之該材料; 保留- (d )再次進行該沈積製程,以於保留下來 繼續沈積該材料;以及 /材枓上- (e )再次進行該研磨製程,以移除該材料 的表面裸露出來,而保留下位於該開口内之該材料^溥膜 ^如申^奮專利範圍第i項所述之平坦化製程/更 驟(f ) ’右在步驟()中,該開口內 t匕括 中 上 + 專利範圍第1項所述之平坦化製程,f ~ + 步=(f),若在步驟(e)中,該開口内之該材 更包泰 f平f,則重複進行步驟(d)至(e)直到該開口 ^ ^未 表面完全平坦。 4成网口内之該材 λ 如由士教士 … 表面元全平坦 沈積3製ί Π i利範圍第1項所述之平坦化製程 4 化學氣相沈積製程。 研磨製程係2 : 2圍第1項所述之平坦化製程 5如申括化學機械研磨製程。 .係選自!巧f圍第1項所述之平坦化製程 ;|屢材料、一逡μ以. 其中驾 其中驾 材料係選自—介電材& 3 —— 〇 6 ·如申凊專利範導體材料係包括_ 2 Ϊ C。所述之平坦化製程,其中 _ · N衣杜,其t 導體材料與一半導體材料^ 12207691220769 Six Emperor 9805 Amends the scope of the patent application1. A Pingyuanhua cake, including: (a) providing a substrate, a film has been formed on the substrate, and at least a hukou is formed; , 瓜 ",… ", Erlu thin dagger open / or have at least one opening, (b) perform a deposition system, deposit a material to cover it, and fill the opening; film (C)-grinding Process to remove a portion of the material, the material located in the opening and on the film; reserve-(d) perform the deposition process again to continue depositing the material while remaining; and / on the material-- e) The grinding process is performed again to remove the exposed surface of the material, and the material located in the opening is retained. The flattening process as described in item i of the patent scope of the patent application / more (F) 'Right in step (), the opening t is in the upper and middle + flattening process described in item 1 of the patent scope, f ~ + step = (f), if in step (e), the If the material in the opening is more stable, repeat steps (d) to (e) until the opening The surface ^ ^ is not completely flat. The material λ in the net mouth is made by a priest ... The surface is completely flat deposited 3 The flattening process 4 described in item 1 of the scope of the chemical process 4 The chemical vapor deposition process. Grinding Process 2: The flattening process 5 described in item 1 of 2 is described in the chemical mechanical polishing process.. It is selected from the flattening process described in item 1 of Qiao F ;; The driving material is selected from the group consisting of -dielectric material & 3-〇6 · The conductor material of the patented patent includes _ 2 Ϊ C. The flattening process described above, where _ t Conductor material and a semiconductor material ^ 1220769 11292twf1.ptc 第15頁11292twf1.ptc Page 15
TW92119805A 2003-07-21 2003-07-21 Planarization process TWI220769B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW92119805A TWI220769B (en) 2003-07-21 2003-07-21 Planarization process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW92119805A TWI220769B (en) 2003-07-21 2003-07-21 Planarization process

Publications (2)

Publication Number Publication Date
TWI220769B true TWI220769B (en) 2004-09-01
TW200504852A TW200504852A (en) 2005-02-01

Family

ID=34114660

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92119805A TWI220769B (en) 2003-07-21 2003-07-21 Planarization process

Country Status (1)

Country Link
TW (1) TWI220769B (en)

Also Published As

Publication number Publication date
TW200504852A (en) 2005-02-01

Similar Documents

Publication Publication Date Title
US11552041B2 (en) Chemical mechanical polishing for hybrid bonding
TW441013B (en) Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US20110227189A1 (en) Dishing-Free Gap-Filling with Multiple CMPs
US6503827B1 (en) Method of reducing planarization defects
US6017803A (en) Method to prevent dishing in chemical mechanical polishing
JPH10178096A (en) Method for manufacturing aluminum contact
CN100403512C (en) Interconnect structure with low-resistance inlaid copper/barrier and method for manufacturing the same
TW516109B (en) A method of manufacturing semiconductor device and semiconductor device
TW201916255A (en) Method of manufacturing semiconductor device
US11374165B2 (en) Method of forming ultra-smooth bottom electrode surface for depositing magnetic tunnel junctions
JP2000208516A (en) Semiconductor device having multilayer wiring structure and manufacture thereof
TWI251898B (en) Damascene process for fabricating interconnect layers in an integrated circuit
TWI220769B (en) Planarization process
JP4573515B2 (en) Semiconductor die planarization method
US6069082A (en) Method to prevent dishing in damascene CMP process
TW525248B (en) Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication
JPH10326779A (en) Planarization method for semiconductor substrate
CN109887880A (en) A kind of semiconductor connection structure and preparation method thereof
TW479324B (en) Manufacturing method of dual-metal damascene structure
US6897121B2 (en) Method of removing HDP oxide deposition
JP2002305201A (en) Method of manufacturing semiconductor device
TW444340B (en) Method for forming self-aligned copper wire by using electroplating technique
TW530384B (en) Damascene method for forming spacer
KR20050032435A (en) Method of forming plug of semiconductor device
TW594925B (en) Method of fabricating metal interconnects and method of filling openings

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent