1220758 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內 容、實施方式及圖式簡單說明） 本發明是有關於一種記憶體，且更特別的是有關於一 種含有缺陷的記憶體。 在過去的十年裏，記憶體陣列之速度及容量已有了相 當大的改進。更特別的是，由於其在各領域之多種功能， 動態隨機記憶體（dynamic random access memory，DRAM) 已成爲積體電路工業之主要產品。動態隨機記憶體之技術 已由非同步型式，例如是快頁模式(fast page mode)，延伸 數據輸出(extended data output，EDO)，猝發型延伸數據輸 出(burst-EDO)，演進成今曰的同步型態，例如是同步動態 隨機記憶體（SDRAM)，Direct Rambus DRAM( Direct RDRAM)，雙資料速率(double data rate，DDR)同步動態隨 機 §己憶體（DDR-SDRAM)，以及 SynchLink SDRAM(SLDRAM)等。由於DRAM之單位位元成本降低， 每進入一個新的階段，其每一晶片的密度增加4倍。這主 要是由於其技術的改進而使得更多的記憶胞(memory cell) 可以封裝入同一晶粒中。因此，在DRAM進入一個新的 階段時，每一記憶體晶片的成本大約增加4倍。例如，一 16Mb的動態隨機記憶體之成本爲3元，而64Mb的動態 隨機記憶體之成本爲11元。 另外’每一個標準的記憶模組利用一數量的動態隨機 記億體已被廣泛地被應用於個人電腦中。早期之標準動態 6 7318pif2 (無劃底線） 1220758 隨記憶體包括單排式記憶模組（single-in-line memory module，SIMM)。近來，雙排列記憶模組（dual-in-line memory module，DIMM)以及小輪廓雙排歹[j記憶模組（Small-0utline DIMM)顯得越來越重要。 由於動態隨機記憶體之尺寸日趨增加，其成本相對地 增加。此外，當動態隨機記憶體應用於模組中且使用於其 應用中，其整體的價格變得更高。同時，動態隨機記憶體 製程中，有相當大數量的動態隨機記憶體具有缺陷，是眾 所皆知的事。因此，在生產複數個動態隨機記憶體之後， 40%的動態隨機記憶體可能具有缺陷。 因此，提供一 種系統及方法以使得具有缺陷的動態隨機記憶體得以使用 是必需的。該系統應該可以很簡單地應用，具有成本效益 以及低成本。本發明便提供了此一需要。 一種使具有至少一個缺陷的記憶體得以正確操作的方 法及系統在此揭露。首先，該方法及系統包括將記憶體中 的缺陷予以遮蓋，並對一控制晶片提供及接收一數據。 接著，揭露一使得具有缺陷之記憶體得以正確操作之 控制晶片。該控制晶片包括一解碼元件，以接收指令及位 址信號，以及一列位址比較器，以與該解碼元件溝通。該 控制晶片又包括一行位址比較器，以與該解碼元件以及一 用來接收來自該列位址比較器以及該行位址比較器之擊中 信號之擊中檢查元件溝通。該控制晶片又包括一暫存器， 用以接收來自擊中檢查元件之信號，以對一處理系統接收 及提供數據。經由本發明之系統及方法的應用，具有缺陷 7318piC (無劃底線） 7 之動態隨機記憶體得以被使用。因此，動態隨機記憶整體 的產能顯著地提高了。 圖式之簡單說明： 第la及lb係本發明之一系統的範例。 第2係一簡單方塊圖，繪示出本發明之一控制晶片。 第3a及3b圖係方塊圖，繪示出第2圖中之解碼元件。 第4圖係方塊圖，繪示出第2圖中之行位址比較器及 增量器。 第5圖係第2圖中之列位址比較器。 第6圖係第2圖中之擊中檢查方塊。 第7圖係繪示出動態隨機記憶體之寫入操作的時序表 示。 第8圖係繪示出動態隨機記憶體之讀取操作的時序表 示。 第9圖係繪示出動態隨機記憶體之具有啓動數據罩幕 指令(DQM)之寫入操作的時序表示。 第10圖係繪示出動態隨機記憶體之具有啓動數據罩 幕指令(DQM)之讀取操作的時序表示。 第11圖係具有位址擊中之寫入操件之控制晶片暫存 模式時序的表示。 第12圖係具有位址擊中之讀取操件之控制晶片暫存 模式時序的表示。 第13圖係具有位址擊中之寫入操件之控制晶片非暫 存模式時序的表示。 7318pif2 (無劃底線） 8 1220758 第14圖係具有位址擊中之讀取操件之控制晶片非暫 存模式時序的表示。 圖式之標記說明： 10 :本發明之系統 100 :控制晶片 102 :動態隨機記憶體 104 :數據匯流排 106 :數據罩幕指令 200 :解碼元件 300 :行位址比較器及增量器 400 :列位址比較器 500 :擊中檢查元件 600 :暫存器 202 :鎖存器 204 :解碼器 206 :系統時脈信號 302 :增量器 304 :行位址比較器 402 :鎖存器 404 :列位址比較器1220758 发明 Description of the invention (The description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the drawings.) The invention relates to a memory, and more particularly to a type of defect Memory. In the past decade, the speed and capacity of memory arrays have improved considerably. More specifically, due to its various functions in various fields, dynamic random access memory (DRAM) has become the main product of the integrated circuit industry. Dynamic random memory technology has evolved from non-synchronous types, such as fast page mode, extended data output (EDO), and burst-EDO. Synchronous type, such as synchronous dynamic random memory (SDRAM), Direct Rambus DRAM (Direct RDRAM), double data rate (DDR) synchronous dynamic random § memory (DDR-SDRAM), and SynchLink SDRAM ( SLDRAM) and so on. As the unit bit cost of DRAM is reduced, the density of each chip increases 4 times each time it enters a new stage. This is mainly due to the improvement of its technology so that more memory cells can be packed into the same die. Therefore, as DRAM enters a new stage, the cost of each memory chip increases approximately 4 times. For example, the cost of a 16Mb DRAM is 3 yuan, and the cost of a 64Mb DRAM is 11 yuan. In addition, each standard memory module uses a number of dynamic random memory devices, which have been widely used in personal computers. Early standard development 6 7318pif2 (Unlined) 1220758 The memory includes a single-in-line memory module (SIMM). Recently, dual-in-line memory modules (DIMMs) and small-profile dual-line memory modules (Small-0utline DIMMs) have become increasingly important. Due to the increasing size of dynamic random access memory, its cost has increased relatively. In addition, when DRAM is used in modules and used in its applications, its overall price becomes higher. At the same time, a considerable number of DRAMs in the DRAM manufacturing process are known to be defective. Therefore, after producing a plurality of dynamic random access memories, 40% of the dynamic random access memories may be defective. Therefore, it is necessary to provide a system and method for making use of defective dynamic random access memory. The system should be simple to apply, cost-effective and low-cost. The present invention provides this need. A method and system for correctly operating a memory having at least one defect is disclosed herein. First, the method and system include masking defects in the memory, and providing and receiving a data to a control chip. Next, a control chip is disclosed that enables defective memory to operate properly. The control chip includes a decoding element to receive instructions and address signals, and a column of address comparators to communicate with the decoding element. The control chip further includes a row of address comparators to communicate with the decoding element and a hit checking element for receiving hit signals from the column of address comparators and the row of address comparators. The control chip further includes a register for receiving a signal from the hit inspection component to receive and provide data to a processing system. Through the application of the system and method of the present invention, a dynamic random access memory with a defect of 7318 piC (underlined) 7 can be used. As a result, the overall capacity of dynamic random memory has increased significantly. Brief description of the drawings: The la and lb are examples of a system of the present invention. The second series is a simple block diagram showing a control chip of the present invention. Figures 3a and 3b are block diagrams showing the decoding elements in Figure 2. Figure 4 is a block diagram showing the row address comparator and the incrementer in Figure 2. Figure 5 is a column address comparator in Figure 2. Figure 6 is the hit check block in Figure 2. FIG. 7 is a timing chart showing a write operation of the dynamic random access memory. FIG. 8 is a timing chart showing the read operation of the DRAM. FIG. 9 is a timing diagram showing a write operation of a dynamic random access memory with a start data mask instruction (DQM). FIG. 10 is a timing diagram showing a read operation of a dynamic random access memory with a start data mask instruction (DQM). Fig. 11 is a timing diagram of a temporary storage mode of a control chip having an address hit write operation. Figure 12 shows the timing of the control chip temporary storage mode with the read operation of the address hit. Fig. 13 shows the timing of the non-temporary mode of the control chip with the write operation of the address hit. 7318pif2 (Underlined) 8 1220758 Figure 14 shows the timing of the non-temporary mode of the control chip with the read operation of the address hit. Explanation of the marks of the drawings: 10: System 100 of the present invention: Control chip 102: Dynamic random access memory 104: Data bus 106: Data mask instruction 200: Decoding element 300: Row address comparator and incrementer 400: Column address comparator 500: hit check element 600: register 202: latch 204: decoder 206: system clock signal 302: incrementer 304: row address comparator 402: latch 404: Column Address Comparator
406a_406d :歹[J 408 :多工器 502-506 :及閘 508 :暫存器 9 7318piC (無劃底線） 1220758 實施例 本發明是有關於記憶體，更特別的是，本發明是有關 於具有缺陷的記憶體。下列說明可使習知此技藝者能夠由 專利申請之內容及必要條件中得以製造及使用本發明。較 佳實施例之各種修改以及在此敘述的一般原理及特徵爲習 知此技藝者所顯而易見的。因此，本發明並不侷限於此一 實施例，其涵蓋在此敘述之原理及特徵的最廣範圍。 本發明使得一位元至位元取代一動態隨機記憶體102 中之缺陷，使得隨態隨機記憶胞102得以使用。爲更特別 描述本發明，下文特配合所附圖式作詳細說明。 第la圖係一簡單方塊圖，繪示出依據本發明，第一 實施例之系統10。本實施例有關一非暫存模式之實施例。 如圖所示，時脈、指令、位址及數據信號同時提供給一控 制晶片1〇〇及一動態隨機記憶102。此外，數據信號經由 數據匯流排，提供及傳送給控制晶片100及動態隨機記憶 體102。數據匯流排104依序地耦接至一中央處理單元 (CPU，未顯示於圖中），其提供指令及位址信號給動態隨 機記憶體102及控制晶片100。該控制晶片100亦可與其 他型式之系統，例如是繪圖或嵌入式動態隨機記憶體102 相耦接。DQM信號係由CPU提供給控制晶片100，修改 後之DQM信號則由控制晶片100提供給動態隨機記憶體 102。修改後之DQM信號提供動態隨機記憶體1〇2或控制 晶片1〇〇是否提供數據的指示。 第lb圖繪示出本發明之系統的第二實施例，其在一 7318pif2 (無劃底線） 10 1220758 高級DIMM模組中相當普遍，稱爲暫存模式。其元件與前 一實施例類似。然而在本實施例中，指令及位址信號會先 被鎖存在控制晶片100中，然後再被送至動態隨機記憶體 102 中。 藉著控制晶片100的使用，在動態隨機記億體102中 的缺陷可以被遮蓋，而控制晶片100接收及提供正確的數 據。更詳細的描述控制晶片1〇〇的操作，下列的說明將參 考附圖。 第2圖係第la及lb圖中，控制晶片100之簡單方塊 圖。控制晶片100包括一解碼元件200，其接收來自中央 處理單元之信號。該解碼元件200可實施指令解碼及時序 控制功能，並提供控制信號給其他的功能方塊。該解碼元 件200與一行位址比較器及增量元件300，以及一列位址 比較器400互相溝通。該行位址比較器及列位址比較器300 及400接收控制及位址信號，並提供信號給一由解碼元件 200控制之擊中檢查元件500，而在解碼元件200中之暫 存器600將會提供數據給外在系統（例如是一未繪示之 CPU)，或是由CPU接收數據。 第3a圖係一解碼元件200在非暫存模式下應用的方 塊圖。該解碼元件200包括一鎖存器202，用以接收來自 CPU之系統時脈信號、指令信號以及位址信號。該系統時 脈信號206亦提供給一解碼器204。鎖存之指令及位址信 號提供給解碼元件204。在第3b圖所繪示之暫存模式中， 該鎖存之指令及位址信號將會提供給動態隨機記憶體 7318pif2 (無劃底線） 1220758 102。鎖存器202的目的在於鎖存指令及位址信號，以供 同步設計下之解碼器204使用。而解碼器204的目的在於 實施指令解碼及解譯，以及提供時序控制給控制晶片1〇〇 之所有其他功能方塊。解碼器204提供控制信號給列位址 比較器400、行位址比較器300、撃中檢查元件500、以及 暫存器以確保正確的時序及控制晶片100之功能，並充分 配合同步動態隨機記憶體102之規格。 第4圖係行位址比較器及增量器300之方塊圖。該行 位址比較器及增量器300包括一增量器302，其接收來自 解碼器之位址信號及控制信號，以及系統時脈信號。位址 提供給行位址比較器304,將此位址與儲存之位址相比較。 行位址比較器304之輸出爲行位址擊中信號，其將提供給 擊中檢查方塊。儲存之位址係對應到具有缺陷之動態隨機 記憶胞102之位址。在製程之測試階段中，缺陷動態隨機 記憶胞102的位址可以儲存在例如是EEPROM或快閃記 憶體之晶片上（on-chip)或晶片外（off-chip)之非揮發記憶體 中。另一個儲存缺陷位址的方法是在控制晶片1〇〇中使用 一自行測試之迴路。在系統電源開啓階段中，該自行測試 迴路會測試動態隨記憶體102並將具有缺陷之動態隨機記 憶胞102的位址鎖存及儲存於一暫存器中。以上任一方法 中，具有缺陷之動態隨機記憶胞102之位址儲存皆爲直接 第5圖係一列位址比較器400。該列位址比較器400 藉著一鎖存器402接收位址。鎖存器402再提供給一位址 12 7318pif2 (無JiJ底線） 1220758 比較器404，在該位址比較器404中，位址與預先儲存的 位址相比較。在列位址比較之後，該資料必需存入與區塊 位址(bank address)相關之適當的列406a-406d中。該列乃 是基於來自解碼器204之信號。適當的信號再被送至一多 工器408。而基於區塊選擇信號，該多工器408將列擊中 信號送至擊中檢查區塊500中。該列擊中信號及行擊中信 號同時提供給擊中檢查區塊500,以建立適當的信號給暫 存器600。 第6圖繪示出擊中檢查區塊600的一個例子。該擊中 檢查區塊包括一第一及閘502 ,其接收列擊中信號及行擊 中信號。如果兩個信號同時有效，及閘將產生一最終撃中 信號。之後，最終擊中信號提供給及閘504及506。及閘 504是用來決定是否有一讀取擊中。及閘506是用來決定 是否有一寫入擊中。RD及WR控制信號同是來自解碼元 件200。根據這些信號是否爲啓動，並且依據時脈信號及 控制信號，暫存器508會對數據匯流排接收或提供適當的 數據。 於是，基於本發明之控制晶片100符合同步動態隨機 記憶體102之操作規格，其包括讀取（READ)、寫入 (WRITE)、循序猝發（sequential BURST)、交錯猝發 (interleave BURST)、猝發停止（BURST STOP)、電源下降 (POWER DOWN)、時脈暫停（CLOCK SUSPENSION)等命 令。下列時序圖解釋基本的同步動態隨機記憶體102操作 及控制晶片100如何在讀取及寫入時與同步動態隨機記億 13 7318pif2 (細底線） 1220758 體102交互作用。在這些例子中，爲了簡單了解，以猝發 長度爲4來作爲例子，習知此技藝者輕易看出，其他猝發 長度亦可以在此使用而仍在本發明之精神及範圍之內。在 此考慮兩種應用，第11圖及第12圖爲暫存模式，第13 及14圖爲非暫存模式(例如緩衝及非緩衝)模式操作。 第7圖係動態隨機記憶體在寫入操作的時序表示。 在本實施例中，列啓動指令在一時脈週期中由CPU 發出。同時，CPU亦發出一列位址。該列啓動指令及該列 位址將被動態隨機記憶體102所鎖存。兩個時脈週期之後， 一寫入指令及一行位址再由CPU發出。同時，有效數據 將在數據匯流排出現。之前鎖存的列位址及行位址將決定 在動態隨機記憶體102中之一唯一位址位置。由於此爲一 寫入操作，對應該單一位址位置之來自數據匯流排的數據 將被儲存於動態隨機記憶體102中。由於此時脈衝長度爲 4個操作，動態隨機記憶102將在下一時脈週期增加行位 址。如此，行位址之增加方式取決於是否其於循序或交錯 模式。行位址之增加的操作將會繼續，而相對應之數據將 出現，直到四個數據全部儲存在動態隨機記憶體102中爲 第8圖係動態隨機記憶體在讀取操作的時序表示。 在本實施例中，列啓動指令及列位址在一時脈週期中 由CPU發出。該位址被鎖存在動態隨機記憶體102中。 兩個時脈之後，讀取指令由該CPU發出。由於此爲一讀 取操作，根據CAS延遲時間（latency)，動態隨機記憶體102 7318pif2 (無劃底線) 14 1220758 將會將數據置於數據匯流排中。在讀取操作中會有CAS 延遲時間的問題。如果CAS延遲時間爲兩個時脈週期， 有效數據將會在接收到讀取指令的兩個時脈週期之後置於 數據匯流排上。如果CAS延遲時間爲三個時脈週期，有 效數據將會在接收到讀取指令的三個時脈週期之後置於數 據匯流排上。 第9圖係繪示出在寫入操作時，具有數據罩幕指令 (DQM)之動態隨機記憶體102的時序。 在寫入操作中，如果一數據罩幕指令(DQM)被啓動， 該動態隨機記憶體102將不會在此一時脈週期中，儲存在 數據匯流排上的數據。 第10圖係繪示出在讀取操作時，具有數據罩幕指令 (DQM)之動態隨機記憶體102的時序。 在讀取操作中，如果一數據罩幕指令(DQM)被啓動， 該動態隨機記憶體102將不會驅動，因此在接收到有效 DQM指令的兩個時脈週期之後，不會將數據置於數據匯 流排上。 第Π圖係繪示出具有位址擊中之寫入操作下，控制 晶片100在暫存模式之時序圖 在此一操作下，列啓動指令及列位址在一時脈週期 中，由CPU發出。該指令及位址被控制晶片1〇〇鎖存， 且送至動態隨機記憶體102中。該動態隨機記憶體102可 在下一時脈週期中將其接收及鎖存。兩個時脈週期之後， 該控制晶片100接收CPU發出之寫入指令及行位址。寫 7318pi£2 (無劃底線） 15 1220758 入指令及行位址將會再次鎖存而傳送到動態隨機記憶體 102。在控制晶片100中，該鎖存的列及行位址是用來與 預先儲存之位址做比較的，其中該預先儲存之位址是對應 動態隨機記憶體1 〇 2中缺陷的位址。在下一*時脈週期中， 行位址將會以在動態隨機記憶體102的方式被增量，此一 增量將會持續進行直到4個位址產生以後爲止。該比較則 在每一個新的位址產生之時完成。來自CPU之對應數據 將在適當時脈週期中，出現在數據匯流排上。如果在任一 時脈週期中，該比較產生一擊中信號，則表示該位址對應 在動態隨機記憶體102之一缺陷胞將會被儲存於該控制晶 片100中。基於本發明，該控制晶片100不會停止對動態 隨機記憶體102的寫入操作。 第12圖係繪示出具有位址擊中之讀取操作下，控制 晶片1〇〇在暫存模式之時序圖。 在此一操作下’列啓動指令及列位址在一時脈週期 中，由CPU發出。該指令及位址被控制晶片100鎖存， 且送至動態隨機記憶體102中。該讀取指令及行位址可被 視做與寫入操作相同。讀取操作會伴隨CAS延遲時間的 問題。如果在任一時脈週期中，該比較產生一擊中信號， 該控制晶片100會配合該CAS延遲時間，在該時脈週期 中，發出一 DQM信號106給動態隨機記憶體102。第12 圖繪示出CAS延遲時間等於兩個時脈週期。如第12圖所 示，在適當的時脈週期中，動態隨機記憶體102將依據接 收到的DQM信號106，不會提供任何數據於數據匯流排 7318pi£2 (無劃底線） 16 1220758 上，並且在正確的時脈週期中，控制晶片100提供正確的 數據。 第13圖繪示出在具有位址擊中之寫入操作下，控制 晶片100之非暫存模式的時序圖。 在此一操作下，列啓動指令及列位址在一時脈週期 中，由CPU發出。這些指令及位址在同一時脈邊緣被控 制晶片100及被動態隨機記憶體102鎖存。兩個時脈之後， 控制晶片100及動態隨機記憶體102同時接收來自CPU 之寫入指令及行位址。在控制晶片100中，鎖存的列及行 位址是用來與一預先儲存之位址相比較的，而該預先儲存 之位址是對應有缺陷動態隨機記憶胞之位址。在下一時脈 中，行位址將會被增量及比較。此一增量及比較將在4個 位址全部產生之後完成。來自CPU之相對的數據會在適 當的時脈週期中出現於數據匯流排上。如果任一時脈週期 中，該比較產生了一個擊中信號，數據將被儲存於控制晶 片100中。控制晶片100將不會停止動態隨機記憶體102 的寫入操作。 第14圖繪示出在具有位址擊中之讀取操作下，控制 晶片100之非暫存模式的時序圖。 在此一操作下，列啓動指令及列位址在一時脈週期 中，由CPU發出。這些指令及位址同時被控制晶片100 及被動態隨機記憶體102鎖存。此一讀取指令及行位址與 寫入操作中相同。如果任一時脈週期中，該比較產生了一 個擊中信號，控制晶片100則依據CAS延遲時間，在此 17 7318pif2 (無劃底線） 1220758 時脈週期中發出DQM信號106給動態隨機記憶體102。 第14圖繪示出三個時脈週期之一 CAS延遲時間。基於此 一規格’在接收到DQM信號時，動態隨機記憶體1〇2將 不會將任何數據置於匯流排中，而控制晶片100將在正確 的時脈週期中提供正確的數據。 利用本發明之系統及方法，具有缺陷之動態隨機記憶 體將可被使用，相對地，動態隨機記憶體之產能得以明顯 增加。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 18 7318pif2 (無劃底線）406a_406d: 歹 [J 408: Multiplexer 502-506: and Gate 508: Register 9 7318piC (Unlined) 1220758 Examples The present invention is related to memory, and more particularly, the present invention is related to having Defective memory. The following description will enable those skilled in the art to make and use the present invention from the contents and requirements of the patent application. Various modifications of the preferred embodiment and the general principles and features described herein will be apparent to those skilled in the art. Therefore, the present invention is not limited to this embodiment, which covers the widest scope of the principles and features described herein. The present invention enables bit-to-bit replacement of defects in a dynamic random access memory 102, and enables random random access cells 102 to be used. In order to describe the present invention more specifically, it is described in detail below with reference to the accompanying drawings. Figure la is a simple block diagram showing the system 10 according to the first embodiment of the present invention. This embodiment relates to an embodiment of a non-temporary storage mode. As shown, the clock, instruction, address and data signals are provided to a control chip 100 and a dynamic random access memory 102 at the same time. In addition, the data signals are provided and transmitted to the control chip 100 and the dynamic random access memory 102 via the data bus. The data bus 104 is sequentially coupled to a central processing unit (CPU, not shown in the figure), which provides instructions and address signals to the dynamic random memory 102 and the control chip 100. The control chip 100 can also be coupled with other types of systems, such as graphics or embedded dynamic random access memory 102. The DQM signal is provided by the CPU to the control chip 100, and the modified DQM signal is provided by the control chip 100 to the dynamic random access memory 102. The modified DQM signal provides an indication of whether the dynamic random access memory 102 or the control chip 100 provides data. Figure lb shows a second embodiment of the system of the present invention, which is quite common in a 7318pif2 (underlined) 10 1220758 advanced DIMM module, which is called a temporary storage mode. Its elements are similar to the previous embodiment. However, in this embodiment, the instruction and address signals are first latched in the control chip 100 and then sent to the dynamic random access memory 102. By using the control chip 100, defects in the dynamic random memory 102 can be covered, and the control chip 100 receives and provides correct data. The operation of the control chip 100 will be described in more detail. The following description will refer to the drawings. Fig. 2 is a simple block diagram of the control chip 100 in Figs. 1a and 1b. The control chip 100 includes a decoding element 200 which receives a signal from a central processing unit. The decoding element 200 can implement instruction decoding and timing control functions, and provide control signals to other function blocks. The decoding element 200 communicates with a row of address comparators and increment elements 300, and a column of address comparators 400. The row and column address comparators 300 and 400 receive control and address signals and provide signals to a hit check element 500 controlled by the decoding element 200, and a register 600 in the decoding element 200 Data will be provided to an external system (such as a CPU not shown) or received by the CPU. Figure 3a is a block diagram of a decoding element 200 applied in a non-temporary storage mode. The decoding element 200 includes a latch 202 for receiving system clock signals, instruction signals and address signals from the CPU. The system clock signal 206 is also provided to a decoder 204. The latched instruction and address signal are provided to the decoding element 204. In the temporary storage mode shown in Figure 3b, the latched instruction and address signal will be provided to the dynamic random memory 7318pif2 (without underline) 1220758 102. The purpose of the latch 202 is to latch the instruction and address signals for use by the decoder 204 in a synchronous design. The purpose of the decoder 204 is to implement instruction decoding and interpretation, and to provide timing control to all other functional blocks of the control chip 100. The decoder 204 provides control signals to the column address comparator 400, the row address comparator 300, the center check element 500, and the register to ensure correct timing and control the function of the chip 100, and fully cooperate with the synchronous dynamic random memory Body 102 specifications. FIG. 4 is a block diagram of the row address comparator and the incrementer 300. The row address comparator and incrementer 300 includes an incrementer 302, which receives an address signal and a control signal from the decoder, and a system clock signal. The address is provided to the row address comparator 304, which compares this address with the stored address. The output of the row address comparator 304 is a row address hit signal, which is provided to the hit check block. The stored address corresponds to the address of the defective dynamic random access memory cell 102. During the testing phase of the process, the address of the defect dynamic random access memory cell 102 can be stored in on-chip or off-chip non-volatile memory such as EEPROM or flash memory. Another method of storing defective addresses is to use a self-testing circuit in the control chip 100. During the system power-on phase, the self-test circuit tests the dynamic random memory 102 and latches and stores the address of the defective dynamic random memory cell 102 in a register. In any of the above methods, the address storage of the defective dynamic random access memory cell 102 is direct. Figure 5 is a row of address comparators 400. The column address comparator 400 receives an address via a latch 402. The latch 402 is then provided to a bit address 12 7318pif2 (without JiJ bottom line) 1220758 comparator 404, in which the address is compared with the pre-stored address. After the column address comparison, the data must be stored in the appropriate columns 406a-406d related to the bank address. The column is based on the signal from the decoder 204. The appropriate signal is then sent to a multiplexer 408. Based on the block selection signal, the multiplexer 408 sends a column hit signal to the hit check block 500. The column hit signal and the row hit signal are provided to the hit check block 500 at the same time to establish an appropriate signal to the register 600. FIG. 6 illustrates an example of the hit check block 600. The hit check block includes a first sum gate 502 that receives a column hit signal and a row hit signal. If both signals are active at the same time, the AND gate will generate a final hit signal. After that, the final hit signal is provided to the AND gates 504 and 506. The AND gate 504 is used to determine if there is a read hit. AND gate 506 is used to determine if a write hit was made. The RD and WR control signals are both from the decoding element 200. Depending on whether these signals are enabled, and according to the clock signal and the control signal, the register 508 receives or provides appropriate data to the data bus. Therefore, the control chip 100 based on the present invention complies with the operating specifications of the synchronous dynamic random access memory 102, which includes read (READ), write (WRITE), sequential burst (sequential burst), interleave burst (interleave burst), and burst stop (BURST STOP), POWER DOWN, CLOCK SUSPENSION and other commands. The following timing diagram explains the basic operation of the synchronous dynamic random access memory 102 and how the control chip 100 interacts with the synchronous dynamic random access memory 13 7318 pif2 (thin bottom line) 1220758 when reading and writing. In these examples, for the sake of simplicity, a burst length of 4 is taken as an example. Those skilled in the art can easily see that other burst lengths can also be used here and still be within the spirit and scope of the present invention. Two applications are considered here. Figures 11 and 12 show the temporary storage mode, and Figures 13 and 14 show the non-storage mode (such as buffered and unbuffered) operation. Figure 7 shows the timing of the write operation of the dynamic random access memory. In this embodiment, the column start instruction is issued by the CPU in one clock cycle. At the same time, the CPU also issues a list of addresses. The column start instruction and the column address will be latched by the dynamic random access memory 102. After two clock cycles, a write instruction and a row of addresses are issued by the CPU. At the same time, valid data will appear on the data bus. The previously latched column and row addresses will determine one of the unique address locations in the dynamic random access memory 102. Since this is a write operation, data from the data bus corresponding to a single address location will be stored in the dynamic random access memory 102. Since the pulse length is 4 operations at this time, the dynamic random access memory 102 will increase the row address in the next clock cycle. As such, the way the row address is increased depends on whether it is in sequential or interleaved mode. The operation of increasing the row address will continue, and the corresponding data will appear until all four data are stored in the dynamic random access memory 102. Figure 8 shows the timing of the read operation of the dynamic random access memory. In this embodiment, the column start command and the column address are issued by the CPU in one clock cycle. This address is latched in the dynamic random access memory 102. After two clocks, a read instruction is issued by the CPU. Because this is a read operation, according to the CAS latency, the dynamic random access memory 102 7318pif2 (underlined) 14 1220758 will place the data in the data bus. There is a problem with CAS latency during read operations. If the CAS delay time is two clock cycles, valid data will be placed on the data bus after two clock cycles of the read command. If the CAS delay time is three clock cycles, valid data will be placed on the data bus after three clock cycles of the read command. FIG. 9 is a timing diagram of the dynamic random access memory 102 having a data mask instruction (DQM) during a write operation. During a write operation, if a data mask command (DQM) is activated, the dynamic random access memory 102 will not store data on the data bus during this clock cycle. FIG. 10 is a timing diagram of the dynamic random access memory 102 having a data mask instruction (DQM) during a read operation. In a read operation, if a data mask instruction (DQM) is activated, the dynamic random access memory 102 will not be driven, so after two clock cycles of a valid DQM instruction are received, data will not be placed On the data bus. Figure Π shows the timing diagram of the control chip 100 in the temporary storage mode under a write operation with an address hit. In this operation, the column start command and the column address are issued by the CPU in a clock cycle. . The instruction and address are latched by the control chip 100 and sent to the dynamic random access memory 102. The dynamic random access memory 102 can receive and latch it in the next clock cycle. After two clock cycles, the control chip 100 receives a write instruction and a row address from the CPU. Write 7318pi £ 2 (Underlined) 15 1220758 The input instruction and the row address will be latched again and transferred to the dynamic random access memory 102. In the control chip 100, the latched row and row addresses are compared with pre-stored addresses, where the pre-stored addresses are addresses corresponding to defects in the dynamic random access memory 102. In the next * clock cycle, the row address will be incremented in the manner of the dynamic random access memory 102, and this increment will continue until the four addresses are generated. This comparison is done when each new address is generated. The corresponding data from the CPU will appear on the data bus in the appropriate clock cycle. If the comparison generates a hit signal in any clock cycle, it means that the address corresponding to a defective cell in the dynamic random access memory 102 will be stored in the control chip 100. Based on the present invention, the control chip 100 does not stop the writing operation to the dynamic random access memory 102. FIG. 12 is a timing chart of the control chip 100 in the temporary storage mode under a read operation with an address hit. In this operation, the column start instruction and the column address are issued by the CPU in one clock cycle. The instruction and address are latched by the control chip 100 and sent to the dynamic random access memory 102. The read instruction and the row address can be regarded as the same as the write operation. Read operations are accompanied by CAS latency issues. If the comparison generates a hit signal in any clock cycle, the control chip 100 will cooperate with the CAS delay time, and in this clock cycle, issue a DQM signal 106 to the dynamic random access memory 102. Figure 12 shows that the CAS delay time is equal to two clock cycles. As shown in Figure 12, in an appropriate clock cycle, the dynamic random access memory 102 will not provide any data on the data bus 7318pi £ 2 (without underline) 16 1220758 based on the received DQM signal 106. And in the correct clock cycle, the control chip 100 provides correct data. FIG. 13 shows a timing diagram of the non-transitory mode of the control chip 100 under a write operation with an address hit. In this operation, the column start instruction and the column address are issued by the CPU in one clock cycle. These instructions and addresses are controlled by the control chip 100 and latched by the dynamic random access memory 102 at the same clock edge. After two clocks, the control chip 100 and the dynamic random access memory 102 simultaneously receive the write command and the row address from the CPU. In the control chip 100, the latched row and row addresses are compared with a pre-stored address, and the pre-stored address corresponds to the address of the defective dynamic random memory cell. In the next clock, the row address will be incremented and compared. This increment and comparison will be completed after all 4 addresses have been generated. Relative data from the CPU will appear on the data bus in the appropriate clock cycle. If the comparison generates a hit signal in any clock cycle, the data will be stored in the control chip 100. The control chip 100 will not stop the writing operation of the dynamic random access memory 102. FIG. 14 is a timing diagram of the non-temporary mode of the control chip 100 under a read operation with an address hit. In this operation, the column start instruction and the column address are issued by the CPU in one clock cycle. These instructions and addresses are simultaneously latched by the control chip 100 and the dynamic random access memory 102. This read instruction and row address are the same as in a write operation. If in any clock cycle, the comparison generates a hit signal, the control chip 100 sends a DQM signal 106 to the dynamic random access memory 102 during the clock cycle based on the CAS delay time of 17 7318 pif2 (no underline) 1220758. Figure 14 shows the CAS delay time for one of the three clock cycles. Based on this specification, when receiving the DQM signal, the dynamic random access memory 102 will not put any data in the bus, and the control chip 100 will provide the correct data in the correct clock cycle. With the system and method of the present invention, a defective dynamic random access memory can be used. In contrast, the capacity of the dynamic random access memory can be significantly increased. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. 18 7318pif2 (Unlined)