TWI220350B - Equalizer with automatic correction and self-test - Google Patents

Abstract

The main object of the present invention is to provide a transmission line length estimation circuit with a continuous feedback control equalizer, which comprises: a DC bias circuit and a peak detection circuit for producing a DC voltage based on a cable length. The peak detection circuit is provided for a first signal in a length estimation stage and for a second signal in a phase locked loop control stage. An equalizer kernel circuit is provided to receive the first signal and produce the second signal. A transmission line length detection circuit is connected to the peak detection circuit to produce several first parameters for phase shift and amplitude loss based on the cable length. An inner pattern correction circuit is multiplexed to the first signal to produce several second parameters for correcting a locked loop. A feedback control circuit is connected to the equalizer kernel circuit to perform a continuous fine-tuning procedure based on the first parameter and second parameter.

Description

1220350 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to equalizers, especially to equalizers with automatic calibration and self-test. 5-2 Background of the Invention: In the field of data communication system (data communication system), it is generally known that when a transmitting device transmits an analog or digital signal to a transmission medium, such as a transmission line or cable, During the process of a receiving device, the received signal is distorted (distorted) due to the attenuation and phase delay of the signal during transmission in the transmission line. Take 1 OOBaseT Ethernet receiving device (which complies with ANSI / IEEE Std · 8 0 2.3u) as an example, it must be Ethernet-standard 1 25 million b 1 ts to receive one or three levels of analogy The signal ^ is analog slgnal at each level (MLT_3). However, for three-receiving devices, the bit error is related to the signal distortion of the signal transmitted on the $ Ethernet, and such signal distortion is different depending on the transmission. A signal can be Passing the length of the transmission line through different length transmission line network standards ANSI / IEEE St d · 8 0 2. 3u of an Ethernet "to the following Ethernet, in order to compensate for the signal lost in the transmission line caused by the same path Receiving device Before the Ethernet receiving device receives, it will use a true signal to repair the circuit of the receiver.

Page 4 1220350 V. Description of the invention (2) Only after it is transmitted to the Ethernet receiving device for reception; the so-called equalizer circuit can correct the amplitude loss and phase delay caused by transmission in the transmission line. The general equalizer circuit includes a compensation filter. The compensation filter can recover the amplitude and phase delay of the signal lost during transmission by the gain and phase shift controlled by the received control signal. The control signal is usually Provided from equalizer feedback. A general control circuit includes a non-linear element, such as a diode, and φ can receive feedback from the output of the compensation filter. These diodes are usually connected to a passive frequency selective network (passivefrequencyse 1 ectivenetwork); the role of this passive frequency selective network can make the response of the compensation filter follow the dynamic resistance of the diode (dynamicresistance) It changes in a proportional manner, so that accurate compensation for the amplitude loss and phase delay of a squall line can be obtained. The wide range of the RC time constant of the cable and the drastically changing diode resistance can prevent manufacturers from integrating such a control circuit into a monolithic die with another equalizer. The control circuit uses a series of weighted (summed) and summed (hi gh-pa ss) baseline functions. By adjusting the weighting values, these compensation circuits can be adjusted to control the equalizer very accurately, for different cable lengths.

1220350 V. Description of the invention (3) Compensate for the distortion caused. For the specific cable length, three fixed weighting items are designed using the resistance ratio combined with the output of the equalizer; this structure is based on the assumption that the variation of the RC time constant controlled by the variable resistance is derived from the cable length at RC The shifts in time delay are approximately equal. As long as the ratio of resistances is approximately equal throughout the process, such assumptions can be applied. Although such technology can meet the transmission of cables of several lengths, it is difficult for such weighting items to precisely control the compensation of cables of all lengths. Referring to the first figure, a general conventional equalizer i 0 0 includes an automatic gain control (AGC) circuit 130, an analog-to-digital (A / D) converter 140, and a digital adaptive equalizer (digital adaptive equalizer) 170 (ie equalizer core), time domain recovery circuit (timing recOvery) 150 and automatic gain control loop (automatic gain control 100P) 160. A received signal Vs is adjusted in intensity by an automatic gain control circuit 130, and then converted into a digital received signal by an analog-to-digital converter 1 40. The digital adaptive equalizer 1 adjusts the phase of the integer bit received signal to equalize the received signal Ve. Utilizing the automatic blood-supplying L-shaped circuit 1 3 0 and the analog-to-digital converter 1 4 0 in conjunction with the automatic gain control loop 160 and the time domain recovery circuit 1 50 to adjust the strength of different received signals' and the digital adaptive equalizer i 7 〇 is attenuation compensation for different frequencies. Traditional equalizers like this adjust the gain and phase of the received signal at different times. 1220350 V. Description of the invention (4) However, existing equalizers usually require an analog / digital converter (A DC) and a digital equalizer. In addition, when a signal is received, its gain and phase are adjusted in two different stages. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, the traditional equalizer has many shortcomings. The present invention mainly provides a circuit for estimating the transmission line length with a continuous feedback equalizer. The continuous feedback control circuit provides an equalizer for continuous automatic correction. Another object of the present invention is to provide an initialization circuit with self-test and automatic calibration. A self-test step with a pattern generator can reduce the problem of calibration difficulty. According to the above-mentioned object, the present invention provides a circuit for estimating a transmission line length with a continuous feedback control equalizer, which at least includes a DC bias circuit and a spike detection circuit for generating a line length based on a cable length. DC voltage. The spike detection circuit is used for the first signal during the estimated length phase and used for the second signal during the closed loop control phase. The equalizer core circuit is used for receiving the first signal and generating the second signal. A circuit for detecting the length of the transmission line is connected to the spike detection circuit for generating several first parameters for phase shift and amplitude loss according to the length of the cable; an internal pattern correction circuit multiplexes

1220350 V. Description of the invention (5) The multiplexed to the first signal is used to generate a number of second parameters for the correction of a closed loop; and a feedback control circuit is connected to the core circuit of the equalizer and used to The second parameter equalizer core circuit performs continuous fine tuning. 5-4 Detailed Description of the Invention: Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents. The main object of the present invention is to provide an equalizer with continuous automatic calibration and self-test, which at least includes a DC bias circuit and a spike detection circuit for generating a DC voltage according to a cable length. The spike detection circuit is used for the first signal during the estimated length phase and used for the second signal during the closed loop control phase. The equalizer core circuit is used for receiving the first signal and generating the second signal. A circuit for detecting the length of the transmission line is connected to the spike detection circuit for generating a number of first parameters for phase shift and amplitude loss according to the cable length; an internal pattern correction circuit multiplexes the first signal to The calibration of a latching loop generates a number of second parameters; a feedback control circuit is connected to the equalizer core circuit for performing continuous fine tuning on the equalizer core circuit according to the first parameter and the second parameter. A timing generator circuit is connected to the feedback control circuit,

I220350 V. Description of the invention (6) It is responsible for data recovery and correction of unlocking loop. The embodiment of the present invention will be described with reference to additional drawings. The second diagram is a block diagram of a data communication system, which is used to explain the circuit architecture of the present invention for estimating the length of a connection cable. The DC and baseline control 60 receives a differential signal Vc and VN from a transmission line (not shown in the figure), and outputs a signal vs. A direct current bias circuit may be included in the DC and baseline controller 60 to ensure that the differential signal "accepts a bias with VN to reach a common mode (c0mm〇I1 m〇de) DC voltage level (voltage level) The DC voltage level Vs is then transmitted to a spike detection block 6 2 during the length measurement phase, and is transmitted to the blocking control (c 1 〇se 1 ο ο pc ο ntr ο 1) phase. Equalizer core 70. In the present invention, the output of the equalizer core 70 can be transmitted to the spike detection block β2, which can generate better fine-tuning parameters to compensate the RC constant of the transmission line. In addition, the DC voltage The level V s is used to give an internal pattern and self-test circuit 6 6-bias during the correction of the lock-in loop. Furthermore, an estimated cable length block 6 8 for receiving the peak test block output is also used to generate Several parameters are given to a feedback control circuit 64. On the other hand, the control voltage of a voltage control oscillator (VC0) in the timing generator block 72 is connected to the feedback control circuit 64, which is used as Open circuit oop) correction. The feedback control circuit 64 cooperates with the control voltage of VC0 in the internal pattern and self-test circuit 6 6, the estimated cable length block 6 8 and the timing generator block (PLL) 72, which can generate a number of suitable Ginseng

1220350 V. Description of the invention (7) The number is used to adjust the characteristics of the equalizer core 70. With the cooperation of these circuit blocks, the equalizer that can estimate the transmission line length is sufficient for automatic calibration and self-test, so it can be regarded as a continuous feedback equalizer. Of course, a data decoding circuit 74 is connected to the outputs of the equalization core 70 and the spike detection block 62, and then outputs a M L T 3 format signal Ve. Secondly, the present invention provides a continuous feedback equalizer circuit 90 for automatic calibration and self-test. The third figure shows the flow chart of the automatic correction and self-test of the continuous feedback equalizer circuit 90. First, the output signal of the DC and base line controller 60 is initialized (step 20) to obtain several | preset values. The estimated cable length circuit receives the initialized signal to generate a number of adjustment parameters (step 21). The equalizer core adjusts its own characteristic parameters according to the adjustment parameters generated by the estimated cable length circuit (step 2 2). On the other hand, the PLL gain circuit of the timing generator circuit can be corrected for the unlocking loop (step 23), and a voltage generated by the volt-controlled oscillator in the PLL gain circuit can be used to adjust the gain of the equalizer ( Step 2 4). In addition, the internal pattern and the self-test circuit are responsible for the correction of the blocking circuit (step 25), so that the core circuit of the equalizer and the feedback control circuit can perform automatic correction and self-test (step 26). When the equalizer is under normal operating conditions (step 2 7), the limit of the circuit is adjusted by the blocking loop _ (step 2 8). If the gain of the equalizer is too small, the gain can be automatically increased, otherwise the gain is not maintained. change. The present invention uses the generated series of parameters to fine-tune the feedback control, and then sends it to the equalizer core.

Page 10 1220350 V. Description of the invention (8) The present invention provides many advantages. First, through a continuous feedback control circuit, any signal with discontinuous points can find a suitable curve. Secondly, since the equalization system of the present invention does not use an automatic gain controller, it can be applied to a longer navigation line length, for example, a length longer than 120 meters. Furthermore, this suitable curve (continuous curve) can be further adjusted by internal pattern correction. In addition, the additional self-test can reduce the difficulty of calibration, because it is difficult to obtain the calibration conversion curve during mass production. In the present invention, many gain curves that are a function of frequency can be generated by self-testing, thereby reducing the difficulty of calibration. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

1220350 Schematic Brief Description The first diagram is a block diagram of a conventional equalizer; the second diagram is a block diagram of an equalizer disclosed according to the present invention; and the third diagram is a schematic diagram of the automatic calibration and self-test process of the present invention . Symbols of main parts: 60 DC and baseline controller

6 2 Spike detection block 64 Feedback control circuit 66 Internal pattern and self-test circuit 68 Estimated cable length Block 70 Equalizer core 72 Timing generator block 7 4 Data decoding circuit 90 Continuous feedback equalizer circuit 100 etc. 13 0 Automatic gain control circuit

14 0 Analog-to-digital converter 15 0 Time-domain recovery circuit 160 Automatic gain control loop 170 Digital adaptive equalizer

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Claims (1)

1220350 VI. Scope of patent application 1 1. An estimated transmission line length circuit with a continuous feedback control equalizer. The estimated transmission line length circuit includes at least: a DC bias circuit and a spike detection circuit for detecting a cable. The DC voltage is generated by the length. The spike detection circuit is used for a first signal at a first time and used for a second signal at a second time. An equalizer core circuit is used to receive the first signal. And generate the second signal; a transmission line length detection circuit is connected to the spike detection circuit for generating a plurality of first parameters for phase shift and amplitude loss according to the cable length; an internal pattern correction circuit is multiplexed Multiplexed to the first signal to generate a plurality of second parameters for the correction of a closed loop; 彳 _ and a feedback control circuit connected to the core circuit of the chem. The second parameter is used to perform continuous finetuning on the equalizer core circuit. 2. The circuit for estimating the transmission line length according to item 1 of the scope of patent application, wherein the above feedback control circuit includes at least: a timing generator circuit connected to the feedback control circuit for data recovery and unlocking of the loop. Calibration; and a data decoder connected to the spike detection circuit and the core circuit of the adapter. Page 13 1220350 VI. Patent Application Range 3. If the estimated transmission line length circuit of item 1 of the patent application range, the above-mentioned internal pattern correction circuit further includes a self-test (se 1 ftest) for the core circuit of the adapter. . 4. The estimated transmission line length circuit as described in item 1 of the scope of the patent application, wherein the feedback control circuit described above further includes automatic correction (aut o-ca 1 i brat i on) for the core circuit of the adapter o 5. For example, the circuit for estimating the transmission line length in the first scope of the patent application, wherein the first time is the stage of estimating the transmission line length. φ 6. The circuit for estimating the transmission line length according to item 1 of the scope of the patent application, wherein the second time mentioned above is the closed loop control phase. 7. An equalizer with automatic calibration and self-test, the equalizer includes at least: a DC bias circuit and a spike detection circuit for generating a DC current voltage according to a cable length, the spike detection The circuit is used for a first signal at a first time and for a second signal at a second time; an equalizer core circuit is used to receive the first signal and generate the second signal of φ; a detection A transmission line length circuit connected to the spike detection circuit for generating a plurality of first parameters for phase shift and amplitude loss according to the cable length; Page 14 1220350 6. Scope of patent application: an internal pattern correction circuit is multiplexed to the first signal to generate a plurality of second parameters for the correction of a closed loop; a feedback control circuit is connected to the chemistries A core circuit for performing continuous fine tuning of the equalizer core circuit according to the first parameters and the second parameters; and a timing generator circuit connected to the feedback control circuit for responsible for data Recovery (datarec 0very) and correction of unlocking loop. 8. The equalizer according to item 7 of the scope of patent application, wherein the above feedback control circuit further includes automatic correction (aut ο-φ calibration) for the core circuit of the equalizer. The equalizer of the above item, wherein the above-mentioned internal pattern correction circuit further includes a self test responsible for the core circuit of the equalizer ° 10. For example, the equalizer of item 7 of the patent application scope, wherein The first time is the stage of estimating the transmission line length. 1 1. The equalizer according to item 7 of the scope of patent application, wherein the above-mentioned second time _ is a closed loop control stage. Page 15