US20100008414A1 - High-Speed Signaling Systems And Methods With Adaptable, Continuous-Time Equalization - Google Patents

High-Speed Signaling Systems And Methods With Adaptable, Continuous-Time Equalization Download PDF

Info

Publication number
US20100008414A1
US20100008414A1 US12522362 US52236208A US2010008414A1 US 20100008414 A1 US20100008414 A1 US 20100008414A1 US 12522362 US12522362 US 12522362 US 52236208 A US52236208 A US 52236208A US 2010008414 A1 US2010008414 A1 US 2010008414A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
equalizer
signal
data
error
samples
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US12522362
Other versions
US8934525B2 (en )
Inventor
Hae-Chang Lee
Brian S. Leibowitz
Jade M. Kizer
Thomas H. Greer
Akash Bansal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03159Arrangements for removing intersymbol interference operating in the frequency domain
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/10Means associated with receiver for limiting or suppressing noise or interference induced by transmission
    • H04B1/12Neutralising, balancing, or compensation arrangements
    • H04B1/123Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H04L25/0307Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure using blind adaptation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03878Line equalisers; line build-out devices
    • H04L25/03885Line equalisers; line build-out devices adaptive
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L2025/0335Arrangements for removing intersymbol interference characterised by the type of transmission
    • H04L2025/03356Baseband transmission
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L2025/03592Adaptation methods
    • H04L2025/03598Algorithms
    • H04L2025/03611Iterative algorithms
    • H04L2025/03636Algorithms using least mean square [LMS]

Abstract

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Description

    FIELD OF THE INVENTION
  • The present invention relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.
  • BACKGROUND
  • The performance of many digital systems is limited by the interconnection bandwidth within and between integrated circuit devices (ICs). High performance communication channels between ICs suffer from many effects that degrade signals. Primary among them is inter-symbol interference (ISI) from high frequency signal attenuation and reflections due to impedance discontinuities.
  • ISI becomes more pronounced at higher signaling rates, ultimately degrading signal quality to the point at which distinctions between originally transmitted signal levels may be lost. Some receivers cancel ISI using a decision-feedback equalizer (DFE). DFEs multiply each of N recently received symbols by respective tap coefficients, the resulting products representing the ISI attributable to the corresponding symbol. The sum of these products is subtracted from the received signal prior to sampling. The ISI associated with the prior data is thereby reduced or eliminated.
  • In very high-speed systems it can be difficult to resolve the most recent data bit or bits in time to calculate their impact on the incoming symbol. Some receivers therefore ignore the impact of such symbols on the incoming signal, and consequently fail to correct for the ISI attributed to those symbols. Other receivers employ partial response DFEs (PrDFEs) that obtain multiple samples of the incoming data using multiple correction coefficients, one for each of the possible values of the most recently received symbol or symbols. The correct sample is then selected after the most recently received symbol or symbols are resolved.
  • PrDFEs are effective, but require a separate subtraction and sampling path for each possible value of the most recently received symbol or, in the case of multiple symbols (multi-symbol PrDFE), a separate computational path for each possible combination of the multiple symbol values. This results in e.g. 2M paths in a binary PrDFE system that considers M prior symbols. The additional paths occupy area, require power, and slow signal rates by increasing the input capacitance of the receiver. There is therefore a need for power and area-efficient receivers capable of filtering incoming signals to cancel ISI from the most recently received symbol or symbols.
  • BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 depicts a receiver 100, in accordance with one embodiment, that receives information from a transmitter (not shown) via a high-speed communication channel 105.
  • FIG. 2 depicts adaptation engine 135 in accordance with one embodiment.
  • FIG. 3 details an embodiment of a tap-value generator 205 of FIG. 2 that generates a tap value using a sign-sign, least-mean-squared (LMS) algorithm.
  • FIGS. 4A-4D are waveform diagrams illustrating how tap-value generator 205 generates the values for taps α0 (AGCadj) and α1 (EQadj) in accordance with one embodiment.
  • FIG. 5 depicts three eye diagrams 500, 505, and 510 that illustrate the impact on an incoming signal Veq′ of adjusting signals AGCadj and EQadj.
  • FIG. 6 schematically depicts equalizer 120 of FIG. 1 in accordance with one embodiment.
  • FIG. 7 details an embodiment of variable capacitor 645 of FIG. 6.
  • FIG. 8 schematically depicts a bias-voltage generator 800 for use with equalizer 120 of FIG. 6.
  • DETAILED DESCRIPTION
  • FIG. 1 depicts a receiver 100, in accordance with one embodiment, that receives information from a transmitter (not shown) via a high-speed communication channel 105. In one embodiment, receiver 100 is instantiated on an integrated-circuit (IC) device and channel 105 provides differential signals RN and RP to a like-named differential input port of receiver 100 via a pair of pads 110. Channel 105 is AC coupled and includes a termination element 115 in this example. In other embodiments channel 105 is e.g. DC coupled, single ended, or optical. In embodiments adapted to communicate over optical channels, receiver 100 may include an integrated optical-to-electrical converter. Receiver 100 includes an analog, continuous-time equalizer 120, a decision-feedback equalizer (DFE) 125, data and error sampling logic 130, and an equalization-adaptation engine 135.
  • Equalizer 120 equalizes differential data signal RP/RN, conveyed from channel 105 to an input port of equalizer 120, to produce an equalized signal Veq on a like-named output port. (As with other designations herein, Veq refers both to a signal and a corresponding node or port; whether a given designation refers to a signal or a circuit element will be clear from the context.) Receiver 100 corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for continuous-time equalizer 120 based upon a measure of the first-post-cursor ISI. In doing so, receiver 100 can eliminate the need to resolve the most recent data bit in time to calculate its impact on the incoming signal, and thus facilitate communication at higher speeds without the attendant complexity and power required by PrDFE-based receivers. Some embodiments may use PrDFE for subsequent filter taps or to complement the continuous-time equalizer.
  • Equalizer 120 amplifies signal RP/RN using a range of amplification factors, with higher frequency components typically being treated to higher amplification factors. Channel 105 will typically exhibit a low pass filter effect, in which case equalizer 120 may be used to compensate for attenuation of higher-frequency signal components. In some embodiments, the low-frequency gain of equalizer 120 may also be adjusted to compensate for broadband signal attenuation. Gain adjustments can be accomplished by frequency-selective amplification or attenuation, or a combination of amplification and attenuation. In general, the goal of equalization is to reduce or minimize the effects of ISI, so equalization is typically accomplished by adjusting one or more characteristics of a signal in a manner that mitigates the effects of ISI.
  • DFE 125 further equalizes signal Veq to produce a second equalized signal Veq′ for sampling logic 130. DFE 125 stores sequences of sampled data in a buffer 160 as post-tap data values. Though not shown, tap select logic may be included to enable selection of a subset of data values within buffer 160. Receive-side equalization taps can thus be selected to have latencies that match whatever ISI components are evident in channel 105. Each stored data value in buffer 160 after the initial latch is multiplied by a corresponding tap coefficient. The resulting products are summed and the total added to equalized signal Veq to produce the second equalized signal Veq′. In one embodiment clock signal DfeClk to DFE 125 is a recovered clock signal synchronized to the edges of the equalized signal as observed at the input of sampler 155. The DfeClk is phase offset from (e.g. the complement of) receive clock RClk. The error sampler can be timed to the edges of the equalized signal in other embodiments, as by tying the clock terminal of sampler 150 to an edge clock signal (not shown).
  • Amplifier 140 within sampling logic 130 compares signal Veq′ with a selected data level Dlev, outputting a signal indicative of a logic one (zero) if Veq′ is greater than (less than) level Dlev. Sampler 150 periodically captures the output from amplifier 140 on rising edges of a receive clock signal RClk to produce a series of error samples Errn. A second amplifier 145 compares signal Veq′ with a reference voltage Vr (e.g., zero volts), outputting a signal indicative of a logic one (zero) if Veq′ is greater than (less than) level Vr. Sampler 155 periodically captures the output from amplifier 145 on rising edges of receive clock signal RClk to produce a series of data samples Datan.
  • Adaptation engine 135 employs data and error samples Datan and Errn from sampling logic 130 to generate the tap values for equalizer 120 and DFE 125. In an embodiment in which equalizer 120 is adapted to provide both automatic gain control (AGC) to compensate for broadband gain and equalization to compensate for ISI, adaptation engine 135 generates measures of DC attenuation and one or more ISI values by comparing error signals Errn with data samples of various symbol latencies. Based upon these generated values, adaptation engine 135 issues low-frequency control signals LFadj and high-frequency control signals HFadj to a control port of equalizer 120, and thereby controls the low-frequency gain and the peaking response of equalizer 120. In other embodiments a single control signal can control multiple equalization parameters, including e.g. the low-frequency gain and the peaking response,
  • Four simplified frequency-response diagrams 165, 170, 175, and 180 in the lower portion of FIG. 1 depict the approximate effects of adjusting the low-frequency and high-frequency gain of equalizer 120 in one embodiment. As shown in diagram 165, increasing the value of signal LFadj tends to increase the gain of equalizer 120 at low frequencies. With reference to diagram 170, increasing the value of signal HFadj tends to decrease the peak response of equalizer 120 around a particular (high) frequency of interest. Diagram 175 shows how the broadband frequency response of equalizer 120 is adjusted by moving signals LFadj and HFadj together in opposite directions. Diagram 180 shows how the equalization frequency response of equalizer 120 is adjusted by moving signals LFadj and HFadj together in the same direction. Equalizer 120 can equalize incoming signals by attenuating or amplifying some frequency components more than others, or by a combination of amplification and attenuation.
  • The LFadj signal from adaptation engine 135 adjusts the low-frequency gain of equalizer 120. The HFadj signal from adaptation engine 135, adjusts the peaking response of equalizer 120. Signals LFadj and HFadj are combinations of the α[1:0] signals that indicate the broadband gain (AGCadj) and equalization emphasis (EQadj) desired. The remaining adjustment signals α[N:2] are measures of the remaining ISI attributes due to the prior data symbols stored within buffer 160.
  • FIG. 2 depicts adaptation engine 135 in accordance with one embodiment. Adaptation engine 135 includes a series of synchronous storage elements 200 and tap-value generators 205 that together generate, from data and error samples Datan and Errn tap values α[1:0] for equalizer 120 and α[N:2] for DFE 125. The data and error samples are received on respective input ports, while the α values are conveyed to equalizer 120 and DFE 125 via the corresponding adaptation-engine output ports. Tap-value generators 205 each compare incoming error signals Errn with either a current data sample Datan or one of N−1 prior data samples to compute tap values α[N:0]. Element 210 shows the arithmetic logic utilized to generate LFadj and HFadj signals from AGCadj and EQadj (α[1:0]). Increasing the value of signal HFadj decreases the peaking response of equalizer 120 in this embodiment.
  • FIG. 3 details an embodiment of a tap-value generator 205 of FIG. 2 that generates a tap value using a sign-sign, least-mean-squared (LMS) algorithm. Generator 205 includes an XOR gate 300, logic 302 to convert the unsigned XOR output to a signed number, a multiplier 305 to scale the signed number by a constant μ, an adder 310, and a register 315. XOR gate 300 compares the corresponding data and error samples and presents its output to multiplier 305 via converter 302. The data and error samples represent the signs of the sampled values, so XOR gate 300 and converter 302 collectively have the effect of multiplying the signs and presenting the result to multiplier 305. Multiplier 305 multiplies the resulting product by a selected gain step size μ for the filter tap. Adder 310 adds the output from multiplier 305 to the current contents of register 315, which is then updated with the new count. Register 315 thus accumulates a count representative of the α value for the filter tap associated with the data samples of a particular latency. The α value for the filter tap is, in turn, representative of the ISI contribution of that filter tap to the present symbol. Ideally, each α value exactly offsets the respective ISI contribution. Perfection is difficult to obtain in practice, however, and the optimal tap values tend to vary with e.g. temperature and supply-voltage. Tap value generator 205 thus adaptively maintains representative α values that approximate the respective ISI contributions.
  • FIGS. 4A-4D are waveform diagrams illustrating how tap-value generator 205 generates the values for taps α0 (AGCadj) and α1 (EQadj) in accordance with one embodiment. Turning first to FIG. 4A, a signal trace 400 represents an incoming analog signal Veq′ over two symbol times tn−1 (the window for prior data Datan−1) and tn (the window for current data Datan), in a case where signal conveys a data value of 1 at each symbol time. In this embodiment, Vr is equal to zero. Broadband gain adjustments are based upon the current sampled data value Datan and the current sampled error value Errn. The sampled error is not shown; however, it can be seen that error sample Errn for FIG. 4A would be zero because the value of trace 400 is less than Dlev in the time interval for tn. In that case, the AGCadj is incremented to increase the broadband gain of equalizer 120. The same holds true for the example of FIG. 4C. In FIGS. 4B and 4D, however, the current value of Veq′ is greater than Dlev, indicating that the sign of Errn is one, in which case tap value AGCadj is decremented to reduce the broadband gain.
  • Returning to FIG. 4A, adjustments to EQadj are based upon the prior sampled data value Dn−1 and the current sampled error value Errn. As noted previously, error sample Errn for FIG. 4A is zero because the value of trace 400 is less than Dlev in the current time interval. Also evident in FIG. 4A, the value Veq′ for the prior sample time tn−1 is positive (i.e., Dn−1=1) because Veq′ is greater than reference voltage Vr (e.g., zero volts). In that case, the EQadj is incremented to simultaneously decrease the high-frequency and increase the low-frequency gain of equalizer 120. The high-frequency tap value EQadj is likewise incremented if the current error signal is a one and the prior data signal is a zero, as shown in FIG. 4D. On the other hand, EQadj is decremented, to simultaneously increase the high-frequency and decrease the low-frequency gain, if the current error sample has the same value as the prior data sample, conditions that are represented in FIGS. 4B and 4C.
  • The forgoing error comparisons are based upon the upper signal level defined by voltage Dlev and applied via amplifier 140. Adaptation engine 135 only updates the tap values α[N:0] based upon measurements that take place when the current data sample Datan is a logic one. Adaptation engine 135 therefore includes a data filter, not shown, to prevent updates when the current sample Datan is a logic zero. Other embodiments can include a second amplifier/sampler pair to generate error samples, such as by comparing the incoming signal Veq′ with the lower data level −Dlev, or the reference voltage to amplifier 140 can be varied over a number of values or ranges of values to facilitate additional testing and error-correction methods.
  • FIG. 5 depicts three eye diagrams 500, 505, and 510 that illustrate the impact on an incoming signal Veq′ of adjusting signals AGCadj and EQadj. Beginning with diagram 500, a signal eye 515 is of relatively low amplitude with respect to a desired data level Dlev. In this case, using the method described above in connection with FIGS. 4A-4D, the broadband gain of equalizer 120 may be increased to expand eye 515. With reference to diagram 505, the gain would continue to increase stepwise until eye 515 expanded such that signal level Dlev was in the center of the upper “fuzz” band 520. At the center of the fuzz band, the error sample (Errn) from sampling logic 130 would exhibit an equal likelihood of sampling a one or a zero when the current data Dn=1, thus there would be no further net change in AGCadj.
  • We next consider the impact of adjusting value EQadj. Assuming DFE 125 is doing a reasonable job of cancelling the ISI associated with the post-cursor values for taps two through N, the remaining ISI at Veq′ contributing to the width of fuzz band 520 is assumed to be largely a result of first post-cursor ISI. Using the method described above in connection with FIGS. 4A-4D, the equalizer gain of equalizer 120 would be increased or decreased as necessary to reduce the amplitude of fuzz band 520. The adjustment would continue stepwise until eye fuzz band 520 diminished in the manner depicted in diagram 510 of FIG. 5. Thereafter the EQadj, the α1 tap, would experience an equal likelihood of incrementing and decrementing.
  • FIG. 6 schematically depicts equalizer 120 of FIG. 1 in accordance with one embodiment. Equalizer 120 includes two nearly identical stages 600 and 605, the second of which is depicted as a black box for ease of illustration. Other embodiments include more or fewer stages, or other circuit topologies with similar frequency responses. Equalizer stage 600 includes a pair of differential input transistors 615 and 620 with respective loads 625 and 630. Source degeneration is provided by a resistor 635, a transistor 640, and a pair of variable capacitors 645 and 650. The capacitance provided by transistors 645 and 650 is in parallel with resistor 635 and transistor 640 from a differential small-signal perspective, so the net impedance between the sources of transistors 615 and 620 decreases with frequency. As a consequence, the gain of equalizer stage 600 increases with frequency. The resistance through transistor 640 can be adjusted to change the source-degeneration resistance, and thus to alter the low-frequency response of stage 600. The capacitance through capacitors 645 and 650 can be selected to alter the peaking response (high frequency gain) of stage 600.
  • In an alternative embodiment, source degeneration is provided by one or more metal-insulator-metal (MIM) capacitors connected in parallel with resistor 635. The MIM capacitors can be used instead of or in addition to capacitors 645 and 650. Other control mechanisms might also be used to alter the source-degeneration resistance, as by digitally switching in different sizes and combinations of resistors. In still other embodiments the DC gain adjustment is supported via a separate gain-control amplifier, or is omitted altogether.
  • A DAC 655 converts the digital equalization setting LFadj[3:0] from e.g. adaptation engine 135 of FIG. 1 to a gate voltage for transistor 640. The value of the equalization setting thus determines the resistance between the sources of transistors 615 and 620, and consequently the low frequency gain of equalizer stage 600. In one embodiment, the output voltage from DAC 655 increases as setting LFadj[3:0] increases from 0000 to 1111. This maximum output represents the lowest resistance between the sources of transistors 615 and 620, and consequently the highest gain setting for stage 600. The output voltage of a similar DAC (not shown) in stage 605 performs a similar function as DAC 655 in stage 600.
  • FIG. 7 details an embodiment of variable capacitor 645 of FIG. 6: capacitor 650 is identical. Capacitor 645 includes a number of capacitor-connected transistors 700 and respective select transistors 705 controlled by signal HFadj. The areas, and thus the capacitances, of transistors 700 can vary from one to the next (e.g., their areas can be binary coded) for added granularity, or can be thermometer coded to reduce adjustment glitches that might otherwise occur when switching between values. Increasing values of HFadj[3:0] represent decreasing amounts of capacitance in the degeneration network, and therefore decreasing high-frequency gain.
  • FIG. 8 schematically depicts a bias-voltage generator 800 for use with equalizer 120 of FIG. 6. A resistor 805 and transistors 810 and 815 form a half-circuit replica of equalizer stage 600, with the input common-mode voltage Vin_com applied to the gate of transistor 810. A feedback loop including an amplifier 820 and a pair of transistors 825 and 830 sets the voltage on the inverting (−) terminal of amplifier 820 equal to the voltage applied to the non-inverting (+) terminal. In an embodiment in which supply voltage Vdd is 1.2 volts, a resistor divider provides one-volt to the non-inverting terminal of amplifier 820. The resulting bias voltage Vbias to stages 600 and 605 then establishes a one-volt common-mode output voltage for those stages. In some embodiments, lower common-mode voltages are avoided to ensure that transistors 615 and 620 of FIG. 6 are always in saturation.
  • In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments.
  • A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or de-asserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. The output (input) of a signal driving (receiving) circuit is generically referred to as an output (input) port. Circuit elements are controlled by application of control signals to respective control ports.
  • An output of a process for designing an integrated circuit, or a portion of an integrated circuit, comprising one or more of the circuits described herein may be a computer-readable medium such as, for example, a magnetic tape or an optical or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing circuitry that may be physically instantiated as an integrated circuit or portion of an integrated circuit. Although various formats may be used for such encoding, these data structures are commonly written in Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), or Electronic Design Interchange Format (EDIF). Those of skill in the art of integrated circuit design can develop such data structures from schematic diagrams of the type detailed above and the corresponding descriptions and encode the data structures on computer readable medium. Those of skill in the art of integrated circuit fabrication can use such encoded data to fabricate integrated circuits comprising one or more of the circuits described herein.
  • While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example, the depicted embodiments are signal-data-rate (SDR) systems, but other embodiments may support e.g. double-data-rate (DDR) or quad-data-rate (QDR) operation instead of or in addition to SDR operation. Furthermore, the receivers described above employ current-mode signaling, but might also be adapted to employ voltage-mode schemes in which signals are conveyed as modulated voltages. Voltage thresholds may also be employed in the latter case by simply converting current signals to voltage for comparison with a voltage reference. In addition, embodiments of the invention may be adapted for use with multi-pulse-amplitude-modulated (multi-PAM) signals, and PrDFE taps can be inserted after equalizer 120. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or “coupling,” establishes some desired electrical communication between two or more circuit nodes, terminals, or ports. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Where U.S. law applies, only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.

Claims (24)

  1. 1. An integrated circuit to receive a series of symbols over a communication channel, the series of symbols including an incoming symbol and a most-recently-received symbol immediately preceding the incoming symbol, the integrated circuit comprising:
    a continuous-time equalizer having an equalizer input port coupled to the channel, an equalizer control port, and an equalizer output port, the continuous-time equalizer to equalize the series of symbols to produce an equalized signal on the equalizer output port wherein the continuous-time equalizer is adjustable over a range by application of a control signal representative of inter-symbol interference (ISI) attributable to the most-recently-received symbol on the equalizer control port;
    a data sampler having a data-sampler input port, coupled to the equalizer output port, and a data-sampler output port, the data sampler to periodically sample the equalized signal and thereby produce data samples;
    an error sampler having an error-sampler input port, coupled to the equalizer output port, and an error-sampler output port, the error sampler to periodically sample the equalized signal and thereby produce error samples;
    a decision-feedback equalizer (DFE) having a DFE input port coupled to the data-sampler output port, a DFE output port coupled to the data-sampler input port, and a DFE control port, wherein the DFE is adjustable by application of a set of tap values to the DFE control port, and wherein the tap values are representative of inter-symbol interference (ISI) attributable to symbols preceding the most-recently-received symbol in the series of symbols; and
    an adaptation engine having a first adaptation-engine input port coupled to the data-sampler output port, a second adaptation-engine input port coupled to the error-sampler output port, a first adaptation-engine output port coupled to the equalizer control port to issue the control signal, and a second adaptation-engine output port coupled to the DFE control port to issue the tap values.
  2. 2. The integrated circuit of claim 1, wherein none of the tap values to the DFE control port is attributable to the most-recently-received symbol.
  3. 3. The integrated circuit of claim 2, wherein the adaptation engine generates, from the data samples and the error samples, a second control signal representative of second post-cursor inter-symbol interference (ISI) for the incoming signal, and wherein the adaptation engine applies the tap value to the equalizer control port.
  4. 4. The integrated circuit of claim 1, wherein the adaptation engine generates, from the data samples and the error samples, an edge-time tap value representative of an edge time ISI component for the symbols, and wherein the adaptation engine applies the edge-time tap value to the equalizer control port.
  5. 5. The integrated circuit of claim 1, wherein the adaptation engine generates, from the data samples and the error samples, a second control signal representative of a DC level for the incoming signal and applies the second control signal to the control port.
  6. 6. The integrated circuit of claim 5, wherein the adaptation engine derives the second control signal using the first-mentioned control signal.
  7. 7-10. (canceled)
  8. 11. The integrated circuit of claim 1, wherein each of the data and error samples has a sign, and wherein the adaptation engine measures the sign of first post-cursor ISI for the equalized signal by multiplying the sign of one of the data samples by the sign of one of the error samples.
  9. 12. (canceled)
  10. 13. A method for sampling a series of symbols over a communication channel, the series of symbols including an incoming symbol and a most-recently-received symbol immediately preceding the incoming symbol, the method comprising:
    applying continuous-time equalization to the series of symbols to produce a first equalized signal;
    applying decision-feedback equalization to the it equalized signal to produce a second equalized signal;
    sampling the second equalized signal to produce a series of data samples, including an incoming sample of the incoming symbol and a most-recently-received sample of the most-recently-received symbol;
    sampling the second equalized signal to produce a series of error samples;
    generating a plurality of measures of post-cursor ISI, including a first measure of first-post-cursor ISI, from the data samples and the error samples;
    adjusting the continuous-time equalization based upon the measure of the first-post-cursor ISI; and
    adjusting the decision-feedback equalization based upon the measures of post-cursor ISI other than the first-post-cursor ISI.
  11. 14. The method of claim 13, further comprising generating a measure of DC amplitude of the first equalized signal using the data and error samples and adjusting the amplitude of the first equalized signal responsive to the measure of DC amplitude.
  12. 15-17. (canceled)
  13. 18. The method of claim 13, wherein generating the measure of first-post-cursor ISI comprises multiplying a sign of one of the data samples by a sign of one of the error samples.
  14. 19. The method of claim 18, wherein generating the measure of first-post-cursor ISI comprises applying one of the data samples and one of the error samples to a sign-sign LMS algorithm.
  15. 20. The method of claim 18, wherein each of the measures of post-cursor ISI are generated using a product of one of the data samples and one of the error samples.
  16. 21. The method of claim 20, wherein each product is a product of data-sample and error-sample signs.
  17. 22. An integrated circuit comprising:
    a continuous-time equalizer having an equalizer input port to receive a series of input symbols, an equalizer control port, and an equalizer output port, the continuous-time equalizer to equalize the series of input symbols to produce a first equalized signal;
    a decision-feedback equalizer (DFE) having a DFE input port coupled to the equalizer output port to receive the first equalized signal and a DFE output port, wherein the DFE equalizes the first equalized signal to provide a second equalized signal on the DFE output port;
    a sampler coupled to the DFE output port to sample the second equalized signal;
    means for measuring post-cursor ISI associated with the first equalized signal, including first-post-cursor ISI; and
    means fox adjusting the continuous-time equalizer based upon the measured first-post-cursor ISI and for adjusting the DFE based upon the post-cursor ISI other than the first-post-cursor ISI.
  18. 23. The integrated circuit of claim 22, further comprising sampling means for obtaining error samples from the second equalized signal.
  19. 24. The integrated circuit of claim 23, wherein the means for measuring post-cursor ISI adjusts the continuous-time equalizer and the DFE based upon the error and data samples.
  20. 25. (canceled)
  21. 26. An integrated circuit comprising:
    a. continuous-time equalizer to receive a signal and to equalize the signal to produce an equalized signal, wherein the continuous-time equalizer is adjustable in response to a control signal;
    b. a first sampler to periodically sample the equalized signal to produce data samples;
    c. a second sampler to sample the equalized signal and thereby produce error samples; and
    d. an adaptation engine to receive the data samples and error samples and to issue the control signal to the continuous-time equalizer.
  22. 27. The integrated circuit of claim 26, wherein the equalizer equalizes the signal using at least one of frequency-selective amplification and frequency-selective attenuation.
  23. 28. The integrated circuit of claim 26, wherein the error sampler periodically samples the equalized signal.
  24. 29. The integrated circuit of claim 26, wherein the equalizer is adjustable in response to a second control signal, and wherein the adaptation engine issues the second control signal.
US12522362 2007-01-08 2008-01-07 High-speed signaling systems and methods with adaptable, continuous-time equalization Active 2031-04-25 US8934525B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US87946107 true 2007-01-08 2007-01-08
PCT/US2008/000249 WO2008085964B1 (en) 2007-01-08 2008-01-07 Adaptive continuous-time line equalizer for correcting the first post-cursor isi
US12522362 US8934525B2 (en) 2007-01-08 2008-01-07 High-speed signaling systems and methods with adaptable, continuous-time equalization

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12522362 US8934525B2 (en) 2007-01-08 2008-01-07 High-speed signaling systems and methods with adaptable, continuous-time equalization

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/000249 A-371-Of-International WO2008085964B1 (en) 2007-01-08 2008-01-07 Adaptive continuous-time line equalizer for correcting the first post-cursor isi

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14552598 Continuation US9419663B2 (en) 2007-01-08 2014-11-25 High-speed signaling systems and methods with adaptable, continuous-time equalization

Publications (2)

Publication Number Publication Date
US20100008414A1 true true US20100008414A1 (en) 2010-01-14
US8934525B2 US8934525B2 (en) 2015-01-13

Family

ID=39609278

Family Applications (4)

Application Number Title Priority Date Filing Date
US12522362 Active 2031-04-25 US8934525B2 (en) 2007-01-08 2008-01-07 High-speed signaling systems and methods with adaptable, continuous-time equalization
US14552598 Active US9419663B2 (en) 2007-01-08 2014-11-25 High-speed signaling systems and methods with adaptable, continuous-time equalization
US15208332 Active US9860089B2 (en) 2007-01-08 2016-07-12 High-speed signaling systems and methods with adaptable, continuous-time equalization
US15827777 Pending US20180152327A1 (en) 2007-01-08 2017-11-30 High-speed signaling systems and methods with adaptable, continuous-time equalization

Family Applications After (3)

Application Number Title Priority Date Filing Date
US14552598 Active US9419663B2 (en) 2007-01-08 2014-11-25 High-speed signaling systems and methods with adaptable, continuous-time equalization
US15208332 Active US9860089B2 (en) 2007-01-08 2016-07-12 High-speed signaling systems and methods with adaptable, continuous-time equalization
US15827777 Pending US20180152327A1 (en) 2007-01-08 2017-11-30 High-speed signaling systems and methods with adaptable, continuous-time equalization

Country Status (4)

Country Link
US (4) US8934525B2 (en)
EP (3) EP2119156B1 (en)
CN (1) CN101595699A (en)
WO (1) WO2008085964B1 (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060188043A1 (en) * 2005-01-20 2006-08-24 Zerbe Jared L High-speed signaling systems with adaptable pre-emphasis and equalization
US20120057627A1 (en) * 2010-09-03 2012-03-08 Doris Po Ching Chan Adaptation circuitry and methods for decision feedback equalizers
US20120128053A1 (en) * 2010-11-19 2012-05-24 Kevin James Witt Method and apparatus for controlling a continuous time linear equalizer
US8665940B2 (en) 2006-04-27 2014-03-04 Rambus Inc. Adaptive equalization using correlation of edge samples with data patterns
US8705606B2 (en) 2004-05-21 2014-04-22 Rambus Inc. Methods and circuits for adaptive equalization
US8937990B2 (en) * 2012-08-31 2015-01-20 Fujitsu Limited Low-frequency equalizer circuit for a high-speed broadband signal
US9020022B1 (en) * 2013-08-02 2015-04-28 Pmc-Sierra Us, Inc. Analog finite impulse response adaptation method and apparatus
US9143371B1 (en) 2013-07-15 2015-09-22 Pmc-Sierra Us, Inc. Method for reducing jitter in receivers
US20150295736A1 (en) * 2014-04-11 2015-10-15 International Business Machines Corporation Continuous-time linear equalizer for high-speed receiving unit
US20150312066A1 (en) * 2014-04-24 2015-10-29 Jmicron Technology Corp. Equalizer control method and associated apparatus
US9319186B1 (en) * 2014-04-04 2016-04-19 Altera Corporation Receiver eye-monitor circuit and method
US9344145B2 (en) * 2014-05-07 2016-05-17 M31 Technology Corporation Method for transceiving signal based on information from equalizer of receiving unit and method for training equalizer
US9444588B1 (en) * 2015-06-15 2016-09-13 Pmc-Sierra Us, Inc. On-chip bathtub BER measurement for high-speed serdes diagnostics
US9509281B1 (en) 2015-08-03 2016-11-29 International Business Machines Corporation Peaking inductor array for peaking control unit of transceiver
US20170005841A1 (en) * 2015-07-02 2017-01-05 Hitachi, Ltd. Equalizer
US9755870B1 (en) * 2016-03-04 2017-09-05 Inphi Corporation Eye modulation for pulse-amplitude modulation communication systems
US10069656B1 (en) * 2017-02-24 2018-09-04 Cadence Design Systems, Inc. Method for preventing mis-equalizations in decision feedback equalizer based receivers for low loss channels

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5242649B2 (en) * 2010-09-09 2013-07-24 株式会社東芝 Decision feedback equalizer
CN102098248B (en) * 2010-12-24 2014-04-30 合肥昊特信息科技有限公司 High-speed transceiver with adaptive equalization capacity
CN102664842A (en) * 2012-03-08 2012-09-12 无锡华大国奇科技有限公司 System for reducing high-speed signal transmission intersymbol interference
US9231802B2 (en) 2012-12-26 2016-01-05 Nvidia Corporation Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample
US9762381B2 (en) 2013-07-03 2017-09-12 Nvidia Corporation Adaptation of crossing DFE tap weight
US9571311B2 (en) 2014-11-26 2017-02-14 Samsung Display Co., Ltd. Adaptive cyclic offset cancellation for the receiver front-end of high-speed serial links
CN104618280B (en) * 2015-02-02 2018-03-09 华为技术有限公司 A method of eliminating intersymbol interference decision feedback sequence, and one predictor
US10069658B2 (en) * 2015-09-23 2018-09-04 Intel Corporation Pulsed decision feedback equalization circuit
CN106301229A (en) * 2016-08-17 2017-01-04 灿芯半导体(上海)有限公司 Data receiving circuit
CN107657978B (en) * 2017-11-01 2018-09-21 睿力集成电路有限公司 Random access memory

Citations (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4187479A (en) * 1976-12-22 1980-02-05 Hitachi, Ltd. Variable equalizer
US4459698A (en) * 1981-03-20 1984-07-10 Hitachi, Ltd. Variable equalizer
US4639968A (en) * 1985-08-05 1987-02-03 Seaton Ssk Engineering Inc. Machine for cleaning castings
US4750155A (en) * 1985-09-19 1988-06-07 Xilinx, Incorporated 5-Transistor memory cell which can be reliably read and written
US4985900A (en) * 1986-01-18 1991-01-15 Hewlett-Packard Non-intrusive channel-impairment analyzer
US5293405A (en) * 1991-10-31 1994-03-08 International Business Machines Corp. Adaptive equalization and regeneration system
US5481564A (en) * 1990-07-20 1996-01-02 Fujitsu Limited Received data adjusting device
US5682112A (en) * 1994-05-18 1997-10-28 Nec Corporation Phase locked loop control apparatus
US5764695A (en) * 1996-11-26 1998-06-09 Lucent Technologies Inc. Adaptive line equalizer
US5844431A (en) * 1996-09-18 1998-12-01 Exar Corporation Low noise low power CMOS correlated double sampler
US5991339A (en) * 1998-01-16 1999-11-23 Intel Corporation Adaptive equalization using a minimum- jitter criterion
US5999056A (en) * 1998-06-30 1999-12-07 Philips Electronics North Amercia Corporation Variable gain amplifier using impedance network
US6192071B1 (en) * 1997-12-19 2001-02-20 3Com Corporation Detecting overequalization for adapting equalization and offset for data transmissions
US6225795B1 (en) * 1997-12-16 2001-05-01 Volterra Semiconductor Corporation Discrete-time sampling of data for use in switching regulations
US6265911B1 (en) * 1999-12-02 2001-07-24 Analog Devices, Inc. Sample and hold circuit having improved linearity
US6266379B1 (en) * 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6329874B1 (en) * 1998-09-11 2001-12-11 Intel Corporation Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode
US20020009167A1 (en) * 2000-05-22 2002-01-24 Ramin Farjad-Rad Linear data recovery phase detector
US6429692B1 (en) * 2001-06-19 2002-08-06 Octillion Communications, Inc. High speed data sampling with reduced metastability
US6496911B1 (en) * 1998-10-02 2002-12-17 International Business Machines Corporation Apparatus for memory bus tuning and methods therefor
US20030058962A1 (en) * 2001-08-07 2003-03-27 Baldwin Keith R. Intelligent control system and method for compensation application in a wireless communications system
US6570916B1 (en) * 1997-03-04 2003-05-27 Semiconductor Components Industries Llc Adaptive equalization circuit and method
US6624688B2 (en) * 2002-01-07 2003-09-23 Intel Corporation Filtering variable offset amplifer
US20040005001A1 (en) * 2002-07-02 2004-01-08 Jones Keith R. Gain adaptive equalizer
US20040008059A1 (en) * 2002-07-12 2004-01-15 Chen Fred F. Equalizing transceiver with reduced parasitic capacitance
US20040032813A1 (en) * 2002-06-05 2004-02-19 Samsung Electronics Co., Ltd. Optical disc having plurality of recording layers, recording method and reproducing method therefor
US20040052309A1 (en) * 2002-09-17 2004-03-18 Sung-Chiao Li Adaptive multi-modulus algorithm method for blind equalization
US6731683B1 (en) * 2000-10-02 2004-05-04 Lsi Logic Corporation Serial data communication receiver having adaptive equalization
US20040091028A1 (en) * 2002-06-25 2004-05-13 Aronson Lewis B. Transceiver module and integrated circuit with dual eye openers and equalizer
US20040136731A1 (en) * 2001-09-11 2004-07-15 Big Bear Networks, Inc. Method and apparatus for improved high-speed adaptive equalization
US20040153898A1 (en) * 2003-02-05 2004-08-05 Fujitsu Limited Method and system for providing error compensation to a signal using feedback control
US20040190661A1 (en) * 2003-03-26 2004-09-30 Quellan, Inc. Method and system for equalizing communication signals
US6812872B1 (en) * 2002-01-09 2004-11-02 Xilinx, Inc. Degenerative inductor-based gain equalization
US6819166B1 (en) * 2003-01-03 2004-11-16 Silicon Image, Inc. Continuous-time, low-frequency-gain/high-frequency-boosting joint adaptation equalizer and method
US20050047500A1 (en) * 2003-09-02 2005-03-03 Gupta Atul K. Precision adaptive equalizer
US6954495B2 (en) * 2000-04-06 2005-10-11 Nokia Corporation Optimization of channel equalizer
US20050271169A1 (en) * 2004-06-02 2005-12-08 Afshin Momtaz High speed receive equalizer architecture
US6992855B2 (en) * 2003-09-18 2006-01-31 Matsushita Electric Industrial Co., Ltd. Methods for limiting channel control values to thereby improve servo-demodulation robustness
US7016406B1 (en) * 2003-04-29 2006-03-21 Scintera Networks Adaptation structure and methods for analog continuous time equalizers
US7027503B2 (en) * 2002-06-04 2006-04-11 Qualcomm Incorporated Receiver with a decision feedback equalizer and a linear equalizer
US7030657B2 (en) * 2003-12-17 2006-04-18 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation
US7092472B2 (en) * 2003-09-16 2006-08-15 Rambus Inc. Data-level clock recovery
US20060188043A1 (en) * 2005-01-20 2006-08-24 Zerbe Jared L High-speed signaling systems with adaptable pre-emphasis and equalization
US7176721B2 (en) * 2003-12-17 2007-02-13 Rambus Inc. Signal receiver with data precessing function
US7177352B1 (en) * 2004-05-28 2007-02-13 Pmc-Sierra, Inc. Pre-cursor inter-symbol interference cancellation
US20070047636A1 (en) * 2005-08-30 2007-03-01 Lg Electronics Inc. High speed line equalizer and method thereof
US20070110199A1 (en) * 2005-11-15 2007-05-17 Afshin Momtaz Receive equalizer with adaptive loops
US7286597B2 (en) * 2000-04-28 2007-10-23 Broadcom Corporation Methods and systems for adaptive receiver equalization
US20070280341A1 (en) * 2006-05-30 2007-12-06 Fujitsu Limited System and Method for the Adjustment of Offset Compensation Applied to a Signal
US20080107165A1 (en) * 2006-11-07 2008-05-08 Alex Nicolescu Method and apparatus for layer 1 / layer 2 convergence declaration for an adaptive equalizer
US7400675B2 (en) * 2004-08-27 2008-07-15 Mindspeed Technologies, Inc. System and method for digital adaptive equalization with failure detection and recovery
US20080247452A1 (en) * 2007-04-09 2008-10-09 Synerchip Co., Ltd. Adaptive equalizer for use with clock and data recovery circuit of serial communication link
US20080260016A1 (en) * 2004-01-26 2008-10-23 Diablo Technologies Inc. Fully Adaptive Equalization for High Loss Communications Channels
US7496161B2 (en) * 2003-10-14 2009-02-24 Realtek Semiconductor Corporation Adaptive equalization system for a signal receiver
US20100027606A1 (en) * 2008-07-30 2010-02-04 Agere Systems, Inc. Adaptive equalization employing pattern recognition

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60176324A (en) 1984-02-22 1985-09-10 Pioneer Electronic Corp Waveform shaping circuit
US6608919B1 (en) * 1999-11-10 2003-08-19 Digimarc Corporation Method and apparatus for encoding paper with information
US7424053B2 (en) * 2001-08-02 2008-09-09 Agere Systems Inc. Channel equalization in data receivers
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7639736B2 (en) * 2004-05-21 2009-12-29 Rambus Inc. Adaptive receive-side equalization
US7519130B2 (en) * 2005-01-18 2009-04-14 International Business Machines Corporation Front end interface for data receiver
US7764732B2 (en) * 2006-05-08 2010-07-27 Applied Micro Circuits Corporation Adaptive error slicer and residual intersymbol interference estimator
US7782935B1 (en) * 2006-08-31 2010-08-24 Altera Corporation Half-rate DFE with duplicate path for high data-rate operation
US20080279271A1 (en) * 2006-09-01 2008-11-13 Philippe Hauviller Very High Speed Low Power Receiver Equalization System For Non-Return-To-Zero Transmission
US9014252B2 (en) * 2006-09-15 2015-04-21 Lsi Corporation Band-pass high-order analog filter backed hybrid receiver equalization

Patent Citations (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4187479A (en) * 1976-12-22 1980-02-05 Hitachi, Ltd. Variable equalizer
US4459698A (en) * 1981-03-20 1984-07-10 Hitachi, Ltd. Variable equalizer
US4639968A (en) * 1985-08-05 1987-02-03 Seaton Ssk Engineering Inc. Machine for cleaning castings
US4750155A (en) * 1985-09-19 1988-06-07 Xilinx, Incorporated 5-Transistor memory cell which can be reliably read and written
US4985900A (en) * 1986-01-18 1991-01-15 Hewlett-Packard Non-intrusive channel-impairment analyzer
US5481564A (en) * 1990-07-20 1996-01-02 Fujitsu Limited Received data adjusting device
US5293405A (en) * 1991-10-31 1994-03-08 International Business Machines Corp. Adaptive equalization and regeneration system
US5682112A (en) * 1994-05-18 1997-10-28 Nec Corporation Phase locked loop control apparatus
US5844431A (en) * 1996-09-18 1998-12-01 Exar Corporation Low noise low power CMOS correlated double sampler
US5764695A (en) * 1996-11-26 1998-06-09 Lucent Technologies Inc. Adaptive line equalizer
US6570916B1 (en) * 1997-03-04 2003-05-27 Semiconductor Components Industries Llc Adaptive equalization circuit and method
US6266379B1 (en) * 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6225795B1 (en) * 1997-12-16 2001-05-01 Volterra Semiconductor Corporation Discrete-time sampling of data for use in switching regulations
US6192071B1 (en) * 1997-12-19 2001-02-20 3Com Corporation Detecting overequalization for adapting equalization and offset for data transmissions
US5991339A (en) * 1998-01-16 1999-11-23 Intel Corporation Adaptive equalization using a minimum- jitter criterion
US5999056A (en) * 1998-06-30 1999-12-07 Philips Electronics North Amercia Corporation Variable gain amplifier using impedance network
US6329874B1 (en) * 1998-09-11 2001-12-11 Intel Corporation Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode
US6496911B1 (en) * 1998-10-02 2002-12-17 International Business Machines Corporation Apparatus for memory bus tuning and methods therefor
US6265911B1 (en) * 1999-12-02 2001-07-24 Analog Devices, Inc. Sample and hold circuit having improved linearity
US6954495B2 (en) * 2000-04-06 2005-10-11 Nokia Corporation Optimization of channel equalizer
US7286597B2 (en) * 2000-04-28 2007-10-23 Broadcom Corporation Methods and systems for adaptive receiver equalization
US20020009167A1 (en) * 2000-05-22 2002-01-24 Ramin Farjad-Rad Linear data recovery phase detector
US6731683B1 (en) * 2000-10-02 2004-05-04 Lsi Logic Corporation Serial data communication receiver having adaptive equalization
US6429692B1 (en) * 2001-06-19 2002-08-06 Octillion Communications, Inc. High speed data sampling with reduced metastability
US20030058962A1 (en) * 2001-08-07 2003-03-27 Baldwin Keith R. Intelligent control system and method for compensation application in a wireless communications system
US20040136731A1 (en) * 2001-09-11 2004-07-15 Big Bear Networks, Inc. Method and apparatus for improved high-speed adaptive equalization
US6624688B2 (en) * 2002-01-07 2003-09-23 Intel Corporation Filtering variable offset amplifer
US6812872B1 (en) * 2002-01-09 2004-11-02 Xilinx, Inc. Degenerative inductor-based gain equalization
US7027503B2 (en) * 2002-06-04 2006-04-11 Qualcomm Incorporated Receiver with a decision feedback equalizer and a linear equalizer
US20040032813A1 (en) * 2002-06-05 2004-02-19 Samsung Electronics Co., Ltd. Optical disc having plurality of recording layers, recording method and reproducing method therefor
US20040091028A1 (en) * 2002-06-25 2004-05-13 Aronson Lewis B. Transceiver module and integrated circuit with dual eye openers and equalizer
US20040005001A1 (en) * 2002-07-02 2004-01-08 Jones Keith R. Gain adaptive equalizer
US20040008059A1 (en) * 2002-07-12 2004-01-15 Chen Fred F. Equalizing transceiver with reduced parasitic capacitance
US20040052309A1 (en) * 2002-09-17 2004-03-18 Sung-Chiao Li Adaptive multi-modulus algorithm method for blind equalization
US6819166B1 (en) * 2003-01-03 2004-11-16 Silicon Image, Inc. Continuous-time, low-frequency-gain/high-frequency-boosting joint adaptation equalizer and method
US20040153898A1 (en) * 2003-02-05 2004-08-05 Fujitsu Limited Method and system for providing error compensation to a signal using feedback control
US20040190661A1 (en) * 2003-03-26 2004-09-30 Quellan, Inc. Method and system for equalizing communication signals
US7016406B1 (en) * 2003-04-29 2006-03-21 Scintera Networks Adaptation structure and methods for analog continuous time equalizers
US20050047500A1 (en) * 2003-09-02 2005-03-03 Gupta Atul K. Precision adaptive equalizer
US7092472B2 (en) * 2003-09-16 2006-08-15 Rambus Inc. Data-level clock recovery
US6992855B2 (en) * 2003-09-18 2006-01-31 Matsushita Electric Industrial Co., Ltd. Methods for limiting channel control values to thereby improve servo-demodulation robustness
US7496161B2 (en) * 2003-10-14 2009-02-24 Realtek Semiconductor Corporation Adaptive equalization system for a signal receiver
US7030657B2 (en) * 2003-12-17 2006-04-18 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation
US7715471B2 (en) * 2003-12-17 2010-05-11 Rambus, Inc. Signaling system with selectively-inhibited adaptive equalization
US7176721B2 (en) * 2003-12-17 2007-02-13 Rambus Inc. Signal receiver with data precessing function
US7233164B2 (en) * 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system
US7126378B2 (en) * 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US20080260016A1 (en) * 2004-01-26 2008-10-23 Diablo Technologies Inc. Fully Adaptive Equalization for High Loss Communications Channels
US7177352B1 (en) * 2004-05-28 2007-02-13 Pmc-Sierra, Inc. Pre-cursor inter-symbol interference cancellation
US20050271169A1 (en) * 2004-06-02 2005-12-08 Afshin Momtaz High speed receive equalizer architecture
US7400675B2 (en) * 2004-08-27 2008-07-15 Mindspeed Technologies, Inc. System and method for digital adaptive equalization with failure detection and recovery
US20060188043A1 (en) * 2005-01-20 2006-08-24 Zerbe Jared L High-speed signaling systems with adaptable pre-emphasis and equalization
US20070047636A1 (en) * 2005-08-30 2007-03-01 Lg Electronics Inc. High speed line equalizer and method thereof
US20070110199A1 (en) * 2005-11-15 2007-05-17 Afshin Momtaz Receive equalizer with adaptive loops
US20070280341A1 (en) * 2006-05-30 2007-12-06 Fujitsu Limited System and Method for the Adjustment of Offset Compensation Applied to a Signal
US20080107165A1 (en) * 2006-11-07 2008-05-08 Alex Nicolescu Method and apparatus for layer 1 / layer 2 convergence declaration for an adaptive equalizer
US20080247452A1 (en) * 2007-04-09 2008-10-09 Synerchip Co., Ltd. Adaptive equalizer for use with clock and data recovery circuit of serial communication link
US20100027606A1 (en) * 2008-07-30 2010-02-04 Agere Systems, Inc. Adaptive equalization employing pattern recognition

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8705606B2 (en) 2004-05-21 2014-04-22 Rambus Inc. Methods and circuits for adaptive equalization
US9544170B2 (en) 2004-05-21 2017-01-10 Rambus Inc. Methods and circuits for adaptive equalization
US9985806B2 (en) 2004-05-21 2018-05-29 Rambus Inc. Methods and circuits for adaptive equalization
US9112739B2 (en) 2004-05-21 2015-08-18 Rambus Inc. Methods and circuits for adaptive equalization
US10003484B2 (en) 2005-01-20 2018-06-19 Rambus Inc. High-speed signaling systems with adaptable pre-emphasis and equalization
US9148322B2 (en) 2005-01-20 2015-09-29 Rambus Inc. High-speed signaling systems with adaptable pre-emphasis and equalization
US9094238B2 (en) 2005-01-20 2015-07-28 Rambus Inc. High-speed signaling systems with adaptable pre-emphasis and equalization
US9742602B2 (en) 2005-01-20 2017-08-22 Rambus Inc. High-speed signaling systems with adaptable pre-emphasis and equalization
US8989249B2 (en) 2005-01-20 2015-03-24 Rambus Inc. High-speed signaling systems with adaptable pre-emphasis and equalization
US20060188043A1 (en) * 2005-01-20 2006-08-24 Zerbe Jared L High-speed signaling systems with adaptable pre-emphasis and equalization
US9137063B2 (en) 2005-01-20 2015-09-15 Rambus Inc. High-speed signaling systems with adaptable pre-emphasis and equalization
US9553745B2 (en) 2005-01-20 2017-01-24 Rambus Inc. High-speed signaling systems with adaptable pre-emphasis and equalization
US8665940B2 (en) 2006-04-27 2014-03-04 Rambus Inc. Adaptive equalization using correlation of edge samples with data patterns
US9565041B2 (en) 2006-04-27 2017-02-07 Rambus Inc. Adaptive equalization using correlation of edge samples with data patterns
US9900194B2 (en) 2006-04-27 2018-02-20 Rambus Inc. Adaptive equalization using correlation of edge samples with data patterns
US9054906B2 (en) 2006-04-27 2015-06-09 Rambus Inc. Adaptive equalization using correlation of edge samples with data patterns
US20120057627A1 (en) * 2010-09-03 2012-03-08 Doris Po Ching Chan Adaptation circuitry and methods for decision feedback equalizers
US8391350B2 (en) * 2010-09-03 2013-03-05 Altera Corporation Adaptation circuitry and methods for decision feedback equalizers
US20120128053A1 (en) * 2010-11-19 2012-05-24 Kevin James Witt Method and apparatus for controlling a continuous time linear equalizer
US8588288B2 (en) * 2010-11-19 2013-11-19 Maxim Integrated Products, Inc. Method and apparatus for controlling a continuous time linear equalizer
US8937990B2 (en) * 2012-08-31 2015-01-20 Fujitsu Limited Low-frequency equalizer circuit for a high-speed broadband signal
US9143371B1 (en) 2013-07-15 2015-09-22 Pmc-Sierra Us, Inc. Method for reducing jitter in receivers
US9426004B1 (en) 2013-07-15 2016-08-23 Microsemi Storage Solutions (U.S.), Inc. Method for reducing jitter in receivers
US9020022B1 (en) * 2013-08-02 2015-04-28 Pmc-Sierra Us, Inc. Analog finite impulse response adaptation method and apparatus
US9319186B1 (en) * 2014-04-04 2016-04-19 Altera Corporation Receiver eye-monitor circuit and method
US20150295736A1 (en) * 2014-04-11 2015-10-15 International Business Machines Corporation Continuous-time linear equalizer for high-speed receiving unit
US9288085B2 (en) * 2014-04-11 2016-03-15 International Business Machines Corporation Continuous-time linear equalizer for high-speed receiving unit
US20150312066A1 (en) * 2014-04-24 2015-10-29 Jmicron Technology Corp. Equalizer control method and associated apparatus
US9344145B2 (en) * 2014-05-07 2016-05-17 M31 Technology Corporation Method for transceiving signal based on information from equalizer of receiving unit and method for training equalizer
US9444588B1 (en) * 2015-06-15 2016-09-13 Pmc-Sierra Us, Inc. On-chip bathtub BER measurement for high-speed serdes diagnostics
US20170005841A1 (en) * 2015-07-02 2017-01-05 Hitachi, Ltd. Equalizer
US9722769B2 (en) * 2015-07-02 2017-08-01 Hitachi, Ltd. Equalizer
US9509281B1 (en) 2015-08-03 2016-11-29 International Business Machines Corporation Peaking inductor array for peaking control unit of transceiver
US9748927B2 (en) 2015-08-03 2017-08-29 International Business Machines Corporation Peaking inductor array for peaking control unit of transceiver
US10038468B2 (en) 2015-08-03 2018-07-31 International Business Machines Corporation Peaking inductor array for peaking control unit of transceiver
US9755870B1 (en) * 2016-03-04 2017-09-05 Inphi Corporation Eye modulation for pulse-amplitude modulation communication systems
US10069656B1 (en) * 2017-02-24 2018-09-04 Cadence Design Systems, Inc. Method for preventing mis-equalizations in decision feedback equalizer based receivers for low loss channels

Also Published As

Publication number Publication date Type
EP2498463A3 (en) 2013-09-11 application
EP2498463A2 (en) 2012-09-12 application
WO2008085964A3 (en) 2008-11-06 application
WO2008085964B1 (en) 2008-12-24 application
US20180152327A1 (en) 2018-05-31 application
US9860089B2 (en) 2018-01-02 grant
EP2119156A2 (en) 2009-11-18 application
US8934525B2 (en) 2015-01-13 grant
CN101595699A (en) 2009-12-02 application
US20150078430A1 (en) 2015-03-19 application
US20170005839A1 (en) 2017-01-05 application
US9419663B2 (en) 2016-08-16 grant
EP2119156B1 (en) 2015-03-11 grant
EP2498464A2 (en) 2012-09-12 application
WO2008085964A2 (en) 2008-07-17 application

Similar Documents

Publication Publication Date Title
US7099404B2 (en) Digital transmitter
US7233164B2 (en) Offset cancellation in a multi-level signaling system
US20040001540A1 (en) Method and apparatus for channel equalization
US20050271169A1 (en) High speed receive equalizer architecture
US5940441A (en) Integrated adaptive cable equalizer using a continuous-time filter
US6289045B1 (en) Training method in a time domain equalizer and a digital data transmission apparatus including an improved training apparatus
US20070195874A1 (en) Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data
US20050201454A1 (en) System and method for automatically calibrating two-tap and multi-tap equalization for a communications link
US20030053534A1 (en) Transmit amplitude independent adaptive equalizer
US20080304557A1 (en) Self-calibrating continuous-time equalization
US6563868B1 (en) Method and apparatus for adaptive equalization in the presence of large multipath echoes
US6823028B1 (en) Digitally controlled automatic gain control system for use in an analog front-end of a receiver
US8472513B2 (en) TX back channel adaptation algorithm
US7400675B2 (en) System and method for digital adaptive equalization with failure detection and recovery
US20060188043A1 (en) High-speed signaling systems with adaptable pre-emphasis and equalization
US6055269A (en) Adaptive equalization technique using twice sampled non-return to zero data
US20080247452A1 (en) Adaptive equalizer for use with clock and data recovery circuit of serial communication link
US20080212715A1 (en) Method and apparatus for baseline wander compensation in Ethernet application
US20050134306A1 (en) High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation
US20010043649A1 (en) Analog N-tap FIR receiver equalizer
US6570916B1 (en) Adaptive equalization circuit and method
US20030072380A1 (en) Method and apparatus for cross-talk mitigation through joint multiuser adaptive pre-coding
US6798828B1 (en) Full duplex gigabit-rate transceiver front-end and method operation
US20080106313A1 (en) High-speed cable with embedded power control
US6614842B1 (en) FIR filter architecture for 100Base-TX receiver

Legal Events

Date Code Title Description
AS Assignment

Owner name: RAMBUS INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, HAE-CHANG;LEIBOWITZ, BRIAN;KIZER, JADE;AND OTHERS;SIGNING DATES FROM 20070125 TO 20070207;REEL/FRAME:030814/0045

MAFP

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551)

Year of fee payment: 4