06424twf 1 .doc/006 修正日期92.7.18 玖、發明說明： 本發明是有關於一種積體電路工作模式自動設定的 方法與結構，且特別是有關於一種在形成複數個測試用焊 墊與對應測試電路，來以進行積體電路故障分析之方法與 結構。 近年來，半導體的製造技術不斷的進步，形成在晶 圓上的電晶體所佔的面積縮小，使得電晶體在晶圓上單位 面積的密度與數量增加，大幅度地增加積體電路的功能， 如動態隨機存取記憶體（Dynamic Random Access Memory， DR AM)的記憶容量增加。 例如一片純矽的晶圓經過多道複雜的製造程序，如 沈積、蝕刻、微影及摻雜等多項程序，才能在一片晶圓中 佈局出很多的積體電路晶片。此時，佈局完成的晶圓必須 經過切割與封裝等程序，才是市面上所看到的積體電路 (Integrated Circuit，1C)。晶圓在進行切割之前，必須標示 出晶圓上不良的積體電路晶片爲了良率提昇，所以要進行 積體電路的故障分析。 第1A圖繪示晶圓的俯視圖。在第1A圖中，晶圓10 如同上述要經過沈積、蝕刻、微影及摻雜等多項程序，才 能在晶圓10中佈局出每一個積體電路晶片12。當進行積 06424twf 1 .doc/006 修正曰期92.7.18 體電路的故障分析時，檢測出不良的積體電路晶片12 ,便 在積體電路晶片12做上記號，日後在進行封裝的程序時， 便不會將不良的積體電路晶片12進行封裝。 第1B圖繪示積體電路晶片的焊墊示意圖。如第1B 圖所示，當進行積體電路的故障分析時，是利用探針(Pr〇be) 在積體電路晶片14上的焊墊（或輸入接腳）16加入電源， 令積體電路在特定的工作模式進行故障分析。·在第1B圖 中，焊墊16的位置在積體電路晶片14的兩側。第ic圖 繪不另一種積體電路晶片的焊墊示意圖，在第1C圖中， 焊墊20的位置並排集中在積體電路晶片18的中央（此種排 列稱爲 Leadframe On Chip Center，LOC)。 當進行積體電路的故障分析時，積體電路在不同的 工作模式進行故障分析，所需要的輸入信號及電源的數目 就不问。如等待f旲式”(stancj by mode)需要VDD、VSS、/RAS 及/CAS等f目號’ ”輸入拽漏高準位”(丨叩加ieahge high)模式 需要 VDD、VSS、/RAS、/CAS、/WE、/OE、...等信號。如 此，積體電路在不同的工作模式進行故障分析，每需要〜 個輸入信號，意謂著需要一根探針，需要輸入信號的數自 越多’需要探針的數量就越多。對於積體電路晶片上焊熱 數目很多及LOC封裝的積體電路而言，數量眾多的探針 06424twf 1 .doc/006 修正曰期92.7.18 在面積非常小的積體電路晶片上之焊墊，進行積體電路的 故障分析實屬不易，容易造成故障分析之觀察的死角。 因此本發明係提供一種積體電路故障分析之方法與 結構，不需數量很多的探針即可進行積體電路的故障分 析，可以節省所需的探針數量，並且使積體電路的故障分 析之觀察沒有死角。 本發明係提供一種作爲故障分析之積體電路工作模 式自動設定的方法，其中積體電路包括複數個輸入接腳， 用以輸入不同特定電壓到輸入接腳，而使積體電路進入一 模式狀態。 本發明之方法包括下列步驟：首先，在積體電路上形 成一積體電路與一測試電路，並在積體電路上形成複數個 測試用焊墊；接著，根據測試用焊墊，對應設計複數個測 試電路於積體電路上，使測試電路連接至輸入接腳部分與 輸入接腳全部兩者擇一；以及最後加入一測試電源於任一 測試用焊墊，進而使對應之測試電路運作，而控制輸入不 同特定電壓到輸入接腳部分與輸入接腳全部兩者擇一，以 進行積體電路之不同模式，而作故障分析。 此外，本發明亦提供一種作爲故障分析之積體電路工 作模式自動設定的結構，適用於一積體電路之工作模式設 06424twfl .doc/006 修正日期92.7.18 定，其中積體電路包括複數個輸入接腳，用以輸入不同特 定電壓到輸入接腳，而使積體電路進入某一特定模式狀 育g 〇 J〇j\ 本發明之結構包括由複數個測試用焊墊以及複數個測 試電路所構成，其中測試用焊墊形成在積體電路上，而複 數個測試電路，對應測試用焊墊設計在積體電路上，並使 測試電路接至輸入接腳部分與輸久接腳全部兩者擇一。其 中，加入一測試電源於任一測試用焊墊，使對應之測試電 路導通，控制輸入不同特定電壓到輸入接腳部分與輸入接 腳全部兩者擇一，以進行積體電路之不同模式，而作故障 分析。 其中，上述測試用焊墊係爲三個，當三個測試用焊 墊分別以測試電源輸入時，分別進入一等待模式、一輸入 洩漏高準位模式以及一輸入洩漏低準位模式。 上述等待模式係使測試電源導通對應之測試電路，而造成 測試電源爲特定電壓，輸入到輸入接腳部分。而輸入洩漏 高準位模式係使測試電源導通對應之測試電路，而造成測 試電源爲特定電壓，輸入到輸入接腳全部。至於輸入洩漏 低準位模式係使測試電源導通對應之測試電路，一個輸入 接腳輸入測試電源，其他輸入接腳輸入特定電壓，特定電 06424twf 1 .doc/006 修正曰期92.7.18 壓係爲一接地電壓。此外，更包括提供一基本電源焊墊， 用以連接一接地電壓。 因此，本發明只要針對一特定模式，選擇其測試用焊 墊以一探針輸入一測試電源，再加上以一探針接觸到連接 接地電壓的基本電源焊墊，作爲基準電壓，就可以進行特 定工作模式的分析，因此不需要每個輸入接腳都使用一個 探針，而減少探針使用量以及可能所造成的誤接。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明 如下： 圖式之簡單說明： 第1A圖繪示晶圓的俯視圖； 第1B圖繪示習知之積體電路晶片的焊墊示意圖； 第1C圖繪示習知之另一種積體電路晶片的焊墊示意 圖； 第2圖繪示本發明之積體電路故障分析之流程圖； 第3A圖繪示本發明之積體電路晶片的焊墊示意圖； 以及 第3B圖繪示本發明之不同工作模式的測試電路圖。 標號說明： 06424twfl .doc/006 修正日期92.7.18 10 :晶圓06424twf 1 .doc / 006 Modified date 92.7.18 发明, description of the invention: The present invention relates to a method and structure for automatically setting the working mode of an integrated circuit, and in particular to a method for forming a plurality of test pads and corresponding Test circuit for the method and structure of integrated circuit fault analysis. In recent years, semiconductor manufacturing technology has continued to advance, and the area occupied by transistors formed on wafers has been reduced, which has increased the density and number of transistors per unit area on the wafer, greatly increasing the function of integrated circuits. For example, the memory capacity of Dynamic Random Access Memory (DR AM) increases. For example, a pure silicon wafer can undergo many complicated manufacturing processes, such as deposition, etching, lithography, and doping, to lay out many integrated circuit wafers in a wafer. At this time, the finished wafer must go through dicing and packaging processes before it can be seen as an integrated circuit (1C) on the market. Before the wafer is cut, the defective integrated circuit wafer on the wafer must be marked. In order to improve the yield, a failure analysis of the integrated circuit must be performed. Figure 1A shows a top view of the wafer. In FIG. 1A, the wafer 10 undergoes multiple processes such as deposition, etching, lithography, and doping, as described above, before each integrated circuit wafer 12 can be laid out in the wafer 10. When performing a failure analysis of the integrated circuit 24646twf 1 .doc / 006 date 92.7.18, if a defective integrated circuit chip 12 is detected, the integrated circuit chip 12 will be marked, and in the future during the packaging process Therefore, the defective integrated circuit chip 12 will not be packaged. FIG. 1B is a schematic view of a bonding pad of a chip of integrated circuit. As shown in FIG. 1B, when the failure analysis of the integrated circuit is performed, a power supply is added to the solder pad (or input pin) 16 on the integrated circuit chip 14 by using a probe (PrObe) to make the integrated circuit Perform fault analysis in specific operating modes. In FIG. 1B, the positions of the pads 16 are on both sides of the integrated circuit wafer 14. Figure ic shows a schematic diagram of another type of integrated circuit chip. In Figure 1C, the position of the bonding pad 20 is concentrated in the center of the integrated circuit chip 18 side by side (this arrangement is called Leadframe On Chip Center, LOC). . When the failure analysis of the integrated circuit is performed, the integrated circuit performs the failure analysis in different working modes, and the number of input signals and power required is not required. For example, the "stancj by mode" mode requires VDD, VSS, / RAS, and / CAS, etc. "" Input high leakage high level "(丨 叩 plus ieahge high) mode requires VDD, VSS, / RAS, / CAS, / WE, / OE, ... etc. In this way, the integrated circuit performs failure analysis in different operating modes, and each ~ ~ input signal means that a probe is needed, and the number of input signals is required. Since more, 'the more probes are needed. For integrated circuits with a large number of soldering heat on the integrated circuit chip and LOC package, a large number of probes 06424twf 1 .doc / 006 correction date 92.7.18 It is not easy to perform integrated circuit fault analysis on the solder pads on a very small integrated circuit chip, which is easy to cause the dead angle of the failure analysis observation. Therefore, the present invention provides a method and structure for integrated circuit fault analysis. The failure analysis of the integrated circuit can be performed without a large number of probes, which can save the number of probes required, and make the observation of the failure analysis of the integrated circuit without dead ends. The present invention provides a product for failure analysis. Circuit working mode An automatic setting method, in which the integrated circuit includes a plurality of input pins for inputting different specific voltages to the input pins, so that the integrated circuit enters a mode state. The method of the present invention includes the following steps: first, in the integrated circuit An integrated circuit and a test circuit are formed on the circuit, and a plurality of test pads are formed on the integrated circuit. Then, according to the test pads, a plurality of test circuits are correspondingly designed on the integrated circuit to connect the test circuit. To the input pin part and the input pin all; and finally add a test power to any test pad to make the corresponding test circuit operate, and control the input of different specific voltages to the input pin part and the input One of the two pins is selected to perform different modes of the integrated circuit for failure analysis. In addition, the invention also provides a structure for automatically setting the operating mode of the integrated circuit as a failure analysis, which is suitable for an integrated circuit The working mode is set to 06424twfl .doc / 006 and the revision date is 92.7.18. The integrated circuit includes multiple input pins for input. Different specific voltages are applied to the input pins, so that the integrated circuit enters a specific mode. 〇J〇j \ The structure of the invention includes a plurality of test pads and a plurality of test circuits. The pad is formed on the integrated circuit, and a plurality of test circuits are designed on the integrated circuit corresponding to the test pads, and the test circuit is connected to the input pin portion and the input long-term pin. A test power supply is connected to any of the test pads, and the corresponding test circuit is turned on. The control inputs different specific voltages to one of the input pin portion and the input pin to perform different modes of the integrated circuit and cause a failure. Among them, the above-mentioned test pads are three, and when the three test pads are input by the test power, they respectively enter a standby mode, an input leakage high-level mode, and an input leakage low-level mode. The above waiting mode is to make the test power supply turn on the corresponding test circuit, which causes the test power supply to be a specific voltage and input to the input pin. The input leakage high level mode causes the test power supply to conduct the corresponding test circuit, which causes the test power supply to be a specific voltage and all input to the input pins. As for the input leakage low level mode, the test power is turned on by the corresponding test circuit. One input pin is used to input the test power, and the other input pins are used to input a specific voltage. The specified voltage is 06424twf 1 .doc / 006. A ground voltage. In addition, it includes providing a basic power pad for connecting a ground voltage. Therefore, according to the present invention, as long as the test pad is selected for a specific mode, a probe is used to input a test power source, and a probe is used to contact a basic power pad connected to a ground voltage as a reference voltage. Analysis of specific operating modes, so there is no need to use a probe for each input pin, which reduces the use of probes and possible misconnections. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: A brief description of the drawings: FIG. 1A shows a crystal A circle top view; FIG. 1B shows a schematic diagram of a pad of a conventional integrated circuit wafer; FIG. 1C shows a schematic diagram of a pad of another conventional integrated circuit wafer; and FIG. 2 shows a failure of the integrated circuit of the present invention Analysis flow chart; FIG. 3A shows a schematic diagram of the bonding pads of the integrated circuit wafer of the present invention; and FIG. 3B shows a test circuit diagram of different working modes of the present invention. Reference number description: 06424twfl .doc / 006 Revision date 92.7.18 10: Wafer
12，14，18，30，40 :積體電路晶片 16，20 :焊墊 32，42 :焊墊 A 34，44 :焊墊 B 36，46 :焊墊 C 48，50，52，54，56，58，60，62，64，66，68，70 : 電晶體 實施例 第2圖繪示本發明之作爲故障分析之積體電路工作模 式自動設定的方法流程圖。晶圓經過沈積、蝕刻、微影及 摻雜等多項程序，才能在晶圓中形成每一個積體電路晶 片，並在此晶片形成一個測試電路（S22)。所形的積體電路 晶片如同第3A圖繪示本發明之積體電路晶片的焊墊示意 圖所示，在第 3A 圖中，以 ED〇(Extended Data Output) DRAM 爲例，本實施例之積體電路晶片30與習知相同之處包括 複數個輸入接腳31，用以輸入不同特定電壓到輸入接腳 31，而使積體電路30進入一模式狀態。但與習知積體電 路晶片所不同的是本實施例之積體電路晶片30上形成一 組測試用焊墊（如焊墊A 32、焊墊B 34及焊墊C 36)(S24)， 06424twfl.doc/006 修正曰期92.7.18 此組測試用的焊墊是作爲積體電路故障分析之用。焊墊A 32、焊墊B 34及焊墊C 36乃本實施例以三種不同的工作 模式之測試用焊墊爲例，可以應實際的需要設計其他不同 的工作模式之測試用焊墊，以做爲積體電路故障分析之 用。 第3 B圖繪示本發明之不同工作模式的測試電路圖。 在第3B圖中，在積體電路晶片40，針對上述三個測試用 焊墊，來分別設計三種不同工作模式的測試電路，來進行 不同工作模式的積體電路之故障分析。當要測試何種工作 模式的積體電路之故障分析時，只要將測試電源利用探針 加入相對應的測試用焊墊即可(S26)，可以減少探針使用的 數量來進行積體電路之故障分析。 如第3B圖所示，當EDO DRAM要做”等待模式，，的故 障分析時，在焊墊A 42以一探針接上測試電源（一般是5V 或3.3V)，並配合積體電路晶片40上基本電源焊墊（未繪示） 以另一探針連接一接地電壓，作爲基準電壓。在等待模式 下使連接焊墊A 42之測試電源導通對應之測試電路，包 括電晶體48、50、52，並使測試電源爲特定電壓輸入到積 體電路（即EDO DRAM)之部分輸入接腳VDD、/RAS、/CAS。 而進入到”等待模式”，因此，可以檢查EDO DRAM的等待 1220026 06424twfl .doc/006 修正日期92.7.18 電流（standby current) 〇 同理，當EDO DRAM要做”輸入洩漏高準位”的故障 分析時，在焊墊B 44以一探針接上測試電源，並配合積 體電路晶片40上基本電源焊墊（未繪不）以另一探針連接一^ 接地電壓，作爲基準電壓。在輸入洩漏高準位狀態下，使 連接焊墊B 44之測試電源導通對應之測試電路，包括電 晶體54 : 56、58、60、62等所有電晶體，並使測試電源爲 特定電壓，直接輸入到積體電路(即EDO DRAM)之全部輸 入接腳VDD、/RAS、/CAS、/WE../0E等所有接腳。而進 入到”輸入洩漏高準位模式”，因此，可以進行EDO DRAM 的輸入洩漏高準位分析。 同理，當EDO DRAM要做”輸入洩漏低準位”的故障分 析時，在焊墊C 44以一探針接上測試電源，並配合積體 電路晶片上基本電源焊墊（未繪示）以另一探針連接一接地 電壓，作爲基準電壓。在輸入洩漏低準位狀態下，使連接 焊墊C 44之測試電源導通對應之測試電路，包括電晶體 64、66、68、70等所有電晶體，使得一個輸入接腳VDD 輸入測試電源，其他輸入接腳如/RAS、/CAS、/0E輸入特 定電壓，例如特定電壓爲一接地電壓VSS。而進入_ ”輸 入洩漏低準位模式”，因此，可以進行EDO DRAM的输入 11 1220026 06424twfl.doc/006 修正曰期92.7.18 洩漏低準位分析。 根據上述不同的工作模式進行積體電路之故障分析 與結構，若檢測出不良的積體電路晶片，便在積體電路晶 片做上記號，日後在進行封裝的程序時，直接將不良的積 體電路晶片去除，避免不必要封裝成本的支出。 因此，本發明的優點係提供一種作爲故障分析之積 體電路工作模式自動設定的方法與結構，在形成數組測試 電路與測試用焊墊下，加入一測試電源於任一測試用焊 墊，進而使對應之該測試電路運作，控制輸入不同特定電 壓到輸入接腳部分或輸入接腳全部，加上一接地的基準焊 墊即可進行該積體電路之不同模式，而作故障分析。所以 只要針對兩個焊墊使用探針就可以進行，因此，可以減少 外部探針所需的數量，並且使積體電路的故障分析之觀察 沒有死角。 綜上所述，雖然本發明已以較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 1212, 14, 18, 30, 40: Integrated circuit wafer 16, 20: Pad 32, 42: Pad A 34, 44: Pad B 36, 46: Pad C 48, 50, 52, 54, 56 , 58, 60, 62, 64, 66, 68, 70: Embodiment of transistor The second figure shows a flowchart of a method for automatically setting the integrated circuit operating mode as a failure analysis of the present invention. After the wafer is subjected to a number of processes such as deposition, etching, lithography, and doping, each integrated circuit wafer can be formed in the wafer, and a test circuit can be formed on the wafer (S22). The shape of the integrated circuit chip is as shown in FIG. 3A, which illustrates the pad of the integrated circuit chip of the present invention. In FIG. 3A, ED0 (Extended Data Output) DRAM is taken as an example. The body circuit chip 30 is similar to the conventional one in that it includes a plurality of input pins 31 for inputting different specific voltages to the input pins 31, so that the integrated circuit 30 enters a mode state. However, what is different from the conventional integrated circuit wafer is that a set of test pads (such as pad A 32, pad B 34, and pad C 36) are formed on the integrated circuit wafer 30 of this embodiment (S24), 06424twfl.doc / 006 Amendment date 92.7.18 The pads used in this group of tests are for failure analysis of integrated circuits. Pad A 32, pad B 34, and pad C 36 are examples of testing pads in three different working modes in this embodiment. Other testing pads in different working modes can be designed according to actual needs. Used for integrated circuit fault analysis. FIG. 3B illustrates test circuit diagrams of different operating modes of the present invention. In FIG. 3B, in the integrated circuit wafer 40, for the above-mentioned three test pads, test circuits of three different operating modes are respectively designed to perform failure analysis of the integrated circuit in different operating modes. When you want to test the failure mode of the integrated circuit, you only need to add the test power supply probe to the corresponding test pad (S26). You can reduce the number of probes to perform the integrated circuit. Failure analysis. As shown in Figure 3B, when the EDO DRAM is to perform a "standby mode" failure analysis, a test probe (usually 5V or 3.3V) is connected to the pad A 42 with a probe, and the integrated circuit chip is used. The basic power pad (not shown) on 40 uses another probe to connect a ground voltage as the reference voltage. In standby mode, the test power supply connected to the pad A 42 is connected to the corresponding test circuit, including transistors 48, 50 , 52, and make the test power supply a certain voltage input to the input pins VDD, / RAS, / CAS of the integrated circuit (ie, EDO DRAM). And enter the "wait mode", so you can check the wait of the EDO DRAM 1220026 06424twfl .doc / 006 Amendment date 92.7.18 Current (standby current) 〇 Similarly, when EDO DRAM is to perform "input leakage high level" failure analysis, connect test power to pad 44 with a probe. And in conjunction with the basic power pad (not shown) on the integrated circuit chip 40, another probe is used to connect a ground voltage as a reference voltage. Under the state of high level of input leakage, make the test power connected to the pad B 44 Turn on the corresponding test circuit, Including all transistors 54: 56, 58, 60, 62, etc., and make the test power supply a specific voltage, directly input all input pins VDD, / RAS, / CAS, / of the integrated circuit (ie, EDO DRAM) WE ../ 0E and all other pins. And enter the "input leakage high level mode", so you can analyze the high level of input leakage of EDO DRAM. Similarly, when EDO DRAM is going to do "low level of input leakage In the failure analysis, a test probe is connected to the pad C 44 with a probe, and a basic power pad (not shown) on the integrated circuit chip is connected to a ground voltage with another probe as a reference voltage. In the low level of input leakage, make the test power supply connected to pad C 44 conduct the corresponding test circuit, including all the transistors 64, 66, 68, 70, etc., so that one input pin VDD inputs the test power supply, and other Input pins such as / RAS, / CAS, / 0E input specific voltage, for example, the specific voltage is a ground voltage VSS. And enter _ "input leakage low level mode", so you can input EDO DRAM 11 1220026 06424twfl.doc / 006 Revised date 92. 7.18 Leakage low-level analysis: According to the above different operating modes, the failure analysis and structure of the integrated circuit are performed. If a bad integrated circuit chip is detected, it will be marked on the integrated circuit chip and it will be used in the packaging process in the future. The bad integrated circuit chip is directly removed to avoid unnecessary packaging costs. Therefore, the advantage of the present invention is to provide a method and structure for automatically setting the operating mode of the integrated circuit as a failure analysis. Under the test pad, add a test power supply to any test pad, and then make the corresponding test circuit operate, control the input of different specific voltages to the input pin part or all the input pins, plus a ground reference solder The pad can perform different modes of the integrated circuit for fault analysis. Therefore, as long as the probes are used for the two pads, the number of external probes can be reduced, and the failure analysis of the integrated circuit can be observed without dead ends. In summary, although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. 12