TW594912B - Fabrication method of shallow and deep trench isolation structure - Google Patents

Abstract

A fabrication method of shallow and deep trench isolation structure is disclosed. This fabrication method combines a CMP (chemical mechanical polishing) method and other processes of deposition, lithography and etching for fabricating an isolation structure having a filling surface of high degree of flatness. This fabrication method provides a larger process window while the lithographic process is performed for forming a deep trench. By using this fabrication method, the device integrality can be promoted, especially for the bipolar CMOS (BiCMOS) or other CMOS transistors. Moreover, this fabrication method can lower the capacitance value of BiCMOS transistor, thus benefiting the fabrication of high-frequency IC devices.

Description

594912 V. Description of the invention (1) 1 ~ fa._ 明 __. Technology performed: The present invention relates to a shallow trench (S ha 1 1 〇w Trench; S T) and deep trench (Deep (Trench; DT) manufacturing method of isolation structure, in particular, it relates to a manufacturing method combining chemical mechanical polishing (CMP) method and other deposition, lithography, and silver engraving processes, so as to produce high flatness A shallow trench and deep trench isolation structure with a degree of surface. $ Prior technology: Metal Oxide Semiconductor (MOS) transistors are one of the most important basic electronic components in integrated circuit technology. Usually, a complete integrated circuit is composed of many gold-oxygen semiconducting crystals. In order to prevent the short circuit of these adjacent transistors, an isolation structure must be added between the adjacent metal-oxide semi-conductive crystals for electrical isolation. In recent years, the semiconductor industry has developed vigorously, and integrated circuits have now developed into the field of ultra-large integrated circuits (U 11 r a L a r g e S c a 1 e I n t e g r a t e d Circuit, ULS I). In order to pursue integrated circuits with higher density, high speed, and low power consumption, metal oxide semiconductor devices must be continuously reduced. Due to the increase in the degree of integration of semiconductor elements, the isolation structure between elements must also be reduced, which greatly increases the difficulty of element isolation technology. Especially for high-frequency integrated circuit (IC) components, such as Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) transistors, the isolation structure is more important for its resistance valley (RC) characteristics. Generally speaking, the pn junction is used to make 594912. V. Description of the Invention (2) Electrical isolation will result in poor resistance-capacitance (RC) characteristics. Therefore, Bi CMOS transistors usually use shallow trench and deep trench isolation structures, especially for deep sub-micron processes, such as 0.18 micron processes. However, the fillers of shallow trench and deep trench isolation structures (such as HDP (High Density Plasma) silicon oxide layer) produced by conventional technology have very uneven surfaces, and this uneven surface will greatly reduce semiconductors. Component accumulation degree. In particular, deep sub-micron processes have stricter requirements for the flatness of the HDP oxide layer. On the other hand, during the subsequent step of forming the gate material, materials such as polycrystalline stone (ρ ο 1 y-S i) are likely to remain on this uneven surface, plus the formation of a double carrier connection The transistor (Bipolar Junction Transistor; BJT) needs to go through multiple steps of depositing polycrystalline material, so more polycrystalline material will remain on the uneven surface. Residual polysilicon materials often cause many unexpected problems and greatly affect the performance of semiconductor devices. In addition, when the lithography process of deep trenches is performed on uneven surfaces, the process window it can provide is smaller, which increases the difficulty of making deep trenches. ^ Please refer to FIGS. 1A to 11, and FIGS. 丨 A to 1I are schematic cross-sectional views illustrating a manufacturing process of a conventional shallow trench and deep trench isolation structure. Please refer to FIG. 1A. First, a conventional method for manufacturing a shallow trench and a deep trench isolation structure is to provide a substrate 12 having a shallow trench 20 formed thereon, such as a silicon substrate, and a non-shallow trench on the substrate 12. The part 20 is covered with a sUicQn nitride (SiN) layer 18, and the shallow trench 20 is filled with a HDP silicon oxide layer 3594912 V. Description of the invention (3)

To the height of the silicon nitride layer 18. Please refer to FIG. 13, and then completely remove the nitride layer 18, and then re-deposit the silicon nitride layer 28 to cover the substrate} 2 and the HDP oxide layer 30. Please refer to FIG. 1C ′ and then deposit a hard mask (h a r d m a s k) layer 3 8 to cover the silicon nitride layer 2 8. Referring to FIG. D, a photoresist layer 40 is formed on the hard mask layer 38, and a deep trench pattern 42 is defined on the photoresist layer 40. Referring to FIG. 1E, the hard mask layer 38, the nitrided silicon layer 28, and the HDP silicon oxide layer 30 are etched by the deep trench pattern 42. After removing the photoresist layer 40, the hard mask layer 38 is used as a mask, and then a deep trench etching step is performed to form a deep trench 44 in the substrate 12. The hard mask layer 38 is then removed to expose the surface of the silicon nitride layer 28. Referring to FIG. 1p, a lining oxide layer 32 is formed on the bottom and sidewalls of the deep trench 44, and then a channel stop implantation step is performed. Referring to FIG. 1G, a TEOs oxide layer 34 of conformal (coon 〇rmai) is then deposited to cover the bottom and side walls of the deep trench 44 and HDP oxide stone = 30 and silicon nitride layer 2 The side walls of 8 are filled with a polycrystalline silicon layer 36 to fill the deep trenches 44 and shallow trenches 20. Please refer to Section VII, etch back the polycrystalline silicon layer 36, and then remove a part of the TE0s oxide layer 34 by etching. Please refer to FIG. 1I, and then perform a polycrystalline silicon oxidation step. After forming an oxide layer 39 on the surface of the polycrystalline silicon layer 36, and then removing the nitride layer 28, the shallow trench and deep trench isolation structures can be completed.

= Continue to refer to Figure 1I. However, since the conventional manufacturing method of the shallow trench and deep trench isolation structure is to first etch the polycrystalline silicon layer 36 and the TEOS oxide layer 34, the surfaces of the etched polycrystalline silicon layer 36 and the TEOS oxide layer 34 are already uneven, and then Table of trench fillings after polycrystalline silicon oxidation step: Yi Yi

: Myi2, description of the invention (4): two: pieces Ϊ tenants: the unevenness of the 88 filling surface of the 1 channel will cause unpredictable problems created by the process, especially the deep submicron system, It ^ > Ik cut needs to develop a shallow trench and deep trench isolation structure t, 'can effectively and accurately form a high flatness trench filling K i t: in the light background, the conventional shallow trench The surface of the trench isolation structure, trench, and trench filler will be quite uneven. The uneven trench filling surface will cause polycrystalline silicon residue and decrease the accumulation degree of the device ’, which will cause a lot of unpredictable problems for semiconductor devices, especially those manufactured in the deep sub-micron process. Therefore, the main object of the present invention is to provide a method for manufacturing a shallow trench and a deep trench isolation structure. The present invention combines the chemical mechanical polishing method and other processes of deposition, lithography and etching to effectively and accurately form the surface of the trench filling material with high flatness, so as to improve the component concentration of the south and avoid polycrystalline slag residues Y In addition, in the lithography process of deep trenches, a larger retention can be provided. The present invention also provides a shallow trench description 〇a ...... 丨 Wang Jiu / Danqu and deep trench vibration According to the above method, the present invention at least includes: providing a substrate window. Another object is to provide a shallow trench and deep trench isolation structure. The dream of the present invention is to provide high quality and low power for BiCMOS and CMOS transistors. Purpose of% of capacity

Page 9 594912 V. Description of the invention (5) ~~ -——- For example: silicon substrate; forming a shallow trench on this substrate; forming silicon nitride on the substrate and exposing the shallow trench; Forming a liner oxide layer on the bottom and side walls of the shallow trench; depositing a first HDP silicon oxide layer to fill the shallow trench and covering the R cap silicon nitride layer; using chemical mechanical polishing to smooth the first HDP oxide layer to nitrogen Above the fossil layer; forming a photoresist layer on top of the first HDP silicon oxide and forming a deep trench pattern on the photoresist layer; etching the first HDp oxide layer to transfer the deep trench pattern to the first jjDP Oxidize the silicon layer to form a hard mask layer; remove the photoresist layer; form a deep trench in the substrate by etching through the hard mask layer; form a second oxide layer on the bottom and side walls of the deep trench The step of performing channel stop implantation; depositing ^ ⑽ oxygen = layer ^ to cover the second lining oxide layer and the first HDP silicon oxide layer; filling a polycrystalline layer to fill deep trenches and shallow trenches; back Etch the polycrystalline layer to approximately the same height as the substrate; by etching Remove one of the TEOs oxide layers = minutes; etch the polycrystalline silicon layer to further remove more polycrystalline silicon layers, " l Build a first HDP silicon oxide layer over the polycrystalline silicon layer, and fill the deep trenches and shallow trenches; Remove one P knife of the first HDP silicon oxide layer and the second HDP silicon oxide layer to the upper surface of the substrate by inverting the mask of the active region (〇D Reverse; 〇)) 10 and leaving it for a while; A chemical mechanical polishing method is used to smooth the height of the second HDP silicon oxide layer and the first HDP silicon oxide layer to the upper surface of the substrate; and removing the nitrided hair layer. The invention discloses a method for manufacturing a shallow trench and a deep trench isolation structure. The present invention is a combination of chemical mechanical polishing

Page 10 594912 V. Description of the invention (6)

Pol ishing (CMP) and other deposition, lithography, and etching processes are used to fabricate shallow trench and deep trench isolation structures with high flatness filler surfaces.

Please refer to FIGS. 2A to 2J. FIGS. 2A to 2J are schematic cross-sectional views illustrating a manufacturing process of a shallow trench and a deep trench isolation structure according to the present invention. Please refer to FIG. 2A. First, the present invention provides a substrate 12 such as a silicon substrate, wherein a shallow trench 20 is formed on the substrate 12. A nitride layer 18 'has been formed on the substrate 12 and the shallow trench 20 is exposed. For example, a conformal liner oxide layer 60 is formed on the bottom and sidewalls of the shallow trench 20 by thermal oxidation. Then, for example, a high-density plasma chemical vapor deposition method is used to deposit a HDP silicon oxide layer 30 to approximately fill the shallow trench 20 and cover the silicon nitride layer 18, wherein the HDP silicon oxide layer 30 is deposited to a thickness greater than about 90. 0 0 Angstroms. Please refer to FIG. 2B '. Then, for example, a chemical mechanical polishing method is used to smooth the H D P oxidized stone layer 30 to a position from about 100 angstroms to about 3,000 angstroms above the nitrided stone layer 18. Referring to FIG. 2C, a photoresist layer 40 is then formed on the HDP silicon oxide layer 30, and a deep trench pattern 42 is formed on the photoresist layer 40. Please refer to FIG. 2D. Then, for example, the HD P oxide layer 30 is engraved with dry money to transfer the deep trench pattern 42 to the HDP oxide layer 30. The HDP oxide layer 30 can be used as a hard material. The use of the cover layer. Then, the photoresist layer 40 is removed.

Referring to FIG. 2E, the deep trenches 44 are formed in the substrate 12 by, for example, dry etching and using the fjDP oxide layer 30 as a mask ', wherein the depth of the deep trenches 44 is about 7 micrometers. A conformal lining oxide layer 32 is then formed, for example, by thermal oxidation to cover the bottom and sidewalls of the deep trenches 44. After the formation of the liner oxide layer 32, a step of implantation of the channel is performed. Please refer to Figure 2 F.

Μ

Page 11 594912 V. Description of the invention (7)-If the conformal TEOS oxide layer 34 is deposited by chemical vapor deposition, the oxide layer 32 and the HDP oxide layer 30 are covered. Then, for example, the polycrystalline silicon layer 36 is filled by a chemical vapor deposition method, thereby filling the deep trenches 44 and the shallow trenches 20. fRefer to FIG. 2G. __ More and more Shi Xi layer 36 up to the bottom of the shallow trench 20. Then, a part of the TEOS oxide layer 34 is removed by etching, so that the HDP silicon oxide layer 30 is exposed, and at the same time, the height of the TEOS oxide layer 34 is approximately equal to the height of the two polycrystalline silicon layer 36. Then, if necessary, the present invention can further etch the polycrystalline silicon layer 36 to further remove more polycrystalline silicon layer 36. Please refer to FIG. 2H, and then, for example, a CVD silicon oxide layer 70 is deposited on the polycrystalline silicon layer 36 by chemical vapor deposition, and the deep trench 44 and the shallow trench 20 are filled. The Ηρ silicon oxide layer 70 can be filled to be approximately aligned with the upper surface of the HDP silicon oxide layer 30. If necessary, in order to accurately control the height disk quality of the trench filling surface, the present invention can invert the mask and etching method of the active area; part of the HDP oxide layer 30 and HDP oxide layer 70 until Approximately the surface of the nitrided layer 18 is exposed. Please refer to Figure 2! Figure 'Using chemical mechanical polishing method to smooth H 30 and 11_Huameng 4 70 until the surface of the gasification dream layer 18 is exposed. Refer to the second top' and then, for example, dry-etching to remove nitrides Layer 18 to complete the isolation structure for shallow trenches and deep trenches. The flatness 88 of the prepared trench surface is quite south, which is enough to meet the requirements of the deep sub-micron process. The above = the height and thickness of the layers of the apricots by various methods are only shown and not limited. , And needs vary, so it ’s worth noting that the nitrogen-cut layer,

Page 12 594912 V. Description of the invention (8) The TEOS oxide layer can also be its silicon layer. The shallow trenches of the present invention can be applied to other non-conducting conditions and needs. Due to the characteristics of the shallow trench mechanical grinding method of the present invention Therefore, a manufacturing process of the present invention is formed. Due to other deposits, lithography and etch, the ditch fillings of the flatness crystal dreams remain. And, in the process window. Another advantage of the present invention is the manufacturing method. The low-capacitance isolation structure of the present invention, such as a preferred embodiment of a person skilled in the art, is not other than that which does not depart from the present invention, and should be included in the non-conductive and other suitable materials composed of the following dielectric materials Manufacturing method of dielectric material trench. In combination with deep trench manufacturing methods, other trench filling points that sink into high flatness are properly provided to provide a shallow trench. The present invention successfully combines the chemical etching process, so the surface can be effectively used to improve the lithography of the deep trench. Provide a shallow trench and a depth as is understood by BiCMOS and CMOS transistors. The above description is used to limit the scope of patent applications completed under the spirit of the disclosure of the present invention.

Dielectric layer, and polycrystalline layer. In other words, it can be used as a non-conductive material to make full use of chemical machinery, lithography and etching filling surface. Isolation with deep trenches and mechanical grinding method and accurately forming a high accumulation degree, to avoid multiple passes, to provide a larger trench isolation structure for the quality of the south and only the scope of the patent of the present invention; etc. Change or repair

Page 594912 Brief illustration of the preferred embodiment of the present invention has been described in more detail in the preceding explanatory text with the following figures, where: Figures 1 A to 1 I are conventional shallow trenches A schematic sectional view of the manufacturing process of the isolation structure from the deep trench; and FIGS. 2A to 2J are schematic sectional views illustrating the manufacturing process of the isolation structure of the shallow trench and the deep trench of the present invention. Description of drawing numbers: 12 substrates: 1 8, 2 8 silicon nitride layer 2 0 shallow trench 30, 70 HDP silicon oxide layer 32, 60 lining oxide layer 34 TEOS oxide layer 3 6 polycrystalline silicon layer 38 hard cover curtain layer 3 9 Oxide layer 4 0 Photoresist layer 42 Deep trench pattern 44 Deep trench 88 Trench filling surface

Page 14

Claims (1)

594912 VI. Scope of patent application ^-1. A method for manufacturing a shallow trench (Shallow Trench; ST) and a deep trench (Q Trench; DT) isolation structure, at least including: ep providing a substrate; forming a shallow trench on the base On the substrate, a silicon layer has been formed on the substrate and the shallow trench is exposed; a first oxide layer is formed on a bottom and a sidewall of the shallow trench; and a first HDP (High Density Plasma) is formed. High-density electrical equipment) a silicon oxide layer to fill the shallow trench and cover the silicon nitride layer, wherein the _ HDP silicon oxide layer has a thickness; planarize the first HDP silicon oxide layer until about a distance from the nitride A height above the silicon layer; forming a hard mask layer with a deep trench pattern on the first HDP oxide layer; using the hard mask layer as a mask to form a deep trench in the substrate Forming a second lining oxide layer on a bottom and a side wall of the deep trench; performing a channel blocking implantation step on the substrate; forming a TEOS oxide layer that is conformal to cover the second lining oxide Layer and the first HDP silicon oxide layer Forming a polycrystalline silicon layer to fill the deep trenches and the shallow trenches; leaving back the polycrystalline debris layer to about below an upper surface of the substrate; removing a portion of the TEOS oxide layer; forming a second HDP oxide A silicon layer on the polycrystalline silicon layer and filling the deep trench and the shallow trench; Page 15 594912 A HDP silicon oxide layer is approximately equal to σ the negative and VI. Patent application scope Flatten the second surface of the top surface isoplanar to remove the nitrided layer. t 浅 The manufacturing method of the shallow trench and deep trench isolation structure described in item 1 of the patent scope, wherein the substrate is a silicon substrate. 3. The method of manufacturing a shallow trench and a deep trench isolation structure as described in item 丨 of the declared patent scope, wherein the thickness is greater than about 900 Angstroms. 4. The method for manufacturing a shallow trench and a deep trench isolation structure as described in item 丨 of the scope of applying for a patent, wherein the depth of the deep trench is about 7 microns. 5. The manufacturing method of the shallow trench and deep trench isolation structure as described in item 1 of the declared patent scope, wherein the height is about 1,000 angstroms to about 3,000 angstroms. 6. The method for manufacturing a shallow trench and a deep trench isolation structure as described in item 丨 of the patent application scope, wherein after the step of removing the plutonium oxide layer, the method further includes etching the polycrystalline silicon layer to remove more This polycrystalline layer is a polycrystalline layer. 7. The method for manufacturing a shallow trench and a deep trench isolation structure according to item 丨 of the patent application scope, wherein in the step of planarizing the second silicon oxide layer and the first HDP silicon oxide layer, t includes: Invert Active Area⑽ Page 16 594912 Sixth, the scope of the patent application -----〇 =) to remove the second HDm fossil eve 1 ϊ m eve / a part until it is higher than the upper surface of the substrate In order to further reduce the first-depleted μ & oxidized stone layer, a height β HDP emulsified stone layer and the -_ II. The shallow trench and deep trench isolation structure described in item 1. Two HDP oxide stone layers are formed in the polycrystalline dream: The height of the first silicon oxide layer is approximately equal to the height of the first HDP emulsified silicon layer. The manufacturing method of the isolation structure between the trench and the deep trench canal includes: providing a substrate; 3-the substrate has been formed with a -gasified silicon layer on the substrate, and the shallow trench is exposed; forming a A first lining oxide layer is on a bottom and a side wall of the shallow trench; 积: ΐ: Γ oxide layer to fill the shallow trench and cover the gasified stone layer, wherein the first HDP silicon oxide layer has A thickness; mechanical polishing method to smooth the first-, silicon oxide layer up to about a distance above the nitrided layer, a high-yield · forming a photoresist layer on the first Hnp pattern on the photoresist layer; Cut the layer and form a deep trench oxidized stone layer 'to transfer the deep trench pattern to the HDP oxidized stone layer to form a hard mask layer; remove the photoresist layer; Page 17 594912 6. The scope of the patent application is to use the hard mask layer as a mask to form a deep trench in the substrate; to form a second lining oxide layer on a bottom and a side wall of the deep trench; The substrate is subjected to a channel blocking implantation step; a TEOS oxide layer is deposited to cover the second liner oxide layer and the HDP silicon oxide layer; a polycrystalline silicon layer is filled to fill the deep trench and the shallow trench; etchback The polycrystalline silicon layer is approximately lower than an upper surface of the substrate; 'removing a part of the TEOS oxide layer; the polycrystalline chip layer is engraved to further remove more of the polycrystalline silicon layer; HD oxidized; ^ a Yu Xizhi cut vine μ 洱 4 # A i! Layer on the multi-day silicon layer and fill the deep trench and the shallow trench; invert the mask and etching of the active area Removing a portion of the second HDP silicon oxide layer and the first HDP silicon oxide layer until it is about higher than the upper surface of the substrate; using the chemical mechanical polishing method to smooth the second HDp silicon oxide layer and the The first HDP silicon oxide layer is about the same as the substrate Other planar surface; and removing the silicon nitride layer. 10. The method for manufacturing a shallow trench and a deep trench isolation structure as described in item 9 of the scope of the patent application, wherein the substrate is a silicon substrate. Π. A method for manufacturing a shallow trench and a deep trench isolation structure as described in item 9 of the scope of the patent application, wherein the thickness is greater than about 900 Angstroms. 594912 VI. Scope of patent application 1 2 · The manufacturing method of the shallow trench and deep trench isolation structure as described in item 9 of the scope of patent application, wherein the height is about 100 angstroms to about 300 angstroms. 13. The method for manufacturing a shallow trench and a deep trench isolation structure according to item 9 of the scope of the patent application, wherein the depth of the deep trench is about 7 microns. 14. The manufacturing method of the shallow trench and deep trench isolation structure as described in item 9 of the scope of patent application, wherein the second HDP is oxidized in the step of depositing the second HDP silicon oxide layer on the polycrystalline silicon layer. A height of the silicon layer is approximately equal to the height of the first HDP silicon oxide layer. «1 5. A method for manufacturing a shallow trench and deep trench isolation structure, at least comprising: providing a substrate; forming a shallow trench on the substrate, wherein a first dielectric layer has been formed on the substrate, and The shallow trench is exposed; a second dielectric layer is formed to fill the shallow trench and cover the first dielectric layer, wherein the second dielectric layer has a thickness; the second dielectric layer is planarized until about A height above the first dielectric layer; forming a deep trench in the substrate; ♦ forming a conformal third dielectric layer to cover the upper surface and sidewalls of the deep trench; forming a non-conductive layer To fill the deep trench and the shallow trench; Page 19 594912 VI. Apply for a patent to etch back the non-conductive layer until it is lower than an upper surface of the substrate; remove a part of the third dielectric layer to expose the second dielectric layer; form a fourth A dielectric layer on the non-conductive layer and filling the deep trenches and the shallow trenches; planarizing the fourth dielectric layer and the second dielectric layer up to about the same plane as the upper surface of the substrate; and removing The first dielectric layer. 16. The method for manufacturing a shallow trench and deep trench isolation structure as described in item 15 of the scope of patent application, further comprising at least forming a first lining oxide layer on a bottom and a side wall of the shallow trench. 1 7. The method for manufacturing a shallow trench and deep trench isolation structure as described in item 15 of the scope of patent application, further comprising at least: forming a hard mask layer having a deep trench pattern on the second dielectric layer; And using the hard mask layer as a mask to form the deep trench in the substrate. 18. The method for manufacturing a shallow trench and deep trench isolation structure according to item 15 of the scope of patent application, further comprising: forming a second lining oxide layer on a bottom and a sidewall of the deep trench; and the substrate Perform a one-pass rejection implant step. 1 9. Isolation junction of shallow trench and deep trench as described in item 15 of the scope of patent application 594912 6. The manufacturing method of the patent application structure, wherein the non-conductive layer further includes a group selected from the group consisting of polycrystalline silicon and silicon oxide and any combination thereof. 20. The manufacturing method of the shallow trench and deep trench isolation structure described in item 15 of the scope of the patent application, wherein the first dielectric layer is a silicon nitride layer. 2 1. The method for manufacturing a shallow trench and deep trench isolation structure as described in item 15 of the scope of patent application, wherein the second dielectric layer is a HDP silicon oxide layer. 2 2. The method for manufacturing a shallow trench and a deep trench isolation structure as described in item 15 of the scope of patent application, wherein the third dielectric layer is a TEOS oxide layer. 2 3. The method for manufacturing a shallow trench and deep trench isolation structure according to item 15 of the scope of the patent application, wherein the fourth dielectric layer is a HDP silicon oxide layer. 24. The method for manufacturing a shallow trench and deep trench isolation structure as described in item 15 of the scope of patent application, wherein the substrate is a silicon substrate. 25. The method for manufacturing a shallow trench and a deep trench isolation structure as described in item 15 of the scope of patent application, wherein the thickness is greater than about 900 Angstroms. 26. The method for manufacturing a shallow trench and a deep trench isolation structure according to item 15 of the scope of the patent application, wherein the depth of the deep trench is about 7 microns. 594912 VI. Scope of patent application 2 7. The manufacturing method of the shallow trench and deep trench isolation structure described in item 15 of the scope of patent application, wherein the height is about 100 angstroms to about 300 angstroms. 2 8. The method for manufacturing a shallow trench and a deep trench isolation structure as described in item 15 of the scope of patent application, wherein after the step of removing a portion of the third dielectric layer, the method further includes etching the non-conductive layer to remove it. More of this non-conductive layer. 2 9. The method for manufacturing a shallow trench and a deep trench isolation structure according to item 15 of the scope of patent application, wherein in the step of planarizing the fourth dielectric layer and the second dielectric layer, the method further includes: The mask and etching of the active area are adjusted to remove a portion of the fourth dielectric layer and the second dielectric layer up to approximately higher than the upper surface of the substrate, thereby further reducing the fourth dielectric layer and the first dielectric layer. One height of two dielectric layers. 30. The method for manufacturing a shallow trench and a deep trench isolation structure as described in item 15 of the scope of patent application, wherein in the step of depositing the fourth dielectric layer on the non-conductive layer, the A height is approximately equal to the south of the second dielectric layer. Page 22