TW594813B - Manufacture for a lamination capacity - Google Patents

Abstract

A manufacture for a lamination capacity is disclosed. First, provide a substrate layer, then form a plurality of electrical layers by using a metal powder spray method, form a plurality of dielectric layers by a spray method. The capacity is composed of the electrical layers alternately stacked with the dielectric layers. A pair of terminal electrodes is formed on both sides of the electrical layers and is electrical coupled to the respective electrical layers. A passivation layer is formed on the exposed surface of the terminal electrodes. The connection between the electrical layers and the dielectric layers can be improved thereby, that is the standard for the depth uniform ratio of the dielectric layer is under +10%, and the shift variation is under 100 micron between two neighboring electrical layers.

Description

594813

_Case No. 911364 Milk --- 5. Description of the invention (1) Ijg's technology I related to electrode layers' and the manufacturing process needs to be patterned based on the current board settings or the grid system of the Grid A substrate. The good electrical and electrical resistance of the edge layer is well-connected. When the heat is passive, it will not affect one kind, and it will help the electrode layer and structure to improve the conductivity of the semiconductor and the lack of ground rray. The circuit layer is placed in the phase-gas characteristic, which is passive to the passive element j of the wafer and its electricity is heard on the crystalline element. The process and structure of the capacitor, especially the G ± ti with the dielectric layer, to form a multilayer dielectric. . For the time being, the stacking of stacks to form a multi-layer capacitor body has evolved, which has enabled Fung to continue to develop more sophisticated and more advanced electronic components produced in the city. Design of passive components = overlay = technology 'build-up base. ,,; Fan Yue / + Si are occupied in the semiconductor industry "/ \" ^ / 2/1 grid array (1? 111)-(^ 4/6311 FC / BGA ) The package is made up of a chip, and the chip and the package are: Thunder is arranged in the package = = = Force margin is layered, and the adjacent two patterned lines are formed: and the inside of the other 3 element substrate Because the heat energy produced by HA a, Shi · films will be different, it will produce gas characteristics,… = under the environment, but also only. 卞 It has high temperature resistance and high stability.

10183twf2.pt 594813 _ case number 91136482_ year month day amendment _ five, the description of the invention (2) qualitative passive components, and laminated ceramic capacitors (Laminated ceramic c a p a c i t y) is one example. Conventional multilayer ceramic capacitors are mainly composed of a multilayer ceramic dielectric layer and a metallic layer. The ceramic dielectric layer is made of a high dielectric constant material such as barium titanate. titanate), and the metal layer is composed of a conductive material such as silver and silver alloy, and the multilayer metal layer forms a plurality of positive and negative alternating internal electrodes, and the internal electrode and the ceramic dielectric layer system A capacitor structure is formed, and a pair of terminal eletrode are also arranged on both sides thereof, which are electrically connected to the internal electrodes of the positive electrode and the negative electrode respectively, and a surface metal layer can be formed on the surface of the terminal electrode to prevent oxidation of the terminal electrode. In addition, the conventional multilayer capacitor manufacturing process includes the following steps: first, the ceramic green tape process is performed, and a dielectric powder such as a lock salt and an organic binder are uniformly mixed, To form a ceramic green embryo. Next, a metal paste printing (meta 1 pasteprinting) process is performed. The metal powder and the organic adhesive are transferred onto the ceramic green embryo by screen printing to form a metal layer, and the ceramic green embryo is then transferred. After the steps of stacking and pressing, a multilayer ceramic dielectric layer and a metal layer structure are formed, and then the laminated structure is co-fired at a sintering temperature of 1100 ° to 1500 ° ( Sinter), and formed a pair of terminal electrodes on both sides of the structure of the sintered ceramic dielectric layer and the metal layer, and finally sintered again to solidify the pair of terminal electrodes, so that the lamination was completed.

10183twf2.ptc Page 9 594813 _ Case No. 91136482 _ Month and Day __ V. Description of the invention (3) Process of capacitor. It is worth noting that during the co-firing process described above, the organic solvent will be removed by evaporation during high temperature sintering, which will reduce the original volume of the ceramic dielectric layer and the metal layer, and affect the bond between the ceramic dielectric layer and the metal layer. In addition, the thickness of the ceramic dielectric layer and the metal layer cannot be uniform, so the capacitance value of the multilayer capacitor cannot be controlled within the standard range. In addition, during the co-firing process, the thermal expansion coefficient of the metal layer is different from that of the ceramic dielectric layer, and the optimal sintering temperature of the metal layer is also different from the optimal sintering temperature of the ceramic dielectric layer, so many variables cannot be controlled Below, the delamination of cracks, voids, cracks, and surface curvature during the sintering of the multilayer capacitor will seriously affect its standard capacitance value. SUMMARY OF THE INVENTION In view of this, the object of the present invention is to provide a multilayer capacitor manufacturing process and structure, wherein the multilayer capacitor manufacturing process can be performed at a normal temperature, so that the thicknesses of the dielectric layer and the electrode layer can be uniform, and the dielectric layer and the The electrode layer has good bonding property, and can effectively control the capacitance value of the multilayer capacitor within the standard range. To achieve the above purpose of the present invention, a multilayer capacitor manufacturing process is proposed, which includes the following steps: (1) providing a base layer; (2) ) Forming a patterned first mask layer on the surface of the base layer; (3) forming a first electrode layer on the surface of the base layer exposed by the first mask layer by means of high-speed physical metal deposition; ( 4) remove the first mask layer; (5) form a first dielectric layer on the first electrode layer and the base layer by coating the dielectric material; (6) form a second patterned layer The cover layer is on the surface of the first dielectric layer;

10183twf2.ptc Page 10 594813 _Case No. 91136482_Year Month and Day Amendment _ V. Description of the Invention (4) (7) A high-speed physical metal deposition method is used to form a second electrode layer exposed on the second cover layer. On the surface of the first dielectric layer, the second electrode layer and the first electrode layer at least partially overlap; and finally (8) removing the second cover layer. According to the multilayer capacitor manufacturing process of the present invention, the above steps will form two electrode layers (2). If the above steps (2) to (4) are repeated once, three electrode layers (2 + 1) can be formed. If the above steps (2) to (8) are repeated at least once, an even number of electrode layers (2N, N is a natural number greater than 1) will be formed, and then steps (2) to (4) are repeated once more. , An odd number of electrode layers (2 N +1) can be formed. The multilayer capacitor manufacturing process according to the present invention further includes a step (9) of coating a dielectric material to form a second dielectric layer on top of the second electrode layers and the individual topmost layers of the first dielectric layers. (10) forming a pair of terminal electrodes on both sides of the first electrode layers and the second electrode layers, and electrically connecting the first electrode layers and the second electrode layers, respectively; and (11) forming a surface The metal layer is on the exposed surface of the pair of terminal electrodes. In order to achieve the above object of the present invention, a multilayer capacitor is proposed, which is mainly composed of a plurality of electrode layers and at least one dielectric layer. Among them, any two adjacent electrode layers are partially overlapped, and the relative horizontal offset of any two adjacent electrode layers is less than 100 microns. In addition, the dielectric layer is arranged between any two adjacent electrode layers, and the uniformity ratio of the thickness of the dielectric layer can be maintained at about 10%. In order to make the above objects, features, and advantages of the present invention more obvious and easier

10183twf2.ptc Page 11 594813 May_Modify and match the attached drawings to explain in detail_Serial No. 9113fi4R? ._ ^ V. Description of the invention (5) Understand, the following two preferred embodiments are described below, as follows: Embodiments FIG. 1A to FIG. 1 of the first embodiment sequentially show a cross-sectional flowchart of a multilayer capacitor manufacturing process according to the first embodiment of the present invention.

Please refer to FIG. 1A. First, a base layer 110 is provided, and the material of the base layer 110 may be a dielectric material. Next, a patterned first cover layer 12 is formed on the surface of the base layer 11 () by attaching a thin film or spin coating an organic material, and then referring to FIG. 1B, A high-speed physical metal deposition method is used to form a first electrode layer 130a on the surface of the base layer 110 exposed by the first cover layer 120. High-speed physical metal deposition technologies, such as metal spraying (meta) 1 spray) or high speed particle consolidation (metal deposition technology) such as metal deposition technology (metal spraying method, for example, arc spraying method, plasma spraying method) , Flame spraying (flame spray), high velocity oxygen fuel spraying (cathode arc ion plating), and the like. Then, the first cover layer 12 is removed, so that the structure of FIG. 1C can be obtained. Say

Referring to FIG. 1D, a dielectric material 140 is formed on the first electrode layer 130a and the base layer 110 by using a dielectric material coating method, and then a patterned first layer is formed on the surface of the electrical layer 140. The second cover curtain layer 15〇, not ^

10183twf2.ptc Page 12 594813-Case No. 9113 Charm 82__Yueyue Yue Amendment V. The description of the invention (6) is' the second cover layer 150 and the first cover layer 120 are respectively located in the base layer 1 1 0 On both sides, please refer to FIG. 1E, and then form a second electrode layer 130b on the surface of the dielectric layer 14 exposed by the second mask layer 150 by means of high-speed physical metal deposition, and The second electrode layer i30b at least partially overlaps with the first electrode layer 130a, and the area and pitch of the overlap determine the capacitance value between the first and second electrode layers 130a and 130b. Next, the second cover layer 150 is removed to obtain the structure of FIG. 1F. It can be known from the above process that it is assumed that the overlapping area between adjacent two electrode layers is A and the distance is d. From the overlapping area A and the distance d, the capacitance C ′ of the adjacent two electrode layers can be calculated. .c = Ck * A / d, Ck is the capacitance coefficient. It is worth noting that with the multilayer capacitor manufacturing process of the present invention, the thickness of the dielectric layer 140 will not change because the conventional sintering step is not required, and the uniform thickness ratio can be maintained at about 10% of the soil, that is, the thickness is about In the range of 90% to 110% of the standard thickness (about 25 microns). In addition, the present invention uses a method of high-speed physical deposition = the areas of the first and second electrode layers 130a and 13b formed are fixed, and it is more accurate than the conventional screen printing, so adjacent two electrode layers 3a The offset of the overlapping positioning between 13 and 130b can be less than 100 microns, so the overlapping area A can be maintained at about the standard value. Please refer to FIG. 1G. In addition to the steps of providing the base layer 11 () described above, this document can obtain the structure of the multilayer capacitor 100 shown in FIG. 16 by repeating the processes of FIGS. 1A to 1? It is composed of multiple first electrode layers 130a, multiple second electrode layers 130b, and multiple dielectric layers 14o. The first electrode layer 130a, the dielectric layer 140, the second electrode layer 130b, and the dielectric layer 140 may be sequentially stacked on the base layer 110 to form a multilayer first,

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The structure in which the second electrode layers 1 3 0 a, 1 3 0 b and the dielectric layer 1 40 are staggered, and the first electrode layer 130 a may be an even layer or an odd number layer, and the second electrode layer 13 may be an even layer or Odd-numbered layers. The standard capacitance a of the laminated capacitor 10 can be defined by the number of layers of the first and second electrode layers 130a and 130b. In addition, the top and bottom surfaces of the multilayer capacitor 100 can be covered with a cover layer 140a, 140b of a certain thickness and hardness, respectively, to protect the multilayer capacitor 100 from 110, and the cover layer 140b is also coated with a dielectric material. It is formed at the top of the multilayer capacitor 100 structure. Referring to the first figure, a pair of terminal electrodes 160a, 160b 'are also formed on both sides of the laminated capacitor 100, and are electrically connected to the first electrode layer i30a and the second electrode layer 130b, respectively, and the terminal electrode 160a The method of forming i6〇b includes spraying or coating of metal powder. Next, a surface metal layer 170 can be selectively formed on the exposed surfaces of the terminal electrodes 160a and 160b. The surface metal layer 170 can be a nickel / gold composite layer (Ni / Au layer) ^ solder layer (solder) layer) or a composite material layer such as ie free solder layer (ie free solder layer) or a single material layer, and the method of forming the surface metal layer 170 on the surfaces of the terminal electrodes 160a, 160b is, for example, an electroplating method or a method: > Dipping, etc. It is worth noting that because copper is easily oxidized, when the material of the terminal electrodes 160a, 160b is copper, the surface metal layer 17 covering the surfaces of the terminal electrodes 160a, 160b, The surface of the terminal electrodes 160a and 160b can be effectively prevented from being oxidized. The second embodiment 2A ~ 2 FIG. 2 sequentially shows a laminated circuit according to the second embodiment of the present invention.

10183twf2.ptc Page 14 594813 Case No. 91136482 V. Description of the invention (8) Sectional flow chart of the capacity process. Please refer to FIG. 2A. First, a base layer 21 is provided, and the base material may be a dielectric material. Then, a patterned first mask layer 220 is formed on the surface of the base layer 21, wherein the first mask layer 22 includes a first mask dielectric layer 222 and a first removable film 224, The first dielectric layer 2 2 2 and the first removable film 2 2 4 are sequentially stacked on the base layer 2 screen. Then referring to FIG. 2B, a first electrode layer 23 0a is formed on the surface of the base layer 210 and the surface of the first removable film 224 exposed on the first mask layer 22 by a high-speed physical metal deposition method. Since the ancient velocity physics = general deposition technology has been described in the first embodiment, it will not be described again here. Then, the first removable film 2 24 is removed, and a part of the structure of the first electrode layer 23a, 2C located on the surface of the first T = except film 2 24 is removed in conjunction. With reference to the 2D drawing, the brother J is formed by coating a dielectric material on the first dielectric layer 222 above the first mask dielectric layer 222-the dielectric layer 4050, which is 0 in / A second mask layer is formed on the -24 ^^ surface. The first layer can be named. The Γ layer 25 includes a second mask dielectric layer 252 and a 2; 4: Λ film 254, and the second The mask dielectric layer 252 and the second removable dielectric layer 24 ° ... The difference is that the second 1 #to β the first mask layer 22〇 corresponds to the two two # 2 located in the base layer 21 Figure 2: Figure: High-speed physical metal deposition, full: ΐ: 24. The first and second electrode layers 23b are exposed on the surface of the second cover film 250, and the second removable film 254 is a surface. Next, a display film 254 is removed, and the associated removal is located on the second removable film 254

594813 __Case No. 91136482 _Year_Month_Revision__ V. Part of the surface of the invention (9) The second electrode layer 230b, wherein the second electrode layer 230b and the first electrode layer 2 3 0 a are at least partially Overlap to get the structure shown in Figure 2F. Similarly, in the second embodiment of the present invention, the structure of the multilayer capacitor 2000 shown in Figure 2G can be obtained by repeating the processes of Figures 2A to 2F at least once. In addition, a pair of terminal electrodes 260a and 260b are formed on both sides of the laminated electrical layer 2000, and are electrically connected to the first electrode layer 23a and the second electrode layer 230b, respectively, and then a surface can be selectively formed. The metal layer 27Q is here to prevent the surfaces of the terminal electrodes 2 6 0 a and 2 6 0 b from being & oxidized to prevent the surfaces of the terminal electrodes 2 6 0 a and 2 6 0 b from being oxidized, so as to obtain the second η The structure of the multilayer capacitor 200 shown in the figure. From the above description, it can be known that the manufacturing process of the multilayer capacitor of the present invention is different from the conventional manufacturing process of the multilayer capacitor, so there are also breakthroughs in the application of semiconductors. In particular, it is known that the manufacturing process of the multilayer capacitor and the packaging substrate = eight lines, and then the multilayer capacitor is arranged on the packaging substrate. The difference between the manufacturing process of the capacitor & 1 ^ layer capacitor is that it can seal the base = η ~ Valence base layer, and then carry out the above process 1A ~ 1G (or 2A ~ "? Γ table ^ as a package substrate, wait until the completion of the above-mentioned multilayer capacitor production 2 ^ diagram) process f process of the subsequent package substrate . In this way, the multi-layer capacitor may not be subjected to the surface of the substrate, or may be buried inside the package substrate, and the passive components may be arranged in the package substrate. As a packaging base, the present invention utilizes high-speed physical metal deposition—the powder has a large outer diameter, so it can greatly reduce the good adhesion between the gold layer and the dielectric layer coated by the manufacturing process, and it is not easy to generate voids. (V period 'and the phenomenon of electrode (delamination), so you can control the laminated layer l0ld), the delamination capacitance value is in the standard

The thickness of the present invention does not use the partial positioning of the high-definition conventional method to form a multi-layer dielectric layer according to the number of substrates of the present invention. The dielectric layer is left and right, fixed and overlapped. 2. The base layer is encapsulated in the package. 3. The outer layer of the capacitor is formed in a multilayer capacitor. The capacitance value of the multilayer capacitor of the present invention has at least the following excellent multilayer capacitors. By changing the screen printing amount used for physical deposition, the multilayer capacitor sequence can be formed to the first to completion process. The multilayer capacitor electrode layer is high-speed physical, so it can be a good and difficult phenomenon. The process does not require the conventional sintering. Steps, so that the thickness of the electrode layer formed in such a way that the thickness uniformity ratio can be kept at 10% of the soil is accurately brushed, so the adjacent two electrode layers are at 100 microns. S process, the surface of the package substrate can be used as After an electrode layer, a dielectric layer, and a second electrode layered capacitor are manufactured, a subsequent process is performed, which uses high-speed physical metal deposition and coating with a dielectric material. The shape and dielectric layers are alternately stacked to form a metal powder coated by a laminated metal deposition technology to shorten the process cycle, and the electrode layer and the dielectric generate voids and delaminations, which helps the laminated capacitor to provide more stability. Although the present invention has been disclosed as above with two preferred embodiments, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and decorations without departing from the essence of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.

10183twf2.ptc Page 17 594813 _Case No. 91136482_ Year Month Date __ Brief Description of the Drawings 1 A ~ 1 Η The drawing sequentially shows a cross-sectional flowchart of a multilayer capacitor manufacturing process according to the first embodiment of the present invention; and 2A to 2H are cross-sectional flowcharts of a multilayer capacitor manufacturing process according to a second embodiment of the present invention. 100, 200: laminated capacitors 110, 210: base layer 120, 220: first mask layer 222: first mask dielectric layer 224: first removable film 130a, 230a: first electrode Layers 140, 240Dielectric layers 140a, 140b: cover layers 150, 250: second mask layer 252: second mask dielectric layer 254: second removable film 130b, 230b: second electrode layer 160a , 160b, 260a, 260b: terminal electrodes 170, 270: surface metal layer

10183twf2.ptc Page 18

Claims (1)

594813 _Case No. 91136482_ Amendment Date_Applicable patent scope 1 · A multilayer capacitor manufacturing process includes at least the following steps: (1) providing a base layer; (2) forming a patterned first cover layer on The surface of the base layer; (3) forming a first electrode layer on the surface of the base layer exposed by the first mask layer by means of high-speed physical metal deposition; (4) removing the first mask (5) forming a first dielectric layer on the first electrode layer and the base layer by coating a dielectric material; (6) forming a patterned second mask layer on the first layer A surface of a dielectric layer; (7) forming a second electrode layer on the surface of the first dielectric layer exposed by the second cover layer by means of high-speed physical metal deposition, wherein the second electrode layer And the first electrode layer is at least partially overlapped; (8) removing the second cover layer; and (9) forming a second dielectric layer on the second electrode layer by coating a dielectric material and Over the first dielectric layer. 2. The multilayer capacitor manufacturing process described in item 1 of the scope of patent application, further comprising repeating steps (2) to (5) at least once, wherein the first electrode layers and the second electrode layer system at least partially overlap. 3. The multilayer capacitor manufacturing process described in item 1 of the scope of patent application, further comprising repeating steps (2) to (9) at least once, wherein the first electrode layers and the second electrode layers are at least partially overlapped. 4. The multilayer capacitor manufacturing process described in item 3 of the scope of patent application 10183twf2.ptc Page 19 594813 _Case No. 91136482_Year Month Day Amendment_ 6. The scope of patent application includes repeating steps (2) to (5) once, where the first electrode layers and the second electrode layers are at least Partial overlap. 5. The multilayer capacitor manufacturing process described in item 1 of the patent application scope further includes a step (1 0): forming a pair of terminal electrodes on both sides of the first electrode layers and the second electrode layers, and respectively And electrically connected to the first electrode layers and the second electrode layers. 6. The multilayer capacitor manufacturing process described in item 5 of the patent application scope further includes a step (11): forming a surface metal layer on the exposed surfaces of the pair of terminal electrodes. 7. The multilayer capacitor manufacturing process as described in item 6 of the scope of patent application, wherein the surface metal layer is one of a nickel / gold composite layer and a solder layer. 8. The multilayer capacitor manufacturing process as described in item 1 of the scope of the patent application, wherein the high-speed physical metal deposition method is a high-speed particle solidification method, arc spray method, plasma spray method, flame spray method, and high-speed oxygen fuel One of the spray method and the cathodic arc ion sputtering method. 9. A multilayer capacitor manufacturing process, comprising at least the following steps: (1) providing a base layer; (2) forming a patterned first cover layer on a surface of the base layer, wherein the first cover layer includes a first A mask dielectric layer and a first removable film, and the first mask dielectric layer and the first removable film are sequentially stacked on the base layer; (3) high-speed physical metal In a deposition method, a first electrode layer is comprehensively formed on the surface of the base layer and the surface of the first removable film exposed by the first cover layer; 10183twf2.ptc Page 20 594813 _Case No. 91136482_Year__ Sixth, the scope of patent application (4) removes the first removable film, and the associated removal of the first located on the surface of the first removable film Part of the first electrode layer; (5) forming a first dielectric layer on the first electrode layer and the first mask dielectric layer by coating a dielectric material; (6) forming a pattern A second mask layer is on the surface of the first dielectric layer, wherein the second mask layer includes a second mask dielectric layer and a second removable film, and the second mask dielectric is The layer and the second removable film are sequentially stacked on the first dielectric layer; (7) A second electrode layer is formed on the second mask layer by a high-speed physical metal deposition method. The exposed surface of the first dielectric layer and the surface of the second removable film; (8) removing the second removable film, and removing the surface of the second removable film together; Part of the second electrode layer, wherein the second electrode layer and the first electrode layer are at least partially overlapped; and (9) coated with a dielectric material The manner, forming a second dielectric layer on the second electrode layer and the first dielectric layer. 10. The multilayer capacitor manufacturing process as described in item 9 of the scope of patent application, further comprising repeating steps (2) to (5) at least once, wherein the first electrode layers and the second electrode layer system at least partially overlap. 11. The multilayer capacitor manufacturing process described in item 9 of the scope of patent application, further comprising repeating steps (2) to (9) at least once, wherein the first electrode layers and the second electrode layers are at least partially overlapped. 12. The multilayer capacitor manufacturing process described in item 11 of the scope of patent application, further comprising repeating steps (2) to (5) once, wherein the first electrodes 10183twf2.ptc Page 21 594813 _Case No. 91136482_ Year Article _6. Patent application scope The layers and the second electrode layers at least partially overlap. 13. The multilayer capacitor manufacturing process as described in item 9 of the scope of patent application, further comprising a step (10): forming a pair of terminal electrodes on both sides of the first electrode layers and the second electrode layers, and respectively And electrically connected to the first electrode layers and the second electrode layers. 14. The multilayer capacitor manufacturing process described in item 13 of the scope of patent application, further comprising a step (11): forming a surface metal layer on the exposed surfaces of the pair of terminal electrodes. 15. The multi-layer capacitor manufacturing process described in item 14 of the scope of patent application, wherein the surface metal layer is one of a nickel / gold composite layer and a solder layer. 16. The multilayer capacitor manufacturing process as described in item 9 of the scope of patent application, wherein the high-speed physical metal deposition method is a high-speed particle solidification method, an arc spray method, a plasma spray method, a flame spray method, and a high-speed oxygen fuel. One of the spray method and the cathodic arc ion sputtering method. 10183twf2.ptc Page 22