TW594659B - Display device with de-interlaced mode - Google Patents

Display device with de-interlaced mode Download PDF

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Publication number
TW594659B
TW594659B TW91122729A TW91122729A TW594659B TW 594659 B TW594659 B TW 594659B TW 91122729 A TW91122729 A TW 91122729A TW 91122729 A TW91122729 A TW 91122729A TW 594659 B TW594659 B TW 594659B
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Taiwan
Prior art keywords
complex
plural
control signal
output control
display
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Application number
TW91122729A
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Chinese (zh)
Inventor
Jin-Rung Wu
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Explore Microelectronics Inc
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Priority to TW91122729A priority Critical patent/TW594659B/en
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Publication of TW594659B publication Critical patent/TW594659B/en

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Abstract

The present invention relates to a display device with de-interlaced mode, wherein a timing controller is mainly used to generate plural digital signals, the plural signals generate plural output control signals, so as to control a gate driver, then control a display panel to display plural full picture frames through the gate driver, wherein the timing controller comprises a programmable register module to store plural timing parameters temporarily, and a vertical/horizontal timing unit to control a timing control unit for generating plural digital signals and for outputting the control signal according to the timing setup by the timing parameters.

Description

594659 五、發明説明( 本發明<王要目的係在提供—種去交錯模式之顯示裝 置’俾能不需使用額外的緩衝器而保持畫面解析度,並能 降低產品成本。 、為達成上迷心目白勺,本發明纟交錯模式之顯示裝置, 王要包括:-顯示面板,用以顯示複數完整畫面圖框 (full picture frame ),複數畫面圖框係由複數奇數圖 框(odd-half frame )與複數偶數圖框( f:ame)所組成;以及—時序控制器,用以產生複數數位 信號,以藉由複數數位信號產生複數輸出控制信號,俾供 控制一閘極驅動器(gate driver),閉極驅動器則控制 顯示面板顯示複數完整畫面圖框,其中,複數輸出控制信 號係分為複數奇輸出控制信號與複數偶輸出控制信號,複 數奇輸出控制信號與複數偶輸出控制信號係被整合而依序 輸出,以控制該顯示面板來顯示複數奇數圖框與複數偶數 圖框而達成顯示複數畫面圖框。 由於本發明構造新穎,能提供產業上利用,且確有增 進功效,故依法申請發明專利。 【圖式簡單説明】 第1圖係本發明之功能方塊示意圖。 第2圖係本發明之信號輸出關係之第一示意圖。 弟3圖係本發明之信號輸出關係之第二示意圖。 第4圖係本發明之信號輸出關係之第三示意圖。 弟5圖係本發明之信號輸出關係之第四示意圖。 本紙張尺度通用巾國國家標準(CNS) A4規格(210X297公董) (請先閲讀背面之注意事項再填寫本頁各欄) 裝 -----訂--------41^^ I · 594659 A7 B7 五、發明説明(3 )【圖號説明】 顯不面板 時序控制器 2 垂直/水平計時單元21時序控制單元22 可程式化暫存器模組23 閘極驅動器 3 【較佳具體實施例之詳細説明】 有關本發明之較佳實施例,敬請參照第丨圖顯示之功 此方塊圖,其主要包括顯示面板丨、時序控制器2、及閘極 驅動器(gate driver) 3等主要構件。當然,一個顯示裝 置還包括其他主要功能元件,在此僅對有關本發明所提供 之功能的元件加以説明。 時序控制器2用以產生複數種數位信號,並藉由該等 複數數位信號產生複數輸出控制信號(〇ut ),以輸出至 閘極驅動器3,俾供控制顯示面板丨顯示複數完整的畫面圖 框(full Picture frame),其中,每一完整的畫面圖框 係由複數可數圖框(〇dd-half frame)與複數偶數圖框 (even_half frame )所構成,複數輸出控制信號則由複 數奇輸出控制信號與複數偶輸出控制信號Q 在時序控制器2中更包括一垂直/水平計時單元2 1、一 時序控制單元2 2、及一可程式化暫存器模組2 3。垂直/水 平計時單元2 1透過可程式化暫存器模組2 3所儲存之複數 計時參數來控制時序控制單元22產生該等數位信號,該等 數位信號包括一啓始信號(sp )、複數時脈信號 I紙張尺度適國家標準(CNS) _A4規格(210X297公爱)----- 玲η (請先閲讀背面之注意事項再填寫本頁各攔) 裝 -----訂---- ,線! 594659 A7 B7 五、發明説明(6 ) 利,俾嘉惠社會,實感德便。惟應注意的是,上述諸多實 施例僅係為了便於説明而舉例而已,本發明所主張之權利 範圍自應以申請專利範圍所述為準,而非僅限於上述實施 例〇 (請先閲讀背面之注意事項再填寫本頁各攔) 裝 ϋ ·ϋ *·ϋ ^ - ϋ «11-1 1^— ^^1 i^i an 、τ 9 本紙張尺度適用中國國家標準_ (CNS) A4規格(210X297公釐)594659 V. Description of the invention (The present invention < The main purpose of the present invention is to provide a display device of a de-interlaced mode ', which can maintain the screen resolution without using an additional buffer, and can reduce the cost of the product. It is confusing that the display device of the staggered mode of the present invention includes:-a display panel for displaying a plurality of full picture frames, the plurality of picture frames are composed of odd-half frames ) And a complex even frame (f: ame); and-a timing controller for generating a complex digital signal to generate a complex output control signal by the complex digital signal for controlling a gate driver , The closed-pole driver controls the display panel to display the complete picture frame. Among them, the complex output control signal is divided into a complex odd output control signal and a complex even output control signal. The complex odd output control signal and the complex even output control signal are integrated. And output sequentially to control the display panel to display the complex odd-numbered picture frame and the complex even-numbered picture frame to achieve the display of the complex number picture Since the present invention has a novel structure, can provide industrial use, and indeed has an enhanced effect, it applies for an invention patent in accordance with the law. [Schematic description] Figure 1 is a functional block diagram of the present invention. Figure 2 is a The first schematic diagram of the signal output relationship of the invention. The third diagram is the second diagram of the signal output relationship of the invention. The fourth diagram is the third diagram of the signal output relationship of the invention. The fifth diagram is the signal output relationship of the invention. The fourth schematic diagram. The national standard (CNS) A4 size of this paper standard (CNS) A4 (210X297) (please read the precautions on the back before filling in the columns on this page) --- 41 ^^ I · 594659 A7 B7 V. Description of the invention (3) [Illustration of drawing number] Display panel timing controller 2 Vertical / horizontal timing unit 21 timing control unit 22 Programmable register module 23 Gate Pole driver 3 [Detailed description of the preferred embodiment] For the preferred embodiment of the present invention, please refer to the block diagram shown in FIG. 丨, which mainly includes a display panel 丨, a timing controller 2, and a gate electrode. Drive iver) 3 and other major components. Of course, a display device also includes other main functional elements, only the elements related to the functions provided by the present invention will be described here. The timing controller 2 is used to generate a plurality of digital signals, and The complex digital signals generate complex output control signals (〇ut) for output to the gate driver 3 and are provided for controlling the display panel 丨 to display a complex full picture frame, wherein each complete picture frame The frame is composed of a complex countable frame (〇dd-half frame) and a complex even frame (even_half frame), and the complex output control signal is composed of a complex odd output control signal and a complex even output control signal Q in the timing controller 2 The mid-range includes a vertical / horizontal timing unit 21, a timing control unit 22, and a programmable register module 23. The vertical / horizontal timing unit 2 1 controls the timing control unit 22 to generate the digital signals through the plural timing parameters stored in the programmable register module 2 3. The digital signals include a start signal (sp), a complex number Clock signal I paper size conforms to the national standard (CNS) _A4 specification (210X297 public love) ----- Ling η (Please read the precautions on the back before filling in the blocks on this page) -, Line! 594659 A7 B7 V. Explanation of the invention (6) Benefits, benefit society, and feel good. However, it should be noted that the above-mentioned embodiments are merely examples for the convenience of description. The scope of the rights claimed in the present invention should be based on the scope of the patent application, not just the above-mentioned embodiments. (Please read the back first Please note the details on this page, and then fill in this page) Decoration ϋ ϋ * · ϋ ^-ϋ «11-1 1 ^ — ^^ 1 i ^ i an, τ 9 This paper size applies Chinese National Standard _ (CNS) A4 specifications (210X297 mm)

Claims (1)

594659 A8 B8 C8 D8 1 · 一種去x錯模式之顯示裝置,主要包括: • 一顯示面板,用以顯示複數完整畫面圖框(fun picture frame ),每一完整畫面圖框係由複數奇數圖框 (odd-half frame )與複數偶數圖框( frame )所組成;以及 一時序控制器,用以產生複數數位信號,以藉由該複 數數位信號產生複數輸出控制信號,俾供控制一閘極驅動 器(gate driver),該閘極驅動器則控制該顯示面板顯 示該複數完整畫面圖框, 其中,该複數輸出控制信號係分為複數奇輸出控制信 號與複數偶輸出控制信號,該複數奇輸出控制信號與該複 數偶輻出控制仏號係被整合而依序輸出,以控制該顯示面 板來顯示該複數奇數圖框與該複數偶數圖框而達成顯示該 複數畫面圖框。 2 ·如申請專利範圍第1項所述之顯示裝置,其中,該 複數數位#號係為一啓始信號、複數時脈信號、及複數控 制信號’該複數時脈信號、該複數控制信號、及該複數輸 出控制信號係產生於該啓始信號之後。 3 ·如申請專利範圍第2項所述之顯示裝置,其中,該 複數輸出控制信號係依據該等時脈信號而觸發,以控制諒 閘極驅動器與該顯示面板來顯示該複數完整畫面圖框,該 等輸出控制信號並依據該等控制信號截止輸出。 10 ,本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) ---------------裝·! (請先閲讀背面之注意事項再填寫本頁各攔) 訂 線594659 A8 B8 C8 D8 1 · A x-error-free display device mainly includes: • A display panel for displaying a plurality of complete picture frames. Each complete picture frame is composed of a plurality of odd picture frames. (odd-half frame) and complex even-numbered frame (frame); and a timing controller for generating a complex digital signal to generate a complex output control signal by the complex digital signal for controlling a gate driver (Gate driver), the gate driver controls the display panel to display the complex complete picture frame, wherein the complex output control signal is divided into a complex odd output control signal and a complex even output control signal, and the complex odd output control signal The system is integrated with the complex even-spoke control signal and output sequentially to control the display panel to display the complex odd-numbered frame and the complex even-numbered frame to display the complex-numbered frame. 2 · The display device according to item 1 of the scope of the patent application, wherein the number # of the plural number is a start signal, a plural clock signal, and a plural control signal 'the plural clock signal, the plural control signal, And the complex output control signal is generated after the start signal. 3. The display device according to item 2 of the scope of patent application, wherein the plural output control signal is triggered according to the clock signals to control the gate driver and the display panel to display the plural complete picture frame The output control signals are cut off according to the control signals. 10, this paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling in the blocks on this page)
TW91122729A 2002-10-02 2002-10-02 Display device with de-interlaced mode TW594659B (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100399402C (en) * 2004-09-14 2008-07-02 友达光电股份有限公司 Time sequence controller with external transmission interface and electronic product using said controller
US7634132B2 (en) 2005-04-12 2009-12-15 Realtek Semiconductor Corp. Method and apparatus of false color suppression
US7978265B2 (en) 2005-04-12 2011-07-12 Realtek Semiconductor Corp. Method and apparatus of deinterlacing
US8059920B2 (en) 2005-04-01 2011-11-15 Realtek Semiconductor Corp. Method and apparatus for pixel interpolation
US9495728B2 (en) 2006-08-24 2016-11-15 Realtek Semiconductor Corp. Method for edge detection, method for motion detection, method for pixel interpolation utilizing up-sampling, and apparatuses thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100399402C (en) * 2004-09-14 2008-07-02 友达光电股份有限公司 Time sequence controller with external transmission interface and electronic product using said controller
US8059920B2 (en) 2005-04-01 2011-11-15 Realtek Semiconductor Corp. Method and apparatus for pixel interpolation
US7634132B2 (en) 2005-04-12 2009-12-15 Realtek Semiconductor Corp. Method and apparatus of false color suppression
US7822271B2 (en) 2005-04-12 2010-10-26 Realtek Semiconductor Corp Method and apparatus of false color suppression
US7978265B2 (en) 2005-04-12 2011-07-12 Realtek Semiconductor Corp. Method and apparatus of deinterlacing
US9495728B2 (en) 2006-08-24 2016-11-15 Realtek Semiconductor Corp. Method for edge detection, method for motion detection, method for pixel interpolation utilizing up-sampling, and apparatuses thereof

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