TW591700B - Capacitor structure and the fabrication method thereof - Google Patents

Abstract

A method of forming a capacitor structure. A first dielectric layer is formed on a first conductive layer. At least one via penetrating the first dielectric layer is formed. A second conductive layer is formed on the first dielectric layer and the via is filled to form a connector. The second conductive layer is patterned to form a third conductive layer and a fourth conductive layer separated by an opening. The opening locates above the two sides of the connector. The third conductive layer locates on the connector. Then, dielectric material is filled in the opening to form a second dielectric layer. Thus, a capacitor structure having lateral capacitance is obtained.

Description

591700 V. Description of the invention (1)% The technical field to which the invention belongs The present invention relates to a structure of a capacitor and a method for manufacturing the same, and more particularly to a metal-insulation with a lateral capacitor Object-metal

Cmetal_insulatoi: Ital (MIM) capacitor structure and its manufacturing method. Prior art Capacitors are the key passive components in today's semiconductor integrated circuits. For example, capacitors are often used in mixed signal (MS) circuits, radio frequency (rf) circuits, analogs, and digital circuits. Traditional capacitor structures in integrated circuits include metal-insulator-semiconductor (MEMS) capacitors, PN junction capacitors, and polysilicon-insulator-polysilicon , PIP) capacitors. However, these conventional capacitors include at least one silicon layer as a capacitor electrode, so they have the disadvantages of higher series resistance and instability in high-frequency circuits. Therefore, in recent years, a MIMO capacitor has been developed to provide lower series resistance, low power loss, and other characteristics, which can meet the application of today's mixed-signal circuits and high-frequency circuits. FIG. 1 is a perspective view showing a conventional MIMO capacitor structure 100 (horizontal parallel plate structure). The process is to form a dielectric layer 104 on a metal lower electrode plate 102, and then form a metal upper electrode plate 106 on the dielectric layer 104. In order to enable the dielectric layer 104 to be stably formed on the metal lower electrode plate.

0503-9594twf (nl); tsmc2002-1045; jacky.ptd page 6 591700 V. Description of the invention (2) On the metal plate and the electrode plate on the metal can be formed stably on the dielectric layer 104 It is necessary to use a dielectric material capable of having excellent adhesion with metals as a capacitor dielectric layer, such as chemical vapor deposition (CVD) Si02, SiN, or SiON. However, this conventional MIM capacitor structure 100 limits the application of other high-k materials. There is also 'to increase the capacitance of the conventional MIMO capacitor structure 100, it needs to occupy a considerable layout area (dieout area) or die area (die area)' that is, the level of capacitance must be increased Directional area, however, this will affect the development of component area reduction. Therefore, how to improve the unit capacitance and use high-dielectric material (h i gh k) together has become an important subject for research and development in the industry. U.S. Patent No. 6,451,667 discloses a MIM capacitor manufacturing process. The method is characterized by forming a plurality of first metal wires embedded in an insulating substrate, and then using lithography to form trenches on both sides of the metal wires, and then deposit them. A capacitor dielectric layer is formed on the surfaces of the first metal wires, and then the trench is filled with a metal material to form a second metal wire. This forms a vertical MIM capacitor. Although this method can increase the unit capacitance, the patent does not suggest how to solve the problem when using a high dielectric (h i gh k) material without excellent adhesion to metal. U.S. Patent No. 6417535 discloses a MIM capacitor manufacturing process. The method is characterized by forming a U-shaped lower electrode plate in an insulating layer, and then forming a compliant capacitor dielectric layer on the U-shaped lower electrode plate. An upper electrode plate is formed on the capacitor layer, so as to constitute a vertical MIM capacitor. Although this method can increase the unit capacity, the patent does not propose how to solve the problem.

0503-9594twf (nl); tsmc2002-1045; jacky.ptd page 7 591700 V. Description of the invention (3) Measures should be taken when using high-k materials without excellent adhesion to metals. g β U.S. Patent Early Publication No. 2002/0093780 discloses a high-efficiency MIM capacitor structure. The structure is characterized by a plurality of vertical electrode plates 丄 j. The electrode plates are parallel to each other and constitute a vertical interval between positive and negative electrodes. Each of the capacitor structures is composed of a plurality of conductor pieces electrically connected to each other through a plug. However, the patent does not propose how to solve the problem of confronting high-k materials without high adhesion between metals. _ Kind of Capacitor Junction In view of this, the main object of the present invention is to provide a structure and a manufacturing method thereof. Another object of the present invention is to provide a method for manufacturing a metal-insulator-metal-type (MIM) capacitor junction having a lateral capacitor. Second issue: Another object of the month is to provide a capacitor structure capable of using a high-dielectric (h i σ h U Mn n ^ electric migh k) material without excellent attachment with metals and a method for manufacturing the same. According to the above purpose, the present invention provides a method for manufacturing a capacitor structure, which includes the following steps: providing a first conductor layer; forming a first dielectric layer on the first conductor layer; forming a first dielectric layer; A layer of meat passes through the first dielectric layer to expose a portion of the first dielectric layer.

591700

A conductor layer; forming a second conductor layer on the first dielectric layer and filling the acoustic window to form a connection; patterning the second conductor layer to form a third conductor layer, a first Four conductor layers and an opening for insulating and isolating the third and fourth conductor layers, wherein the opening is located above both sides of the connection line, the third conductor layer is located on the connection line, and the first A four-conductor layer is disposed on a portion of the first dielectric layer; and a second dielectric layer is formed in the opening. The present invention also provides a capacitor structure including: a first conductor layer; a first dielectric layer on the first conductor layer; a line passing through the first dielectric layer and electrically connecting the first dielectric layer EL · 4 / g, a first conductor layer vertically positioned on the connection; a third conductor layer vertically positioned on a portion of the first dielectric layer; and a first dielectric layer positioned on the first dielectric layer Between the two conductor layers and the third conductor layer. In this way, according to the MI capacitor structure of the present invention, it is not necessary to occupy an additional layout area or die area, but can effectively increase the capacitor area and increase the unit capacitance. In addition, the M I M capacitor structure of the present invention can use a high dielectric (h i gh k) material without excellent adhesion to metal, which can increase the unit capacitance, and

591700 V. Description of the invention (5) And there is no problem of unstable structure of MIM electric valley. In order to make the above and other purposes, features, and comprehensibility of the present invention, the following is specifically cited 鲂 占 者 # 办 丨 and suppress the monk: Click here for more examples of yak and seasons, and cooperate with the attached details The description is as follows: 口 Α # For implementation, please refer to FIGS. 2A to 2E, which are schematic cross-sectional views of the capacitor junction process of the present invention. It should be particularly explained here that although this embodiment takes a gold-clad-insulator-metal type (MIM) capacitor as an example, the present invention does not limit the material of the capacitor structure. First, a method for manufacturing a capacitor structure according to an embodiment of the present invention will be described. Referring to FIG. 2A, a first metal layer 21o which is a conductor is formed on a substrate 200. In the towel, the substrate 200 may include different components, such as an electric crystal, a diode, and other conventional semiconductor components (not shown). In addition, the substrate 200 may also include other metal interconnect layers (not shown). For the sake of simplicity, only a flat substrate 200 is shown here. The first metal layer 210 may be a metal layer formed by a physical vapor deposition (pvD) method or an electric ore method, such as Cu, Λ1, AiSiCu, Ti, nN, Ta,

TaN ... and so on. The thickness of the first metal layer 210 is, for example, 1000 Å (A). Secondly, referring to FIG. 2A, a first dielectric layer 22 () is formed on the first metal layer 210. Wherein, “the first dielectric layer 22 is formed by, for example, chemical vapor deposition (CVD)”, the material is, for example, § 102, SiN, or SiON, and the thickness of the first dielectric layer 220 is, for example, 2 002-500 Angstroms (A).

591700 V. Description of the invention (6) "-It is specifically stated here that, in order to enable the first dielectric layer 22o to be stably formed on the first metal layer 21o, and a second one to be formed in the future The metal layer 240 (as shown in FIG. 2C) can be firmly formed on the first dielectric layer 220. Therefore, a dielectric material capable of adhering to the metal must be used as the capacitor dielectric layer. Or dielectric), so the first dielectric layer 22 is preferably a Si02, SiN or SiON layer. Secondly, “Please refer to FIG. 2B to form at least one interlayer window (or contact window) 230 through the first dielectric layer 220 to expose part of the first metal 210 layer.” FIG. 2B is a diagram showing a plurality of layers. The via window 230 is taken as an example. The via window 230 is, for example, a via or a trench, and a forming method thereof is, for example, formed by a conventional lithography etching process. Secondly, referring to FIG. 2C, a second metal layer 240 that is a conductor is formed on the first dielectric layer 220, and the dielectric layer window 230 is filled to form a connection (or a contact plug). Plug) 25. The second metal layer 240 may be a metal layer formed by a physical vapor deposition (PVD) method or a plating method, such as Cu, Al, AlSiCu, Ti, TiN, Ta, TaN, etc. The thickness of the second metal layer 240 is, for example, loooo to 20,000 angstroms (A). Secondly, please refer to FIG. 2D. For example, a third metal layer 270, a fourth metal layer 280, and a third metal layer 270 are removed by removing a portion (ie, patterning) the second metal layer 240 through a conventional lithographic etching process. An opening 260, wherein the opening 260 is located above both sides of the connection line 250 to insulate the third metal layer 270 and the fourth metal layer 280; the third metal layer 270 is located on the connection line 250; The four metal layers 280 are located on part of the first dielectric layer 220.

II

0503-9594twf (nl); tsmc2002-1045; jacky.ptd Page 11 591700 V. Description of the invention (7)-That is, the second metal layer 240 is divided into, for example, the third metal Layer 270 and fourth metal layer 28, and the third metal layer H = and the fourth metal layer 280 are separated from each other by opening σ 26 (); The line 250 is electrically connected, and the t-layer 280 is insulated from the connection 250, the third metal layer 27o, and the first metal layer 2m =. Next, referring to FIG. 2E, a dielectric material is filled into the opening 26o, and a second dielectric layer 290 is formed between the third metal layer 270 and the bathroom layer 280. It should be particularly noted here that since the third metal layer 27 and the fourth metal layer 280 are both firmly formed on the first dielectric layer 22, this step does not need to consider the second dielectric layer too much. 29〇 Adhesion to metal, so this step can use any high dielectric material, even high dielectric (high k) material without excellent adhesion to metal, high dielectric material such as Ta2 05, SrTi03, U2 03, γ2〇3,

Hf02, Zr02, BaTi〇3, etc., fill it in the filling method 3 into the opening 32 6 0. In this way, the third metal layer 270, the second dielectric layer 290, and the fourth metal layer 280 in this step constitute a lateral MI capacitor. Furthermore, the first metal layer 2 10 and the fourth metal layer δ are electrically connected to power sources of different polarities (+/-), respectively. According to the above-mentioned process of the embodiment, the present invention also provides a metal-insulator-metal-type (MIM) capacitor structure having a lateral capacitor. Here, for convenience of explanation, the same names and symbols as those in Fig. 2E are used. The Μ Μ capacitor structure of the present invention includes: a first metal layer 210;

591700

A first dielectric layer 220 is located on the first metal layer 21o; a connection 250 'passes through the first dielectric layer 22o and is electrically connected to the first metal layer 210; a third metal layer 270 A vertical position on the connection 250; a fourth metal layer 280 on a portion of the first dielectric layer 220; and a second dielectric layer 290 on the third metal layer 270 and the first Four metal layers between 280. FIG. 3 shows an example of the top view of the capacitor structure of the present invention, but it is not a limitation of the top view outline of the capacitor structure of the present invention (only the relative positions of the third metal layer 270 and the fourth metal layer 280 are shown). The cross-sectional view of c_c ′ is shown in FIG. 2E. Referring to FIG. 3, the third metal layer 270 of the capacitor structure of the present invention is regarded as a first vertical electrode (27 °). Here, for example, it is a toothed comb structure, and the fourth metal layer 28 ° is Considered as a second straight electrode (270), for example, it is a tooth-shaped comb structure, and the first and first vertical electrodes (270, 280) are interdigitated. In addition, to explain here, please refer to FIG. 2E. In order to effectively increase the capacitance of the present invention, it is preferable to make the width t2 of the fourth metal layer 280 larger than the width t1 of the third metal layer 270, which can reduce Capacitance loss due to the formation of the second metal layer 270. Also, increase the height h of the third metal layer 270 / the fourth metal layer 280 as much as possible, so that the capacitance between the third metal layer 270 and the fourth metal layer 280 can be greatly increased (because the sidewall area is increased). Also, increase the number of the third metal layer 270 and the fourth metal layer 280 as much as possible, so that the third metal layer 270 and the fourth metal layer 28 () can be greatly increased.

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591700 V. Capacitance between inventions (9) (because the number of side walls is increased. Application example This application example is the application of the above-mentioned embodiment of the present invention to the interconnection process. The following uses Figures 4A to 4C to illustrate this application example. The process is to be special here. It is explained that the process part of this application example that is the same as or similar to the previous embodiment will not be described in detail. In addition, in Figures 4A to 4C, the symbol of the capacitor structure is the same as the previous implementation. The symbols used in the examples are the same. Please refer to FIG. 4A to provide a semiconductor substrate 400, such as a silicon wafer. The substrate 400 may contain different components, such as transistors, diodes, and other components. A known semiconductor device (not shown). In addition, the substrate 400 may also include other metal interconnect layers (not shown). In order to simplify the illustration, only a flat substrate 40 is shown here. Then, an insulating layer 402, such as a Si 02 layer, is formed on the rhyme substrate 400. Then, a first metal inlay process (here, a copper inlay process is taken as an example) and a chemical mechanical polishing (CMP) process are used to form a first layer. One A copper layer 404 and a second copper layer 406 (the second metal layer 406 is regarded as a conductor and a runner / wire line) are embedded in the insulating layer 402. Secondly, please refer to FIG. 4B and implement the above implementation. Example process (not repeated here) 'and a patterning process, and the capacitor structure C of the present invention is defined on part of the insulating layer 402 (ie, defined in a predetermined capacitor region), where The first metal layer 210 of the capacitor structure c of the present invention is electrically connected to the first copper layer 404. Refer to FIG. 4C to form an inner metal dielectric layer.

0503-9594twf (nl); tsmc2002-104; jacky.ptd 591700 V. Description of the Invention (ίο). (Intermetal dielectric layer, IMD) 408 covers the capacitor structure C. The inner metal dielectric layer 408 is, for example, a Si02 layer, a phosphorite glass layer (PSG), a borophosphosilicate glass layer (BPSG), or a fluorine-doped silicon glass layer (FSG). Figure 4C, a third copper layer 410 and a fourth copper layer 412 are formed using a conventional metal damascene process (here, a copper damascene process is taken as an example) and a chemical mechanical polishing (CMp) process (the fourth metal layer 412 is used as Are wires, rurnier / wire lines) embedded in the inner metal dielectric layer 408. Among them, the third copper layer 410 is electrically connected to the first surface of the capacitor structure c of the present invention by the first copper plug 4 1 4 passing through the inner metal dielectric layer 408. The four metal layers 280 . The fourth copper layer 412 is electrically connected to the second metal layer 406 through a second copper plug 416 passing through the inner metal dielectric layer 408 to form an interconnect structure. It should be noted here that the first copper layer 404 and the third copper layer 410 are respectively electrically connected to power supplies of different polarities (+/−). Features and advantages of the present invention The present invention provides a capacitor structure and a manufacturing method thereof. The characteristic steps include: first, forming a first dielectric layer on a first conductor layer. Then 'form at least one dielectric window through the first dielectric layer to expose a portion of the first conductive layer, layer two, and then form a second conductor layer on the first dielectric layer and fill the Φ dielectric window to form a connection . After that, the second conductor layer is patterned to form a first conductor layer, a fourth conductor layer, and an opening, wherein the openings are located above both sides of the connection line to insulate and isolate the third conductor layer from the fourth conductor layer, and the third conductor The level is on the wiring 'and the fourth conductor level is on a portion of the first dielectric layer. Pick up

Page 15 591700 V. Description of the Invention (11). A second dielectric layer is formed in the opening. In this way, a capacitor structure having a lateral capacitance is formed. In this way, according to the MIM capacitor structure of the present invention, it is not necessary to occupy an extra layout area or die area, but can effectively increase the capacitor area and increase the unit capacitance. Furthermore, the M IM capacitor structure of the present invention can use a high dielectric (high k) material that does not have excellent adhesion to metal, and can increase the unit electric valley stem 'without the problem that the M IM capacitor structure is unstable. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The protection of the invention shall be determined by the scope of the attached patent application.

591700 Circular type simple illustration Figure 1 is a perspective view of a conventional MIM capacitor structure; Figures 2A to 2E are schematic cross-sectional views of a MIif capacitor junction according to an embodiment of the present invention; and again * ^ Lance King Figure 3 shows the 4A Figure 4C is a schematic cross-sectional view of this process. An example of the top view of a capacitor structure; the clear MEMS capacitor structure is applied to the interconnection system Symbol description Known part (Figure 1) 1 0 2 ~ metal lower electrode plate 106 ~ metal upper electrode plate

100 ~ traditional ΜΙΜ capacitor structure · 104 ~ dielectric layer; part of this case (2A ~ 2Ε Figure 20 ~ substrate; '220 ~ first dielectric layer; 240 ~ second metal layer; 260 ~ opening; Figure 3) 210 ~ first metal layer; 230 ~ interlayer window; 250 ~ connection; 270 ~ third metal layer (280 ~ fourth metal layer (290 ~ second dielectric layer t1 ~ third metal) T2 of the layer ~ h of the fourth metal layer ~ the third metal layer / βρ: the first vertical electrode): the second vertical electrode) t degrees; t degrees; @the height of the metal layer.

Page 17 591700 The diagram briefly illustrates the part of this case (Figures 4A ~ 4C) 400 ~ semiconductor substrate; 404 ~ the first copper layer; C ~ the MIM capacitor structure of the case 410 ~ the third copper layer; 414 ~ the first plug; 4 0 2 ~ insulating layer; 4 06 ~ second copper layer; 408 ~ inner metal dielectric layer; 412 ~ fourth copper layer; 4 1 6 ~ second plug.

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Claims (1)

591700 6. Application Patent Scope 1. A method for manufacturing a capacitor structure, comprising the following steps: providing a first conductor layer; forming a first dielectric layer on the first conductor layer; forming at least one dielectric window passing through the first A portion of the first conductor layer is exposed from the dielectric layer; forming a second conductor layer on the first dielectric layer and filling the dielectric layer window to form a connection; patterning the second conductor layer to form a An opening is formed above both sides of the connection line; and a second dielectric layer is formed in the opening. 2. The method for manufacturing a capacitor structure according to item 1 of the scope of patent application, wherein the first conductor layer is a metal layer. 3. The method for manufacturing a capacitor structure according to item 1 of the scope of patent application, wherein the first dielectric layer is a Si02, SiN or SiON layer. 4. The method for manufacturing a capacitor structure according to item 1 of the scope of patent application, wherein the first dielectric layer is deposited on the first conductor layer by a deposition method. 5. The manufacturing method of the capacitor structure according to item 1 of the scope of the patent application, wherein the interlayer window is a hole or a trench. 6. The method for manufacturing a capacitor structure according to item 1 of the scope of patent application, wherein the second conductor layer is a metal layer. 7. The method of manufacturing a capacitor structure according to item 1 of the scope of patent application, wherein the second dielectric layer is filled with a dielectric material in the opening by a filling method. 0503-9594twf (nl); tsmc2002-1045; jacky.ptd page 19 πΐ / ΟΟ 8. The manufacturing of a capacitor structure as described in item 7 of the scope of patent application, wherein the dielectric material is a high dielectric material. ^ 9. The manufacturing of the capacitor structure as described in item 8 of the scope of the patent application, wherein the high dielectric material is Ta205, SrTi03, La20, Zr02, or "D.%." , Hf〇2 1 U. Manufacturing of a kind of electric valley structure A "Shibu Li step · Provide an insulating substrate with a first conductor layer; · The body layer forms a second conductor layer on the substrate and is electrically connected The first baffle forms a first dielectric layer on the second conductor layer; the second conductance = at least-the dielectric window passes through the -dielectric layer to expose a portion of the first dielectric layer. And filling the dielectric layer to form a third conductor layer on the first dielectric layer, and forming a connection through the window; patterning the third conductor layer to form a fourth conductor layer, a fifth conductor layer and a An opening, wherein the opening is located above both sides of the connection line to insulate the fourth and fifth conductor layers, the fourth conductor layer is located on the connection line, and the fifth conductor layer is located in part of the first conductor layer; On the dielectric layer; forming a second dielectric layer in the opening; patterning the fifth conductor layer, the fourth conductor layer, the second dielectric layer, the first dielectric layer and the second conductor Layer to form a capacitor structure on the substrate; forming an insulating layer on the substrate to cover the capacitor structure; and forming a sixth conductor layer on the insulating layer by passing through the insulation 0503-95941wf (η 1); tsmc2002-1045; j acky.ptd page 20 591700 There are 11 different layers of the layer, 11 methods, and the body layer is 12 of 13 and 14 of its plugs are electrically connected to the fifth conductor layer. During the quick change, the first conductor layer and the sixth conductor layer are respectively electrically connected. Sexual power. The first conductor layer is a metal layer in the manufacturing of the capacitor structure according to item 10 of the scope of patent application. The second conductor layer is a metal layer in the edge of the capacitor structure as described in Item 10 of the scope of patent application. .As the manufacturer of the capacitor structure described in item 10 of the patent application, the first dielectric layer is the manufacturer of the Si02 capacitor structure in the 1 iN or si0N layer. OK ... The first dielectric layer is deposited on the first dielectric layer by a deposition method. 15. The method for manufacturing a capacitor structure according to item 10 of the patent application, wherein the interlayer window is a hole or a trench. 16. The method for manufacturing a capacitor structure according to item 10 of the scope of patent application, wherein the third conductor layer is a metal layer. — 1 7. The method for manufacturing a capacitor structure as described in item No. 0 of the patent application scope, wherein the second dielectric layer is filled with a dielectric material in the opening by a filling method. 1 8. The method for manufacturing a capacitor structure as described in item 7 of the scope of the patent application, wherein the dielectric material is a high dielectric material. ... 19. The method of manufacturing a capacitor structure as described in item 8 of the scope of the patent application, wherein the high dielectric material is T a2 05, S r T i 0 3 L a2 03, γ2, Hf02, Zr02 4BaTi03. 591700 VI. Patent application scope 2 0. The method for manufacturing a capacitor structure as described in item 10 of the patent application scope, wherein the insulating layer is a Si02 layer. 21. The manufacturing method of the capacitor structure according to item 10 of the patent application scope, wherein the sixth conductor layer is a metal layer. 22. A capacitor structure comprising: a first conductor layer; a first dielectric layer on the first conductor layer; a line passing through the first dielectric layer to be electrically connected to the first conductor layer A second conductor layer on the connection line, wherein the second conductor layer is a first vertical electrode; a third conductor layer on a portion of the first dielectric layer, wherein the third conductor layer A second vertical electrode, and the first and second vertical electrodes are interdigitated; and a second dielectric layer is located between the first and second vertical electrodes. 23. The capacitor structure as described in claim 22, wherein the first conductor layer is a metal layer. 2 4. The capacitor structure according to item 22 of the scope of patent application, wherein the second conductor layer is a metal layer. 25. The capacitor structure according to item 22 of the scope of the patent application, wherein the third conductor layer is a metal layer. 2 6. The capacitor structure according to item 22 of the scope of patent application, wherein the first dielectric layer is a Si02, SiN or SiON layer. 2 7. The capacitor structure described in item 22 of the scope of patent application, wherein the 0503-9594twf (nl); tsmc2002-1045; jacky.ptd page 22 591700 6. Scope of patent application The first dielectric layer is formed on the first conductor layer by a deposition method. 2 8 · The capacitor structure described in item 22 of the scope of the patent application, wherein the second dielectric layer is filled with a dielectric material in the opening σ by a filling method, wherein, where, Zr02 or 2 9 · The dielectric materials of the galvanic and gate structures described in item 28 of the scope of patent application are high dielectric materials. < 30. As described in item 29 of the scope of patent application: Capacitor Binary High Dielectric Materials Ta205, SrTi03, La203, 2 3 2 BaTi03. 0503 -95941wf (η 1); t smc2002-1045; j acky.p td 23rd tribute