TW591676B - Base board structure with hidden capacitor - Google Patents

Abstract

A base board structure with hidden capacitor is disclosed. The base board structure is formed of a single layer or several layers of base boards with hidden capacitors. Each base board with hidden capacitor comprises several capacitor units. The traces in each capacitor unit can be connected arbitrarily in parallel or in series through the circuit connection layer above/below the base board structure, so as to be combined into various capacitors having different capacitances and bandwidths for satisfying the requirements of different circuits. Also, each capacitor unit can have the signal transmission lines for transmitting the electrical signals of the electronic devices above/below the base board structure based on different circuit designs. Therefore, the purpose of electrical signal connection can be accomplished by simple circuit layout.

Description

591676 V. Description of the invention (1) " " ------ [Technical field to which the invention belongs] The present invention relates to a substrate structure with a built-in capacitor, which is used in the integration and shrinking of electronic circuits. Hidden capacitor substrate structure. '' [Previous technology], > In order to meet the high-frequency and high-speed development needs of technology products, the signal rise time (trise time; tr) of the circuit system is getting faster and faster, and at the same time, the timing budget (Timing Budget) and noise Boundary

Margin) is getting smaller and smaller. In addition to the selection of components, the stability of the system is absolutely related to the noise immunity of the circuit (Noise I mmu n ty). Among them, the three major issues of noise suppression are reflected noise (Ref lection Noise), coupled noise (Coupled Noise), and switching noise (Switching Noise). Suppression of reflection noise (Reflection Noise) mainly must do impedance matching. To deal with | Ma He Noise (C oup 1 ed N oise) must pay attention to the control of the distance and length of parallel lines, and IC high-speed switching (turri on / turn丁 〇ff) Switching noise (or synchronous switching noise) generated by τΓ

Simultaneous Switching Noise (SSN) must rely on a large number of de-coupling capacitors or bypass capacitors to stabilize the power supply and filter high-frequency noise. However, many capacitors are thin, short, and small. The trend is to increase the interference, so these capacitors must be (the shorter the tr is, the closer the distance is) to have their effective area to place more capacitors. Make the product unable to take into account the light, and the longer the path of the current loop, the dry gas and the IC stay within a certain distance to dry fruit, that is, even if the force π substrate may be too far away, it is impossible to reach 591676

591676 Description of the invention (3) It will often cause the occupied area to be too large, which is beneficial to practicality. M # The electric constant is about 9.5, and when f ... moon shape (the dielectric of ceramic substrate ^ hanging FR-4 dielectric) The constant only A47 plus # can be widely adopted and usually must be increased to more than 100) is only 4.7, but the right one is = board two base states in development and / Ϊ two enough to be used as a capacitor material is still Capacitor technology center. The above reasons are the current built-in organic substrate = to solve these problems. The previous case provided some solutions. Chains such as Wu Guodi's patent No. 56 3 3785 use an internal connection with resistance, capacitance, and inductance. The substrate (interc〇nnect) is bonded to the wafer by means of wire bonding, and the substrate is divided into a plurality of block arrays. The parent block is a passive component, which can produce the effects of resistance, capacitance and inductance, and then use wires (Trace) each block is connected to a bonding pad (bon (i pad)) on the outer edge for remote connection of electrical signals.

Although this method provides a high-performance, high-density IC package, because of the use of trace design, it will produce unnecessary electrical and salty effects, reducing the electrical quality; and must match the chip size and pins It is not convenient to make different designs with different pin assignments. [Summary of the Invention] In view of the problems of the conventional technology above, an object of the present invention is to provide a substrate structure with a built-in capacitor. The substrate structure has wide frequency and low resistance.

Page 8 591676 V. Description of the invention (4) 杬, and the advantages of low switching noise, and the substrate structure can be directly connected to the chip to effectively reduce the number of passive capacitive elements and the rear ^: Surface adhesion technology (Surface Mount Technology; SMT). Second, because the substrate structure is closer to the wafer, it can provide better alum filtering effect, and it will not occupy the same amount of space as a stand-alone capacitor, achieving better space utilization. The substrate structure with a built-in valley is composed of a single-layer or multi-layer internal board, and each layer of the built-in capacitor substrate is composed of several capacitor units. Therefore, the user can The circuit connection layer combines the positive electrode leads and negative electrode leads connected to each capacitor unit into two or more in series, to form a variety of capacitors with different capacitance values ^ 2 for the needs of different circuits; and each capacitor The unit can have more than one signal transmission according to the same circuit design. It is: to perform the electronic components above and below the substrate structure; of =: the electrical signal connection can be achieved without complicated circuit layout, the user This substrate structure can be used as the core of a printed circuit board, and then the surface of this substrate structure can be manufactured layer by layer using the traditional printed circuit board process or Bui ld-up substrate process technology. Required circuit. In order to better understand the purpose, structural features and functions of the present invention, the detailed illustrations are shown in the following figure: v, [Embodiment] Please refer to "Figure 1" and "Figure 2", Developed for the present invention

A perspective view and a cross-sectional view of a single-layer substrate structure 100 with a built-in capacitor. The single-layer capacitor substrate 100 is composed of one or one element 111. /, J electricity is flat and the user can set a signal transmission line 1116 in the capacitor unit ι2 according to the needs of its circuit design. When a single layer of capacitor-embedded substrate structure 100 is used, the chip above it must signal the electronic components below it. During the transmission, the electrical signal can be conducted directly through this signal transmission line 111 6 without the need for complicated circuit layout to achieve the purpose of electrical signal connection. The number of signal transmission lines 111 6 can be different according to each Depends on the needs. If not, please refer to “Figure 丨” and “Figure 5” for reference. There is no need to set any signal transmission line in the power valley unit 11 13. The arrangement of the capacitor units in the single-layer built-in capacitor substrate 100 can be as shown in "Figure 1": each capacitor unit 1 1 1 is arranged in a matrix, or as shown in "Figure 3": Each capacitor unit 1 1 1 is irregularly arranged, and the arrangement manner is that the capacitor unit 111 is arranged by the user according to the required capacitance or the design of different circuits. The shape of each capacitor unit 1 is not limited to the rectangle shown in the "Figure 1", but can also be any other shape: hexagonal, octagonal, etc. The shape can be different according to the user Changes in demand. This single-layer substrate structure with built-in capacitors can shorten the bonding distance to the wafer and reduce the number of passive capacitor elements and subsequent surface mounting technology (SMT) manufacturing processes. After the production of the single-layer built-in capacitor substrate 100 is completed, each capacitor unit 1 1 1 can be connected in series or parallel by the layout of the circuit.

V. Description of the invention (6) It is intended to be combined into a suitable high-frequency bandwidth and low-resistance for different circuit requirements. For example: the number of capacitors and the number of capacitors with the same voltage source value, the user can arbitrarily combine the three non-capacitance units m in the inner-middle meeting (string each of the J board no matching. And horses) In order to reach the circuit, each capacitor cell is composed of three main field electrode layers 1111, a negative electrode layer 1112, & sandwiched by :: Fenghe: a dielectric layer 1113 in the middle of the positive and negative electrode layers m2. Positive charge: Jichuan 11 and the formula is: I material is composed of, for example: metal steel. The common capacitance of f is 0ε X (A / d) where C: capacitance value £: dielectric coefficient of the dielectric material A: area of the positive and negative electrode layers d: distance between the positive and negative electrodes, it can be known that the capacitance value is proportional to the dielectric The dielectric system of the electrical material is jj η θ ^-the distance between the electrodes is inversely proportional. Therefore, the dielectric constant of the dielectric layer is shaped by the insulating material *, and the thickness "s 1 Π 3 can be used to achieve a higher Capacitance value. As shown in the figure “%” f, “4” of the single-capacitor unit 111, and each single capacitor in the single-layer-capacity-embedded substrate structure 100, its positive electrode layer mi, negative Each of the electrode layer 1112 and the dielectric layer 1113 has a positive electrode lead hole 1 U 2a, 1 11 3a, a fixed negative electrode lead hole 111 lb, 1113b, and one or several signal transmissions.

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V. Description of the Invention (7) Wheel hole llllc, 1112c, 1113c. Each positive electrode layer 1Π1 and negative electrode layer are connected and turned on by connection. Each of the positive electrode lead holes ⑴2a, ⑴3a, and each negative in the electric layer ⑴3; the electrode lead holes 11 1 1 b, 1 1 1 3 b, and each signal transmission wheel. The wire holes J 丨 J 1 c, Π 1 2 c, and 1 11 3 c form a conductive positive electrode lead η 1 4, a negative electrode lead 111 ^ 5, and one or several parallel signal transmission lines 1U6.

It can be known from the "Figure 4" that the positive electrode lead 1U4 is only conductive with the positive electrode layer mi, and the negative electrode lead 1115 and the signal transmission line 1116 are insulated from the positive electrode layer 1111; and the negative electrode lead 1 i J 5 is only conductive with the negative electrode layer 1112, and the positive electrode lead 1114 and the signal transmission line 1116 are insulated by the electrode layer 1112. / ,, and the positive electrode lead 1114, the negative electrode lead 1115, and the signal transmission line 111 6 are pulled out from the upper and lower sides of the single-layered capacitor-embedded substrate structure for circuit layout. The position of each signal transmission line 丨 丨 丨 6 can be determined by the user according to the layout of the circuit. This signal transmission line 丨 丨 丨 6 passes through the middle of each capacitor unit 111 and does not communicate with the positive electrode layer 1111. The negative electrode layer 1112 is conductive; therefore, if a single-layer capacitor-embedded substrate structure 100 needs to transmit signals with the electronic components below it, the signal can be directly transmitted through this signal transmission line 丨 丨 丨 6 Signal conduction, without the need for complicated circuit layout to achieve electrical signal connection. Please refer to "Figure 5" and "Figure 6". This is a 3D perspective view of the substrate structure of the multilayer built-in capacitor. A cross-sectional view of a substrate structure with a plurality of single-layer built-in capacitors after stacking 100

Page 12 591676 V. Description of the invention (8) 300, and then the capacitor unit lu can be connected in parallel or in series through the layout of the line, which greatly increases the range of the capacitance value and increases the flexibility in use. Please refer to "Figure 7" as shown in the figure below. This multilayer built-in capacitor has a circuit connection layer 200 on the bottom surface. The purpose is to connect the positive electrode lead 1114 and negative electrode connected to the 2 capacitor unit ⑴. ^ Ϊ ί415, the connection and layout of the line, and each capacitor unit 111 is connected in parallel or in parallel to form a capacitor of any capacitance. On the surface of this circuit, a number of conductive bumps 210 are made on the surface of the thick inner six, which is used to draw the circuit from the multi-channel insect basin board structure 300 using the circuit connection layer 200; the chip above i 220 performs electrical signal connection. Applicable ;: Door: The package form of the substrate structure 300 with capacitors is also ⑴ i ChiT) i / package (BaU Grid Array; BGA), flip chip package

Stack Pac; e; ^^ ^ ^ t (3D bit & ge / temple packaging technology to assemble. This line: Ϊί layer :::: * is the line connection layer 2 °. Above view 'line area m is made of conductor So = there are J common wiring areas 2. 1 'The wiring of this common wiring area 2G1 = Conduction: This is = when parallel to the same common wiring line, the s phase is conductive. So when these capacitor units 1 1 1 enter but The wires that are planted on the electrode plates are directly connected to produce larger;: dots;? There will be a problem of large inductance, and m ^ is not a good connection method. ^ Ming will be connected to the same potential Electrode lead 丨 丨 i 4

591676 V. Description of the invention (9) Or the negative electrode lead 11 15 is connected to the same common wiring area 2101, for example: If only two different voltage values are applied, it can be divided into several blocks corresponding to the two The common wiring area 201 & 20b with different voltage values, the common wiring area 20a applies one of the voltage values, and the common wiring g2Olb applies the other voltage value. Therefore, please refer to "Figure 9". The circuit connection layer 2000 can be designed with different numbers and shapes of common wiring areas 2 0 1 c, 2 0 1 d, 2 according to different needs of users. 0 1 e, 2 0 1 f, for example: honeycomb, square, circular, etc., and corresponding to the common wiring area of different voltage values 20 b, 2 0 1 d, 2 0 1 e, 2 0 1 f, yes Staggered. The advantage of this common wiring area 201 is that when pulling a wire, it is only necessary to pull the wires to be connected to the same potential to the same common wiring area 20i, and then the electrical signals of the entire common wiring area 201 will be conducted. Therefore, Can effectively reduce the effect of inductance. However, the common wiring area 201 and the signal transmission line 1116 are mutually connected to each other. Therefore, the chemical transmission line 1 1 1 6 can be connected in common with each of the capacitor units 1 1 1 and 201 without passing through. A situation in which the circuit is turned on may occur. The above-mentioned single-layer capacitor-embedded substrate structure 100 or a multi-layer capacitor-embedded valley substrate,. In the structure 3 0 0, the positive electrode layer 1 1 1 1 and the negative electrode layer 1 1 1 2 can be used to produce conductive positive electrode layer 1111 and negative electrode layer 111 2 by sputtering, hafnium plating, and metal plating; and Electrical layer} 丨 丨 3 can be made by sputtering, evaporation, coating, or printing to create an insulating dielectric layer. Or, the dielectric layer 111 3 is formed by laminating an insulating sheet capacitor material, and then the upper and lower layers of the positive electrode layer 11.11 and the negative electrode layer 1 丨 2 are produced by means of copper foil lamination. Laminate and press to form this

Page 14 591676 V. Description of the Invention (ίο) Multi-layer built-in capacitor substrate structure 300. And each positive electrode layer, each negative electrode, each of the positive electrode lead holes 1112 & in the layer m2 and the dielectric layer 3: swarf each negative electrode lead hole 1111 b, 111 3b, and each signal play 4 holes 1 1 1 1 CN 111 2 C, 1 1 1 3 C, can be made by etching or drilling (dri 1 1). Another way to make the capacitor unit U1 is to sequentially fabricate the positive electrode layer 11n, the dielectric layer 1113, and the negative electrode layer 111 2 on the surface of an inorganic substrate. The material of the inorganic substrate can be ceramic, silicon, or silicon. Glass.

When ceramic is used as the material of the inorganic substrate, each of the positive electrode layer 1111 and the dielectric layer can be produced by using the developed thick film process technology or thin film process technology that has developed so far! i i 3 and the negative electrode layer i J J 2. As shown in "Figure 10", and when the silicon is used as the material of the inorganic substrate, it can be made on the surface of the silicon substrate 2 3 0 -side by using semiconductor process technology. Layer 丨 丨 丨 丨, dielectric layer 丨 丨 丨 3, and negative electrode layer L11 2 to form a wafer-type built-in capacitor substrate structure 400; this wafer-type built-in capacitor substrate structure 400 is formed by conductive bumps on its surface 21 and the electrical signals are connected to the chip 220 above it to effectively reduce the thickness of the entire module. ,

The single-layer capacitor-embedded substrate structure 100 or the multi-layer capacitor-embedded substrate structure 300 can also be applied to the layout of integrated circuits at the same time to directly form a system on chip (SOC) in semiconductor manufacturing. , Will help this substrate to integrate with other components. The substrate structure of the single-layer built-in capacitor is 100 or the base of the multi-layer built-in capacitor

Page 15591676-Fifth, the description of the invention (11) The board structure 3 0 0 can be applied to different package shapes of various chips, such as: Ball Grid Array (BGA), flip chip package (pup chip) , Wafer-level packaging (WL-csp) or three-dimensional stacking " packing (3D stack P: c) =) !; so 'can use the currently developed and mature process technology and packaging technology for production and packaging, For direct mass production. : The above are only the preferred embodiments of the present invention. They are used to limit the implementation scope of the present invention; that is, all equal changes and changes made in accordance with the application of the present invention are within the scope of the patent of the present invention. Simple illustration 591676

Fig. 1 is a perspective view of a substrate structure with a single-layer built-in capacitor of the present invention. Fig. 2 is a cross-sectional view of a substrate structure with a single-layer built-in capacitor of the present invention. Fig. 3 is a perspective view of an irregularly arranged capacitor unit. ; Θ 'Figure 4 is an exploded view of a single capacitor unit; Figure 5 is a substrate structure of a multilayer built-in capacitor; Figure 6 is a substrate junction of the multilayer built-in capacitor; Figure 7 is a substrate of the multilayer built-in capacitor; 1 side view; Figure; Photographing the connection layer of the circuit Figure 8 is a top view of the connection layer of the circuit; Figure 9 is above the honeycomb common wiring area, the picture is ... Explanation], ,, Q structure. Section 100 111 1111 1111b 1111c 1112 1112a 1112c 1113 1113a 1113b 1113c Single-layer capacitor structure built-in capacitor unit Q positive electrode layer negative electrode lead hole signal transmission wire hole negative electrode layer positive electrode lead hole signal transmission line hole dielectric layer Positive electrode lead hole Negative electrode lead hole Signal transmission line hole 591676 Brief description of the diagram 1114 Positive electrode 1115 Negative electrode 1116 Signal transmission 112 Capacitor sheet 113 Capacitor sheet 200 Line connection 201 Common connection 201a Common connection 201b Common connection 201c Common connection 201d Common connection 201e Common connection 201 f Common connection 210 Conductive bump 220 Chip 230 Silicon substrate 300 Multi-layer inner 400 Chip-type substrate structure with built-in capacitors Built-in capacitor substrate structure Leads Leads Transmission line element Line area Line area Line area Line area Line area Line block

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Claims (1)

591676 6. Scope of patent application • A substrate structure with built-in capacitors, which includes:-a built-in capacitor substrate with more than one layer, which is composed of more than one capacitor unit, with a two-tone capacitor value through the circuit layout, the The capacitor unit includes: a dielectric layer of Feng Shixin; a positive electrode layer connected to one side of the dielectric layer; a negative electrode layer connected to the other side of the dielectric layer; The electrode layer, the negative electrode layer, and the dielectric layer have a positive electrode lead hole, a negative electrode lead hole and one or more of the two, and a transmission line hole, which is connected to the positive electrode layer and the negative electrode. Layer ^ the ^ two electrical layers, each of the positive electrode lead hole, each of the negative electrode lead hole, and each of the ^ number transmission line hole to form a positive electrode lead, a negative electrode lead f =: more than a signal transmission line The positive electrode lead and the signal transmission line: the negative electrode layer is insulated, and the negative electrode lead and the signal transmission edge: the positive electrode layer is insulated, and the positive electrode lead, the negative current J, and the signal transmission line are Pull on both sides of the capacitor structure , The row circuit layout. Introduce the substrate structure with built-in capacitors described in the scope of the patent, each of the negative electrode layer and the dielectric layer has one of the following:; 2: a wire hole 'conducts and connects the positive electrode layer and the negative electrode two :: Each of the signal transmission wheel wire holes of the electrical layer forms more than one binary value. The signal transmission wheel wire system and the negative electrode layer and the; : = ,,,,,… The substrate structure of the built-in capacitors described in item 2 of the scope of patent application, which is on page 19, 591676 — ——————— 6. The scope of patent application ^^ Far positive electrode sound, " Edge negative The electrode layer and the dielectric layer are each formed with 4 holes of the signal transmission wheel such as: "". Xizheng® Γ Patent Fan Yuan No. 2 of the substrate structure with built-in capacitors, in which the holes are thorns of the two male negative electrode layers and the dielectric layers of the signal transmission line 5. Rushen, 2 diamond two's Way to form. The plate structure ^ t ^ ^ surrounds the substrate structure of the built-in capacitor as described in item 1, the base substrate-a layer of line connection layer on the side, is located at the negative electrode of the built-in capacitor ^ Ϊ, and is used to connect each capacitor unit The positive electrode leads and rows are connected in series or connected for wiring layout, and each of the capacitor units is connected to 6. If applied, a capacitor having an arbitrary capacitance value is formed. This line is connected to the substrate and structure of the built-in capacitor as described in item 5 of the bank, including the surface of the board. The printed circuit board manufacturing process is used to manufacture the substrate structure of the built-in capacitor base as described in the item ==, wherein the surface y of the capacitor substrate is manufactured in the built-in capacitor using the build-up substrate process technology. Chu R = the substrate structure of the line connecting layer member with a built-in capacitor, wherein the common wiring area connected to the positive potential of the same potential is used to connect to the common wiring area. ^ Λ or the negative electrode lead is connected to the same 9 · If a patent is applied || The board structure further includes a substrate structure with two built-in capacitors on the T substrate, the surface on the two sides of the base substrate; 2; The built-in capacitor and the negative electrode lead are connected to three ports = the positive electrode lead of the capacitor unit and the layout of the order line, each of the capacitor units is placed on α () 76 'patent application structure, and ten built-in capacitor bases are connected. Or in parallel, to form a capacitor of any capacitance. This line D applies for the substrate with built-in capacitors described in item 9 of the patent scope: The connecting layer is made on the surface of the board using a printed circuit board manufacturing process. The substrate structure of a built-in capacitor as described in item 9 of the scope of the patent application, wherein the two-way connection layer is fabricated on the surface of the built-in valley substrate by using the build-up substrate process technology. 1 2 Taxi \ 1 / Shang Xing ^ σ A. The structure of the substrate with built-in capacitors described in item 9 of the patent scope, in which the Hai Hai line connection layer includes more than one common wiring area for connecting to the same potential. The positive electrode lead or the negative electrode lead is connected to the same common wiring area. \ 3 · Eight as described in the application; the substrate structure with built-in capacitors described in item 1 of the scope of interest, wherein the dielectric layer is composed of a material with a high dielectric constant. /, \ 4 · Baru. The substrate structure of the built-in capacitor as described in the first item of the scope of the patent application, wherein the f θ clothing mode is selected from the group consisting of sputtering, evaporation, coating and printing. = · The substrate structure of the built-in capacitor as described in item 1 of the eight patent scope, which is composed of the 〃 layer 4 series which is laminated by using an insulating sheet capacitor material. For example, the substrate structure of the built-in capacitor as described in item 1 of the patent scope, wherein the method of making the layer is selected from the group consisting of sputtering, evaporation, electroplating, and copper box --- U · Zhongyanshen's patented scope of the substrate structure of the built-in capacitor, where = 乂 ′, the production method of the electrode layer is selected from the group consisting of sputtering, evaporation, electroplating, and copper foil compression. Xuanguan π W / White Page 21 591676 VI. Application for patent scope 1 8. The substrate structure with built-in capacitors as described in item 1 of the scope of patent application, wherein the positive electrode layer, the negative electrode layer and the dielectric layer each have the positive electrode lead hole. Each of the negative electrode lead holes is formed by etching. 1 9. The substrate structure with a built-in capacitor according to item 1 of the scope of the patent application, wherein each of the positive electrode lead hole and the negative electrode lead hole of the positive electrode layer, the negative electrode layer, and the dielectric layer is Formed by drilling. 2 0. The substrate structure with a built-in capacitor according to item 1 of the scope of the patent application, wherein the capacitor unit is formed on the surface of an inorganic substrate with the positive electrode layer, the dielectric layer, and the negative electrode layer. 2 1. The substrate structure with built-in capacitors as described in item 20 of the scope of patent application, wherein the inorganic substrate is one selected from the group consisting of ceramics, stone evening and glass. 2 2. According to the substrate structure with built-in capacitors described in Item 21 of the scope of patent application, when ceramic is used as the material of the inorganic substrate, it is selected from one of a combination of thick film process technology and thin film process technology to make the positive electrode. An electrode layer, the dielectric layer, and the negative electrode layer. 2 3. According to the substrate structure of the built-in capacitor as described in Item 21 of the scope of the patent application, when silicon is used as the material of the inorganic substrate, the positive electrode layer, the dielectric layer and the negative electrode are manufactured by using semiconductor process technology. Floor. Page 22