TW591676B - Base board structure with hidden capacitor - Google Patents
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591676 五、發明說明(1) "" ------ 【發明所屬之技術領域】 本發明係有關於一種具内藏電容之基板結構,應用於 電子電路進行整合縮裝時之内藏電容基板結構。 ' 【先前技術】 、 >為滿足科技產品高頻、高速化的發展需求,電路系統 的信號上升時間(Rise Time ; tr)越來越快,同時使得時 序盈餘度(Timing Budget)及雜訊邊界(N〇ise591676 V. Description of the invention (1) " " ------ [Technical field to which the invention belongs] The present invention relates to a substrate structure with a built-in capacitor, which is used in the integration and shrinking of electronic circuits. Hidden capacitor substrate structure. '' [Previous technology], > In order to meet the high-frequency and high-speed development needs of technology products, the signal rise time (trise time; tr) of the circuit system is getting faster and faster, and at the same time, the timing budget (Timing Budget) and noise Boundary
Margin )越來越小。除了元件的選用之外,系統的穩定與 否與電路的雜訊免疫(N〇 i s e I mmu n丨t y )能力有絕對的關 係,其中,雜訊抑制主要的3大課題為反射雜訊 (Ref lecti〇n Noise )、耦合雜訊(c〇upled N〇ise )以 及切換雜訊(Switching Noise)。 抑制反射雜訊(Reflection Noise)主要必須做好阻 抗匹配’對付|馬合雜訊(C 〇 u p 1 e d N 〇 i s e )必須注意平行 線距離及長度的控制,而IC高速切換(turri on/turn 丁 〇 f f )日τΓ所產生的切換雜訊(或是稱為同步切換雜訊Margin) is getting smaller and smaller. In addition to the selection of components, the stability of the system is absolutely related to the noise immunity of the circuit (Noise I mmu n ty). Among them, the three major issues of noise suppression are reflected noise (Ref lection Noise), coupled noise (Coupled Noise), and switching noise (Switching Noise). Suppression of reflection noise (Reflection Noise) mainly must do impedance matching. To deal with | Ma He Noise (C oup 1 ed N oise) must pay attention to the control of the distance and length of parallel lines, and IC high-speed switching (turri on / turn丁 〇ff) Switching noise (or synchronous switching noise) generated by τΓ
Simultaneous Switching Noise ; SSN )則必須靠大量的 解麵合電容(De-coupling Capacitor)或旁路電容 (Bypass Capaci tor )來穩定電源並過濾高頻雜訊。 但是為數眾多的電容元 薄、短、小的發展趨勢,而 擾越大,所以這些電容必須 (t r越短距離越近)才有其效 面積來擺放更多的電容,亦 件伸在在使產品無法兼顧輕、 且電流迴路的路徑越長雜气 與I C保持在一定的距離之内干 果,也就是說即使增力π基板、 可能因相距太遠而、無法達的 591676Simultaneous Switching Noise (SSN) must rely on a large number of de-coupling capacitors or bypass capacitors to stabilize the power supply and filter high-frequency noise. However, many capacitors are thin, short, and small. The trend is to increase the interference, so these capacitors must be (the shorter the tr is, the closer the distance is) to have their effective area to place more capacitors. Make the product unable to take into account the light, and the longer the path of the current loop, the dry gas and the IC stay within a certain distance to dry fruit, that is, even if the force π substrate may be too far away, it is impossible to reach 591676
591676 發明說明(3) 往會造成所佔面積太大而益實用性之情m # 電常數約9. 5,而當f… 月形(陶瓷基板之介 ^ 吊見之FR 一 4之介電常數僅A47加# 能被廣泛採用通常必須提高至1〇〇以上)僅為4.7,但右要 的有=板二 基州 在開發中並/Ϊ 两到足以被用來做為電容的材料仍 式電容技術心。以上之原因都是目前有機基板的内藏 =解決這些問題,前案提供了一些解決的方式,链 如吳國弟56 3 3785號專利,係利用一個具有電阻、電容以1^ 及電感效應的内連通基板(interc〇nnect , 採用焊線接合的方式與晶片接合,且基板分割為複數個區 塊陣列,母一區塊内為一個被動元件,而可產生電阻、電 容以及電感之效應,再利用導線(trace )將每一區塊連 接至外緣的接合墊(b〇n(i pad ),以進行電氣信號之遠 接。591676 Description of the invention (3) It will often cause the occupied area to be too large, which is beneficial to practicality. M # The electric constant is about 9.5, and when f ... moon shape (the dielectric of ceramic substrate ^ hanging FR-4 dielectric) The constant only A47 plus # can be widely adopted and usually must be increased to more than 100) is only 4.7, but the right one is = board two base states in development and / Ϊ two enough to be used as a capacitor material is still Capacitor technology center. The above reasons are the current built-in organic substrate = to solve these problems. The previous case provided some solutions. Chains such as Wu Guodi's patent No. 56 3 3785 use an internal connection with resistance, capacitance, and inductance. The substrate (interc〇nnect) is bonded to the wafer by means of wire bonding, and the substrate is divided into a plurality of block arrays. The parent block is a passive component, which can produce the effects of resistance, capacitance and inductance, and then use wires (Trace) each block is connected to a bonding pad (bon (i pad)) on the outer edge for remote connection of electrical signals.
此方式雖然提供了一種高性能、高密度的I C封裝,作 疋因為採用導線(t r a c e )的設計,會產生不必要的電咸 效應,降低了電性上的品質;且必須配合晶片大小以及針 腳排列(pin assignment )的不同來作不同的設計,在實 際製作上並不方便。 灵 【發明内容】 鑒於以上習知技術的問題,本發明之目的在於提供一 種具内藏電容之基板結構,此基板結構具有寬頻、低阻Although this method provides a high-performance, high-density IC package, because of the use of trace design, it will produce unnecessary electrical and salty effects, reducing the electrical quality; and must match the chip size and pins It is not convenient to make different designs with different pin assignments. [Summary of the Invention] In view of the problems of the conventional technology above, an object of the present invention is to provide a substrate structure with a built-in capacitor. The substrate structure has wide frequency and low resistance.
第8頁 591676 五、發明說明(4) 杬,以及低切換雜訊之優點,而且此基板結構可直接與曰 片進行接合,以有效減少被動式電容元件之數目及後^ : 表面黏著技術(Surface Mount Technology; SMT)。、 二 由於此基板結構更貼近晶片,因此,可提供更好的 矾過濾效果,且不會像獨立式的電容器必須佔有額的^ 積,達到較佳之空間利用率。 、 此具内藏電谷之基板結構是由單層或多層内办 板所組成,而每一層内藏電容基板是由數個電容單元二^ j因此,使用者可藉由此基板結構上方之線路連接層 ,將連揍至各個電容單元之正電極引線及負電極引二一 亚聯或是串聯,組合成各種具有不同電容值之電容^ 2 用於不同電路之需求;而且,每個電容單元可依使用 、 同的電路設計而具有一個以上之信號傳輸 Ϊ是::進行此基板結構上方與下方之電子元件 ;之=:可不需藉由複雜的電路佈局來達到電氣訊號連 ,使用者可藉由此基板結構作為印刷電路板中的核心展 ^、再於此基板結構之表面利用傳統印刷電路板的制 程或是增層法(Bui ld-up)基板製程技術一層一層地制= 所需之電路。 衣出 為使對本發明的目的、構造特徵及其功能有進一牛 了解’茲配合圖示詳細說明如卞: v 、 【實施方式】 請參考「第1圖」及「第2圖」所示,為本發明所研發 591676Page 8 591676 V. Description of the invention (4) 杬, and the advantages of low switching noise, and the substrate structure can be directly connected to the chip to effectively reduce the number of passive capacitive elements and the rear ^: Surface adhesion technology (Surface Mount Technology; SMT). Second, because the substrate structure is closer to the wafer, it can provide better alum filtering effect, and it will not occupy the same amount of space as a stand-alone capacitor, achieving better space utilization. The substrate structure with a built-in valley is composed of a single-layer or multi-layer internal board, and each layer of the built-in capacitor substrate is composed of several capacitor units. Therefore, the user can The circuit connection layer combines the positive electrode leads and negative electrode leads connected to each capacitor unit into two or more in series, to form a variety of capacitors with different capacitance values ^ 2 for the needs of different circuits; and each capacitor The unit can have more than one signal transmission according to the same circuit design. It is: to perform the electronic components above and below the substrate structure; of =: the electrical signal connection can be achieved without complicated circuit layout, the user This substrate structure can be used as the core of a printed circuit board, and then the surface of this substrate structure can be manufactured layer by layer using the traditional printed circuit board process or Bui ld-up substrate process technology. Required circuit. In order to better understand the purpose, structural features and functions of the present invention, the detailed illustrations are shown in the following figure: v, [Embodiment] Please refer to "Figure 1" and "Figure 2", Developed for the present invention
之單層具内藏電容之基板結構100之立體圖及剖面圖,此 單層内藏電容基板100則是由一個或是一個以 元111所組成。/ 、j电合平 而使用者可依其電路設計之需求在電容單元ιΐ2中設 置有信號傳輸線1116,當單層内藏電容之基板結構1〇〇上 方之晶片要與其下方的電子元件進行訊號之傳遞時,可直 接透過此信號傳輪線111 6進行電氣訊號之導通,而不需藉 由複雜的電路佈局來達到電氣訊號連接之目的,且信號傳 輸線111 6之數目多寡可依各別不同之需求而決定。如果沒 有此,求的話,請參考「第丨圖」及「第5圖」中所示,於 電谷單元11 3中不需設置有任何信號傳輸線丨丨1 6。 單層内藏電容基板1 〇 〇中電容單元丨丨1的排列方式可如 「第1圖」所示:各個電容單元1 1 1為矩陣式排列,或是如 「第3圖」所示:各個電容單元1 1 1為不規則之排列,其排 列方式皆是由使用者依照其所需的電容量,或是不同電路 的設計進行電容單元111之排列。而各個電容單元丨丨1之形 狀並不僅局限於「第1圖」中所示的矩形,而亦可為其他 任意形狀:六角形、八角形···等,其形狀皆可依使用者不 同的需求而進行改變。 此單層内藏電容之基板結構丨〇 〇可縮短與晶片接合距 離’並減少被動式電容元件之數目及後續表面黏著技術 (Surface Mounting Technology; SMT)的製程。 當單層内藏電容基板1〇〇製作完成之後,可再藉由電 路之佈局而將各個電容單元1 1 1進行串聯或是並聯,以任A perspective view and a cross-sectional view of a single-layer substrate structure 100 with a built-in capacitor. The single-layer capacitor substrate 100 is composed of one or one element 111. /, J electricity is flat and the user can set a signal transmission line 1116 in the capacitor unit ι2 according to the needs of its circuit design. When a single layer of capacitor-embedded substrate structure 100 is used, the chip above it must signal the electronic components below it. During the transmission, the electrical signal can be conducted directly through this signal transmission line 111 6 without the need for complicated circuit layout to achieve the purpose of electrical signal connection. The number of signal transmission lines 111 6 can be different according to each Depends on the needs. If not, please refer to “Figure 丨” and “Figure 5” for reference. There is no need to set any signal transmission line in the power valley unit 11 13. The arrangement of the capacitor units in the single-layer built-in capacitor substrate 100 can be as shown in "Figure 1": each capacitor unit 1 1 1 is arranged in a matrix, or as shown in "Figure 3": Each capacitor unit 1 1 1 is irregularly arranged, and the arrangement manner is that the capacitor unit 111 is arranged by the user according to the required capacitance or the design of different circuits. The shape of each capacitor unit 1 is not limited to the rectangle shown in the "Figure 1", but can also be any other shape: hexagonal, octagonal, etc. The shape can be different according to the user Changes in demand. This single-layer substrate structure with built-in capacitors can shorten the bonding distance to the wafer and reduce the number of passive capacitor elements and subsequent surface mounting technology (SMT) manufacturing processes. After the production of the single-layer built-in capacitor substrate 100 is completed, each capacitor unit 1 1 1 can be connected in series or parallel by the layout of the circuit.
五、發明說明(6) 意組合成適當的高頻寬低阻 用於不同電路之需纟。例如:在 及電容數目’以適 同的電壓源值,使用者即可將内 -中會冑三個不 電容單元m進行任意組合(串 J板no中的各個 上的匹配。 並馬卩),以達到電路 而每個電容單元是由三層主要 田 電極層1111、負電極層1112,&夾置於::豐合而成:正 負電極層m2中間的介電層1113。正電:極川11與 式為: I材枓所組成,例如:金屬鋼。而f容的公 〇 ε X (A/d) 其中C :電容值 £ :介電材料之介電係數 A :正負電極層之面積 d :正負電極間之距離 數,可知:電容值正比於介電材料之介電係 j j η θ ^ 一 '電極間之距離成反比的關係,因此,介電層 的介電常數的絕緣材料所形*,且採用厚度“ s 1 Π 3可以達到較高的電容值。 圖,%參f「第4圖」所示,4單-電容單元111之分解 二 而此單層内藏電容之基板結構100中的每一個電容單 ,其正電極層mi、負電極層1112及介電層1113中 」ϋ位置的地方各具有一個正電極引線孔1 U 2a、1 11 3a、 一固負電極引線孔111 lb、1113b,及一個或是數個信號傳V. Description of the invention (6) It is intended to be combined into a suitable high-frequency bandwidth and low-resistance for different circuit requirements. For example: the number of capacitors and the number of capacitors with the same voltage source value, the user can arbitrarily combine the three non-capacitance units m in the inner-middle meeting (string each of the J board no matching. And horses) In order to reach the circuit, each capacitor cell is composed of three main field electrode layers 1111, a negative electrode layer 1112, & sandwiched by :: Fenghe: a dielectric layer 1113 in the middle of the positive and negative electrode layers m2. Positive charge: Jichuan 11 and the formula is: I material is composed of, for example: metal steel. The common capacitance of f is 0ε X (A / d) where C: capacitance value £: dielectric coefficient of the dielectric material A: area of the positive and negative electrode layers d: distance between the positive and negative electrodes, it can be known that the capacitance value is proportional to the dielectric The dielectric system of the electrical material is jj η θ ^-the distance between the electrodes is inversely proportional. Therefore, the dielectric constant of the dielectric layer is shaped by the insulating material *, and the thickness "s 1 Π 3 can be used to achieve a higher Capacitance value. As shown in the figure “%” f, “4” of the single-capacitor unit 111, and each single capacitor in the single-layer-capacity-embedded substrate structure 100, its positive electrode layer mi, negative Each of the electrode layer 1112 and the dielectric layer 1113 has a positive electrode lead hole 1 U 2a, 1 11 3a, a fixed negative electrode lead hole 111 lb, 1113b, and one or several signal transmissions.
第11頁 591676Page 11 591676
五、發明說明(7) 輪線孔llllc、1112c、1113c。 藉由連接導通各個正電極層1Π1、負電極層〗 電層⑴3中之各個正電極引線孔⑴2a、⑴3a、各個負; 極引線孔11 1 1 b、1 1 1 3 b,及各個信號傳輪線孔J丨J 1 c、 Π 1 2 c、1 11 3 c,以形成一條導通的正電極引線η 1 4、負電 極引線111^5及一條或是數條互相平行的信號傳輸線1U6。V. Description of the Invention (7) Wheel hole llllc, 1112c, 1113c. Each positive electrode layer 1Π1 and negative electrode layer are connected and turned on by connection. Each of the positive electrode lead holes ⑴2a, ⑴3a, and each negative in the electric layer ⑴3; the electrode lead holes 11 1 1 b, 1 1 1 3 b, and each signal transmission wheel. The wire holes J 丨 J 1 c, Π 1 2 c, and 1 11 3 c form a conductive positive electrode lead η 1 4, a negative electrode lead 111 ^ 5, and one or several parallel signal transmission lines 1U6.
由「第4圖」中可得知··此正電極引線1U4僅與正電極 層mi相導通,而負電極引線1115及信號傳輸線1116是與 正電極層1111絕緣;而此負電極引線1 i J 5僅與負電極層 1112相導通,而正電極引線1114及信號傳輸線1116是盥 電極層1112絕緣。 /、、 而正電極引線1114、負電極引線1115及信號傳輸線 111 6疋於此單層内藏電容之基板結構丨〇 〇之上下兩侧拉 出,以進行電路之佈局。每條信號傳輸線丨丨丨6設置之位置 可由使用者依其電路之佈局而決定,此信號傳輸線丨丨丨6合 由每個電容單元111的中間通過,且不會與正電極層 曰 1111、負電極層1112相導通;因此,如果單層内藏電容之 基板結構1 0 0上方之晶片要與其下方的電子元件進行訊號 之傳遞時,可直接透過此信號傳輪線丨丨丨6進行電氣訊號之 導通,而不需藉由複雜的電路佈局來達到電氣訊號連接之 請芩考「第5圖」及「第6圖」所示,為多層内藏電容 之基板結構3 0 0的立體圖及剖面圖,將多個單層内藏電容 之基板結構1 0 0堆疊後即形成多層内藏電容之基板結構It can be known from the "Figure 4" that the positive electrode lead 1U4 is only conductive with the positive electrode layer mi, and the negative electrode lead 1115 and the signal transmission line 1116 are insulated from the positive electrode layer 1111; and the negative electrode lead 1 i J 5 is only conductive with the negative electrode layer 1112, and the positive electrode lead 1114 and the signal transmission line 1116 are insulated by the electrode layer 1112. / ,, and the positive electrode lead 1114, the negative electrode lead 1115, and the signal transmission line 111 6 are pulled out from the upper and lower sides of the single-layered capacitor-embedded substrate structure for circuit layout. The position of each signal transmission line 丨 丨 丨 6 can be determined by the user according to the layout of the circuit. This signal transmission line 丨 丨 丨 6 passes through the middle of each capacitor unit 111 and does not communicate with the positive electrode layer 1111. The negative electrode layer 1112 is conductive; therefore, if a single-layer capacitor-embedded substrate structure 100 needs to transmit signals with the electronic components below it, the signal can be directly transmitted through this signal transmission line 丨 丨 丨 6 Signal conduction, without the need for complicated circuit layout to achieve electrical signal connection. Please refer to "Figure 5" and "Figure 6". This is a 3D perspective view of the substrate structure of the multilayer built-in capacitor. A cross-sectional view of a substrate structure with a plurality of single-layer built-in capacitors after stacking 100
第12頁 591676 五、發明說明(8) 30 0,再藉由線路之佈局可將電容單元lu進行並聯或是串 聯’大幅增加電容值的範圍,增加使用上的靈活性。 請參考「第7圖」所示’此多層内藏電容之基板結構 下一側之表面具有線路連接層200,其目的是用以將 2電容單元⑴所連接出來的正電極引線1114及負電極將 ^Ϊ ί415,行線路的連接與佈局,將各個電容單元111進 或曰是並聯,以組成任意電容值之電容。而此線路連 厚內歲i六之表面製作有一些導電凸塊210,用以將此多 i路虫盆板結構3〇0利用線路連接層2 0 0所拉出來的 線路;i上方的晶片220進行電氣訊號之連接。 可適;:門:ίι ??藏電容之基板結構300之封裝形態亦 ⑴ i ChiT) i/裝(BaU Grid Array; BGA)、覆晶封裝Page 12 591676 V. Description of the invention (8) 300, and then the capacitor unit lu can be connected in parallel or in series through the layout of the line, which greatly increases the range of the capacitance value and increases the flexibility in use. Please refer to "Figure 7" as shown in the figure below. This multilayer built-in capacitor has a circuit connection layer 200 on the bottom surface. The purpose is to connect the positive electrode lead 1114 and negative electrode connected to the 2 capacitor unit ⑴. ^ Ϊ ί415, the connection and layout of the line, and each capacitor unit 111 is connected in parallel or in parallel to form a capacitor of any capacitance. On the surface of this circuit, a number of conductive bumps 210 are made on the surface of the thick inner six, which is used to draw the circuit from the multi-channel insect basin board structure 300 using the circuit connection layer 200; the chip above i 220 performs electrical signal connection. Applicable ;: Door: The package form of the substrate structure 300 with capacitors is also ⑴ i ChiT) i / package (BaU Grid Array; BGA), flip chip package
Stack Pac ;e;^^ ^ ^ t (3D 咬& ge/寺封裝技術進行組裝。 此線:Ϊί層:。::*為線路連接層2°。之上視圖’ 線區m是由導體所=有J個共同接線區2。1 ’此共同接 區2G1之線路= 導:此以=到同一塊共同接線 行並聯時,、s 相導通。以在當這些電容單元1 1 1進 但是;種於電極板之導線直接連接起來, 產生較大的;:點;;?會有電感較大的問題產生,進而 m ^ 不疋一種良好的連接方法。 ^明將要連接至相同電位之正電極引線丨丨i 4Stack Pac; e; ^^ ^ ^ t (3D bit & ge / temple packaging technology to assemble. This line: Ϊί layer :::: * is the line connection layer 2 °. Above view 'line area m is made of conductor So = there are J common wiring areas 2. 1 'The wiring of this common wiring area 2G1 = Conduction: This is = when parallel to the same common wiring line, the s phase is conductive. So when these capacitor units 1 1 1 enter but The wires that are planted on the electrode plates are directly connected to produce larger;: dots;? There will be a problem of large inductance, and m ^ is not a good connection method. ^ Ming will be connected to the same potential Electrode lead 丨 丨 i 4
591676 五、發明說明(9) 或是負電極引線11 15連接到相同的共同接線區2〇1,例如: 僅要施加兩個不同的電壓值,則可區分為數塊分別相對應 於這兩個電壓值之不同的共同接線區2〇1&、2〇ib,共同接 線區20 la施加其中一個電壓值,而共同接線g2〇lb則是施 加另一個電壓值。 因此,請參考「第9圖」所示,在線路連接層2〇〇上可 依照使用者不同的需求而設計為不同數目、不同形狀之共 同接線區2 0 1 c、2 0 1 d、2 0 1 e、2 0 1 f,例如:蜂巢式、方 形、圓形等,且對應於不同電壓值之共同接線區2〇卜、 2 0 1 d、2 0 1 e、2 0 1 f,是交錯排列的。 此共同接線區2 0 1之優點在於:拉線時只需將要連接至 相同電位之導線拉到同一塊共同接線區2 〇 i,則整塊共同 接線區201之電氣信號即會導通,因此,可有效降低電感 的效應。然而,此共同接線區2〇1和信號傳輸線1116是互 相、、、巴、、彖的,因此,化號傳輸線1 1 1 6可由各個電容單元1 1 1 與共同接線,201中通過,而不會產生電路導通的情形。 而上述單層内藏電容之基板結構1〇〇或是多層内藏電 谷之基板、、、。構3 0 0中,正電極層1 1 1 1和負電極層1 1 1 2可利 用濺鍍、瘵鍍、電鍍金屬的方式製作出導電的正電極層 1111和負電極層111 2 ;而介電層}丨丨3則可利用濺鍍、蒸 鍍、塗,或是印刷的方式製作出一層絕緣的介電層丨丨丨3。 或是利用絕緣性片狀電容材料經過壓合形成此介電層 111 3,再利用銅箔壓合的方式製作出上下兩層正電極層 11.11和負電極層1丨丨2,經由多次的層疊及壓合即可形成此591676 V. Description of the invention (9) Or the negative electrode lead 11 15 is connected to the same common wiring area 2101, for example: If only two different voltage values are applied, it can be divided into several blocks corresponding to the two The common wiring area 201 & 20b with different voltage values, the common wiring area 20a applies one of the voltage values, and the common wiring g2Olb applies the other voltage value. Therefore, please refer to "Figure 9". The circuit connection layer 2000 can be designed with different numbers and shapes of common wiring areas 2 0 1 c, 2 0 1 d, 2 according to different needs of users. 0 1 e, 2 0 1 f, for example: honeycomb, square, circular, etc., and corresponding to the common wiring area of different voltage values 20 b, 2 0 1 d, 2 0 1 e, 2 0 1 f, yes Staggered. The advantage of this common wiring area 201 is that when pulling a wire, it is only necessary to pull the wires to be connected to the same potential to the same common wiring area 20i, and then the electrical signals of the entire common wiring area 201 will be conducted. Therefore, Can effectively reduce the effect of inductance. However, the common wiring area 201 and the signal transmission line 1116 are mutually connected to each other. Therefore, the chemical transmission line 1 1 1 6 can be connected in common with each of the capacitor units 1 1 1 and 201 without passing through. A situation in which the circuit is turned on may occur. The above-mentioned single-layer capacitor-embedded substrate structure 100 or a multi-layer capacitor-embedded valley substrate,. In the structure 3 0 0, the positive electrode layer 1 1 1 1 and the negative electrode layer 1 1 1 2 can be used to produce conductive positive electrode layer 1111 and negative electrode layer 111 2 by sputtering, hafnium plating, and metal plating; and Electrical layer} 丨 丨 3 can be made by sputtering, evaporation, coating, or printing to create an insulating dielectric layer. Or, the dielectric layer 111 3 is formed by laminating an insulating sheet capacitor material, and then the upper and lower layers of the positive electrode layer 11.11 and the negative electrode layer 1 丨 2 are produced by means of copper foil lamination. Laminate and press to form this
第14頁 591676 五、發明說明(ίο) 多層内藏電容之基板結構3 0 0。而各層正電極層、負 電,層m2與介電層⑴3中之各個正電極引線孔1112& : 屑於\各個負電極引線孔1111 b、111 3b,以及各個信號 剧4孔1 1 1 1 C N 111 2 C、1 1 1 3 C,均可利用蝕刻或是鑽孔 (d r i 1 1 )的方式製作出各個穿孔。 而另一種製作出電容單元U1的方式,是在一個無機 基板之表面依序製作出正電極層lln、介電層1113及負電 極層111 2,而此無機基板之材料可選用陶瓷、矽或 璃。Page 14 591676 V. Description of the Invention (ίο) Multi-layer built-in capacitor substrate structure 300. And each positive electrode layer, each negative electrode, each of the positive electrode lead holes 1112 & in the layer m2 and the dielectric layer 3: swarf each negative electrode lead hole 1111 b, 111 3b, and each signal play 4 holes 1 1 1 1 CN 111 2 C, 1 1 1 3 C, can be made by etching or drilling (dri 1 1). Another way to make the capacitor unit U1 is to sequentially fabricate the positive electrode layer 11n, the dielectric layer 1113, and the negative electrode layer 111 2 on the surface of an inorganic substrate. The material of the inorganic substrate can be ceramic, silicon, or silicon. Glass.
、當採用陶瓷作為無機基板之材料時,可利用目前已發 展成熟之厚膜製程技術或是薄膜製程技術製作出每一層正 電極層1111、介電層! i i 3及負電極層i J J 2。 曰 、、凊芩考「第1 〇圖」所示,而當採用矽作為無機基板之 材^料日守,可以在矽基板2 3 0 —側之表面利用半導體製程技 術製作出每一層正電極層丨丨丨丨、介電層丨丨丨3及負電極層 L11 2,形成一個晶片型内藏電容基板結構400 ;此晶片型内 藏電容基板結構40 0係藉由其表面之導電凸塊21〇而與其上 方的晶片220進行電氣信號之連接,以有效地減少整個模 組之厚度。 、When ceramic is used as the material of the inorganic substrate, each of the positive electrode layer 1111 and the dielectric layer can be produced by using the developed thick film process technology or thin film process technology that has developed so far! i i 3 and the negative electrode layer i J J 2. As shown in "Figure 10", and when the silicon is used as the material of the inorganic substrate, it can be made on the surface of the silicon substrate 2 3 0 -side by using semiconductor process technology. Layer 丨 丨 丨 丨, dielectric layer 丨 丨 丨 3, and negative electrode layer L11 2 to form a wafer-type built-in capacitor substrate structure 400; this wafer-type built-in capacitor substrate structure 400 is formed by conductive bumps on its surface 21 and the electrical signals are connected to the chip 220 above it to effectively reduce the thickness of the entire module. ,
此單層内藏電容之基板結構100或多層内藏電容之基 板結構3 0 0亦可同時應用於積體電路之佈局中,以於半導 體製知中直接形成系統晶片(System on Chip; SOC),將 有助於此基板於其他元件之整合。 此單層内藏電容之基板結構1〇〇或多層内藏電容之基The single-layer capacitor-embedded substrate structure 100 or the multi-layer capacitor-embedded substrate structure 300 can also be applied to the layout of integrated circuits at the same time to directly form a system on chip (SOC) in semiconductor manufacturing. , Will help this substrate to integrate with other components. The substrate structure of the single-layer built-in capacitor is 100 or the base of the multi-layer built-in capacitor
第15頁 591676 - 一 五、發明說明(11) 板結構3 0 0可應用於各種晶片之不同封裝形_,例如:球閘 陣列封裝(Ball Grid Array; BGA)、覆晶封裝(pup Chip)、晶圓級封裝(WL —csp)或是三維堆疊封"裝(3D stack P:c】=)!;因此’即可利用目前已發展成熟的的製程技 術及封裝技術進行製作與封裝,以直接進行量產。 :上所述者,僅為本發明其中的較佳實施例而已 =用來限定本發明的實施範圍;即凡依本發明申請 ^ 圍所作的均等變化與㈣,皆為本發明專利範圍所涵罢钝 591676 圖式簡單說明Page 15591676-Fifth, the description of the invention (11) The board structure 3 0 0 can be applied to different package shapes of various chips, such as: Ball Grid Array (BGA), flip chip package (pup chip) , Wafer-level packaging (WL-csp) or three-dimensional stacking " packing (3D stack P: c) =) !; so 'can use the currently developed and mature process technology and packaging technology for production and packaging, For direct mass production. : The above are only the preferred embodiments of the present invention. They are used to limit the implementation scope of the present invention; that is, all equal changes and changes made in accordance with the application of the present invention are within the scope of the patent of the present invention. Simple illustration 591676
第1圖為本發明之單層内藏電容之基板結構的立體圖· 第2圖為本發明之單層内藏電容之基板結構的剖面圖·’ 第3圖為不規則排列之電容單元的立體圖; Θ ’ 第4圖為單一電容單元之分解圖; 第5圖為多層内藏電容之基板結構 第6圖為多層内藏電容之基板結 -圖; 第7圖為多層内藏電容之基板沾1面圖; 圖; 攝結合線路連接層 第8圖為線路連接層之上視圖; 第9圖為蜂巢式共同接線區之上 ,圖為…内藏電容之基二圖槿及 【圖式符號說明】 、、、Q構。 之剖面 100 111 1111 1111b 1111c 1112 1112a 1112c 1113 1113a 1113b 1113c 單層内藏電容之基板結構 電容單元 Q 正電極層 負電極引線孔 信號傳輪線孔 負電極層 正電極引線孔 信號傳輸線孔 介電層 正電極引線孔 負電極引線孔 信號傳輸線孔 591676 圖式簡單說明 1114 正 電 極 1115 負 電 極 1116 信 號 傳 112 電 容 單 113 電 容 單 200 線 路 連 201 共 同 接 201a 共 同 接 201b 共 同 接 201c 共 同 接 201d 共 同 接 201e 共 同 接 201 f 共 同 接 210 導 電 凸 220 晶 片 230 矽 基 板 300 多 層 内 400 晶 片 型 藏電容之基板結構 内藏電容基板結構 引線 引線 輸線 元 元 接層 線區 線區 線區 線區 線區 線區 線區 塊Fig. 1 is a perspective view of a substrate structure with a single-layer built-in capacitor of the present invention. Fig. 2 is a cross-sectional view of a substrate structure with a single-layer built-in capacitor of the present invention. Fig. 3 is a perspective view of an irregularly arranged capacitor unit. ; Θ 'Figure 4 is an exploded view of a single capacitor unit; Figure 5 is a substrate structure of a multilayer built-in capacitor; Figure 6 is a substrate junction of the multilayer built-in capacitor; Figure 7 is a substrate of the multilayer built-in capacitor; 1 side view; Figure; Photographing the connection layer of the circuit Figure 8 is a top view of the connection layer of the circuit; Figure 9 is above the honeycomb common wiring area, the picture is ... Explanation], ,, Q structure. Section 100 111 1111 1111b 1111c 1112 1112a 1112c 1113 1113a 1113b 1113c Single-layer capacitor structure built-in capacitor unit Q positive electrode layer negative electrode lead hole signal transmission wire hole negative electrode layer positive electrode lead hole signal transmission line hole dielectric layer Positive electrode lead hole Negative electrode lead hole Signal transmission line hole 591676 Brief description of the diagram 1114 Positive electrode 1115 Negative electrode 1116 Signal transmission 112 Capacitor sheet 113 Capacitor sheet 200 Line connection 201 Common connection 201a Common connection 201b Common connection 201c Common connection 201d Common connection 201e Common connection 201 f Common connection 210 Conductive bump 220 Chip 230 Silicon substrate 300 Multi-layer inner 400 Chip-type substrate structure with built-in capacitors Built-in capacitor substrate structure Leads Leads Transmission line element Line area Line area Line area Line area Line area Line block
I 第18頁I Page 18
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