TW587333B - Semiconductor device with reduced parasitic capacitance between impurity diffusion regions - Google Patents

Semiconductor device with reduced parasitic capacitance between impurity diffusion regions Download PDF

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TW587333B
TW587333B TW092105956A TW92105956A TW587333B TW 587333 B TW587333 B TW 587333B TW 092105956 A TW092105956 A TW 092105956A TW 92105956 A TW92105956 A TW 92105956A TW 587333 B TW587333 B TW 587333B
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region
layer
impurity diffusion
trench
impurity
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TW092105956A
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TW200305281A (en
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Yuji Asano
Morio Katou
Takao Setoyama
Toshihiko Fukushima
Kazuhiro Natsuaki
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Fujitsu Ltd
Sharp Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02016—Circuit arrangements of general character for the devices
    • H01L31/02019—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02024—Position sensitive and lateral effect photodetectors; Quadrant photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration

Abstract

A first layer is formed on an underlying substrate having a surface layer made of semiconductor of a first conductivity type. The first layer is made of semiconductor having a resistance higher than that of the surface layer. A first impurity diffusion region of a second conductivity type is formed in a partial surface region of the first layer. The first impurity diffusion region does not reach the surface of the underlying substrate. A second impurity diffusion region of the first conductivity type is disposed in the first layer and spaced apart from the first impurity diffusion region. The second impurity diffusion region reaches the surface of the underlying substrate. A separation region is disposed between the first and second impurity diffusion regions. The separation region comprises a trench formed in the first layer and dielectric material disposed at least in a partial internal region of the trench.

Description

587333 玖、發明說明 (發明說明應叙明：發明所屬之技術領域、先前技術、内容、實施方式及圓式簡單說明） 【發明所屬之^技術領域】 相關申請案對照 本申請案係以於2002年3月22曰提出申請之曰本專 5利申凊案第2002-81041號案為基礎，其之整個内容係被併 合於此作為參考。 發明領域 本發明係有關於一種半導體元件，更特別地，係有關 於一種於被形成在一半導體基體上之兩個相鄰之雜質擴散 10 區域間具有降低寄生電容的半導體元件。587333 发明 Description of the invention (The description of the invention should state: the technical field, prior art, content, embodiments, and brief explanations of the invention) The application filed on March 22, 2002 was based on the case No. 2002-81041 of the 5th Lishenyuan Case, the entire contents of which are incorporated herein by reference. FIELD OF THE INVENTION The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having reduced parasitic capacitance between two adjacent impurity diffusion regions 10 formed on a semiconductor substrate.

【先前技；J 發明背景 第11A圖是為一光電二極體的橫截面圖，該光電二極 體是為一種光敏元件（photo sensor)。在一 p-型矽基體100 15 的表面上，由η·型石夕製成的一蟲晶層（epitaxial layer) 101係 被形成。在该η-型蠢晶層101的表面上，一場氧化薄膜 102係被形成俾可界定數個有源區域。 在一個有源區域（在第11Α圖之中央區域的有源區域) 中，數個η-型陰極區域1〇3係相互地間隔一定的距離來被 20 形成。在兩個相鄰的陰極區域103之間，一個p-型分隔區 域1〇4係被形成。形成有該等陰極區域103與分隔區域 104之该有源區域的表面係由一防反射薄膜1 〇5覆蓋。 在與該等形成有陰極區域103之有源區域相鄰之該等 有源區域（在第11Α圖中之右和左側的有源區域）中之每一 7 587333 玖、發明說明 者中，一 P-型陽極導線區域106係被形成。該陽極導線區 域106的底部係到達該p_型矽基體1〇〇。 該陰極區域103與p-型矽基體1〇〇構成一光電二極體 。該p-型矽基體100作用如該光電二極體的陽極。 5 由於光敏元件具有光電轉換功能，如此的光電二極體 係被廣泛地使用作為要與典型為像DVD和CD般之光碟之 光電轉換裝置一起使用的光學檢拾裝置。由於雷射光束的 波長變彳于較短’要與光碟一起使用的光敏元件係被希望以 高速運作。為了實現穩定的高速運作，係希望降低在該光 10 敏元件上之不同類型的寄生電容及防止漏電流。 在第11A圖中所示的光敏元件具有在該陰極區域1〇3 與相鄰之陽極區域106之間、在該陰極區域103與型矽 基體100之間及在該陰極103與分隔區域1〇4之間的寄生 電容。這些寄生電容係被希望降低俾可確保穩定的高速運 15 作。 第11B圖疋為寄生電容被部份地減少之習知光敏元件 的橫截面圖。在該陰極區域103與陽極導線區域1〇6之間 ，一溝渠108係被形成通過該埸氧化薄膜1〇2，該溝渠係 到達該P-型矽基體100的表面層。一氧化矽薄膜係形成於 2〇該溝渠1〇8的底部和内側壁上，而且多晶矽係被填注於該 溝渠108内。 一個P-型高雜質濃度區域109係被形成於與該溝渠 108接觸之η-型磊晶層1〇1和化型矽基體1〇〇的一區域中 。這個ρ-型南雜質濃度區域1〇9防止漏電流經該溝渠 8 587333 玖、發明說明 之底部的流動。 由於具有比石夕之介電常數低之介電常數的薄氧化薄膜 係形成於該溝渠108的側壁上，於該陰極區域1〇3與陽極 ， 導線區域106之間的寄生電容係能夠被降低。 ， 5 雖然在第11B圖中所示之光敏元件之陰極區域103與 陽極導線區域106之間的寄生電容係能夠被降低，在該陰 極區域103與p-型矽基體1〇〇和在該陰極區域ι〇3與分隔 區域104之間的該等寄生電容係無法被降低。 鲁 由於該p-型尚雜質濃度區域1〇9係被形成於該溝渠 10 1〇8四周，寄生電容係被新近形成於該陰極區域1〇3與卜 型高雜質濃度區域109之間。 C發明内容:J 發明概要 本發明之目的是為提供一種於兩個具有相反之導電性 15類型之雜質擴散區域間具有降低寄生電容的半導體元件。 根據本發明之一特徵，一種半導體元件係被提供，該 鲁 半導體元件包含：一底層基體，該底層基體具有至少一個 表面層係由具有第一導電性類型的半導體製成；一第一層 · ,該第一層係形成於該底層基體上或之上而且係由具有比 · 20該底層基體之表面層之電阻高之電阻的半導體製成；一第 一雜質擴散區域，該第一雜質擴散區域係形成於該第一層 的部份表面區域而且係摻雜有具有與該第一導電性類型相 反之第二導電性類型的雜質，該第一雜質擴散區域不到達 該底層基體的表面；一具有第二導電性類型的第二雜質擴 9 587333 玖、發明說明 散區域，該第二雜質擴散區域係被置放於該第一層而且係 與该第一雜質擴散區域在平面方向上相隔一定的距離，該 第二雜質擴散區域係到達該底層基體的表面；及一第一分 隔區域，該第一分隔區域係置於該第一與第二雜質擴散區 ， 5域之間而且係包含一個形成於該第一層内的溝渠與至少置 於該溝渠之部份内部區域的介電材料。 具有高電阻的第一層係設置於該第一雜質擴散區域與 底層基體之間。在該第一雜質擴散區域與底層基體之間的 · 寄生電容係因此能夠被降低。由於介電材料係設置於構成 10該第一分隔區域的溝渠中，在該第一與第二離質擴散區域 之間的寄生電容係能夠被降低。 圖式簡單說明 第1圖是為一第一實施例之光敏元件的平面圖。 第2圖是為該第一實施例之光敏元件的橫截面圖。 15 第3圖是為顯示在該第一實施例之光敏元件之溝渠之 旁邊沿著深度方向之雜質濃度分佈的圖表。 · 第4圖是為顯示一個在該第一實施例之光敏元件之一 分隔區域與該溝渠之間之連接區域的橫截面圖。 ‘ 第5圖是為一第二實施例之光敏元件的平面圖。 · 20 第6圖是為一第三實施例之光敏元件的平面圖。 第7圖是為一第四實施例之光敏元件的平面圖。 第8圖是為一第五實施例之光敏元件的平面圖。 第9圖是為一第六實施例之光敏元件的平面圖。 第10A至i〇G圖是為描繪製造具有與雙極性電晶體整 10 587333 玖、發明說明 合在一起之該第一實施例之光敏元件之半導體元件之方法 的橫截面圖。 第11A和11B圖是為習知光敏元件的橫截面圖。 C實施方式；1 5 較佳實施例之詳細說明 第1圖是為本發明之第一實施例之半導體光敏元件的 平面圖。具有與正方形之外圍一致之平面形狀的一溝渠2 係設置於一半導體基體的表面層上。一分隔區域3連接由 該溝渠2所界定之正方形之相對之兩側的中心俾可把該溝 10 渠2的内部分隔成四個區域。該分隔區域3的末端緊靠該 溝渠2的側壁。 陰極區域la至Id係配置於由該分隔區域3所分隔的 四個區域。該等陰極區域la至ld中之每一者係被設置與 該溝渠2和分隔區域3相隔一定的距離。該等陰極區域“ 15至ld和分隔區域3的表面係由一個會在稍後作說明的防反 射薄膜覆蓋。電極導線開孔4a至4d係對應於該等陰極區 域la至Id來被形成通過該防反射薄膜及在該等陰極區域 1 a至1 d的内部。 一陽極導線區域5包圍該溝渠2的外部。另—溝渠6 20包圍该陽極導線區域5的外部。 第2圖是為沿著在第i圖中所示之點線入2_八2的橫截 面圖。在具有i X 10H到i χ 1〇1W之雜質濃度之p型石夕 ^ 的表面層中’ P-型雜質係被摻雜俾可形成-個具有 大約…之顛峰漢度的p_型高雜質濃度層u。在 11 587333 玖、發明說明 這P-型高雜質濃度層11上，一 p_型磊晶層12係被形成， 忒P-型磊晶層12具有10至2〇μηι的厚度且在其之上表面 側具有相等於或低於1 X l〇14cm-3的ρ_型雜質濃度。在該 Ρ-型磊晶層12上，一 η-型磊晶層13係被形成，該η_型磊 ' 5晶層13具有大約5 X l〇15cm·3的雜質濃度和〇·8到2μηι的 厚度。 在该η-型磊晶層13的表面上，一場氧化薄膜15係被 形成來界定數個有源區域。 · 在第2圖中所示之中央有源區域中的η_型蠢晶層 10中，該等η-型陰極區域U和lb係被形成。雖然未在第2 圖中描繪，該等陰極區域lc和ld亦被形成於這有源區域 中。該等陰極區域la-ld是為摻雜有磷的n_型雜質擴散區 域而且具有1 X 1015到1 x 1020cm-3的雜質濃度。該等陰極 區域la至Id係到達該p-型磊晶層12的上表面。陰極區域 15 U至Id未到達該P-型磊晶層12之上表面的結構亦可以被 應用。 Φ 於在該等陰極區域la與lb之間的n_型磊晶層13中， 分隔區域3係被形成。該分隔區域3是為摻雜有硼的p—型 · 雜質擴散區域而且具有1 X 1〇16到丨x 1〇2〇cm-3的雜質濃度 · 20 。該分隔區域3係電氣地分隔該等陰極區域la和lb並且 防止漏電流在它們之間流動。最好的是，該分隔區域3的 深度係與該等陰極區域la-Id的深度相同或者較淺。 該防反射薄膜16係被形成於該等在其中係形成有陰極 區域la和lb之有源區域的表面上。該防反射薄膜16具有 12 587333 玖、發明說明 5 10 15 20 有一氧切薄膜和-氮切薄膜的兩層結構俾可降低相對 於在接收波長範圍内之光線的反射率。 ，該等陽極導線區域5係被形成於該等相鄰於在其中係 形成有陰極區域13和lb之有㈣域的_區域卜該陽 極導線區域5是為摻雜有硼的p型雜f擴散區域而且具有 ，至i X 的雜質濃度。該陽極導線區域5從 该n-型遙晶層13的上表面延伸到該卜型高雜質漠度層11 。如將於稍後作說明’該陽極導線㈣5係藉由兩個離子 檀入處理來被形成…個在形成該n_魏晶層13之前而 另一個在形成該η-型磊晶層13之後。 —逆向偏壓電壓係被施加於該陰極區域u與陽極導線 區域5之間及於該陰極區域lb與陽極導線區域5之間。 该溝渠2係被形成於該等在其中係設置有陰極區域ι& 和lb的有源區域與該在其中係設置有陽極導線區域5的有 源區域之間。另-溝渠6係被形成俾可與該溝渠2 一起包 圍該陽極導線區域5。該等溝渠2和6延伸到稍微比該在 P-型兩雜質濃度層U與p_型蟲晶I 12之間之邊界淺的深 度而且具有大約Ιμηι的寬度。具有大約〇 3μηι之厚度的氧 夕薄膜18係被形成於该專溝渠2和6的底部和内側壁上 。由多晶矽製成的填料19係被埋藏於該等溝渠2和6内。 一個高度地摻雜有硼的通道阻絕擴散區域2Q係被形成 於與該等溝渠2和6接觸之p-型磊晶層12的部份區域中 。該η-通道阻絕擴散區域2〇具有丨χ 1〇16到丨χ⑺丨以爪。 的硼雜質濃度。該η-通道阻絕擴散區域2〇降低漏電流沿[Prior Art; J Background of the Invention FIG. 11A is a cross-sectional view of a photodiode, which is a photo sensor. On the surface of a p-type silicon substrate 100 15, an epitaxial layer 101 system made of η-type stone eve is formed. On the surface of the n-type stupid crystal layer 101, a field oxide film 102 is formed so as to define a plurality of active regions. In an active region (active region in the center region of FIG. 11A), a plurality of n-type cathode regions 10 are formed at a certain distance from each other. Between two adjacent cathode regions 103, a p-type partition region 104 is formed. The surface of the active region where the cathode region 103 and the separation region 104 are formed is covered by an anti-reflection film 105. Each of the active regions adjacent to the active regions on which the cathode region 103 is formed (active regions on the right and left in FIG. 11A) 7 587 333. Among the inventors, one A P-type anode lead region 106 is formed. The bottom of the anode lead region 106 reaches the p-type silicon substrate 100. The cathode region 103 and the p-type silicon substrate 100 constitute a photodiode. The p-type silicon substrate 100 functions as an anode of the photodiode. 5 Since the photosensitive element has a photoelectric conversion function, such a photodiode system is widely used as an optical pickup device to be used with a photoelectric conversion device, which is typically an optical disc such as a DVD and a CD. Since the wavelength of the laser beam becomes shorter, the photosensitive element system to be used with the optical disc is expected to operate at high speed. In order to achieve stable high-speed operation, it is desirable to reduce the different types of parasitic capacitance on the light-sensitive element and prevent leakage current. The photosensitive element shown in FIG. 11A has between the cathode region 103 and the adjacent anode region 106, between the cathode region 103 and the silicon substrate 100, and between the cathode 103 and the separation region 10. Parasitic capacitance between 4. These parasitic capacitances are expected to be reduced to ensure stable high-speed operation. Fig. 11B is a cross-sectional view of a conventional photosensitive element in which parasitic capacitance is partially reduced. Between the cathode region 103 and the anode lead region 106, a trench 108 is formed through the hafnium oxide film 102, and the trench reaches the surface layer of the P-type silicon substrate 100. A silicon oxide film is formed on the bottom and inner walls of the trench 108, and a polycrystalline silicon system is filled in the trench 108. A P-type high impurity concentration region 109 is formed in a region of the n-type epitaxial layer 101 and the silicon substrate 100 which are in contact with the trench 108. This ρ-type south impurity concentration region 109 prevents leakage current from flowing through the bottom of the trench 8 587333 (invention description). Since a thin oxide film having a lower dielectric constant than that of Shi Xi is formed on the sidewall of the trench 108, the parasitic capacitance between the cathode region 103 and the anode and the lead region 106 can be reduced. . 5 Although the parasitic capacitance between the cathode region 103 and the anode lead region 106 of the photosensitive element shown in FIG. 11B can be reduced, the cathode region 103 and the p-type silicon substrate 100 and the cathode The parasitic capacitance between the region ι03 and the separation region 104 cannot be reduced. Since the p-type impurity concentration region 1009 is formed around the trench 10108, a parasitic capacitance is newly formed between the cathode region 103 and the b-type high impurity concentration region 109. C Summary of the invention: J Summary of the invention The object of the present invention is to provide a semiconductor device with reduced parasitic capacitance between two impurity diffusion regions of opposite conductivity 15 type. According to a feature of the present invention, a semiconductor element system is provided. The semiconductor element includes: a bottom substrate having at least one surface layer made of a semiconductor having a first conductivity type; a first layer. The first layer is formed on or on the underlying substrate and is made of a semiconductor having a higher resistance than the surface layer of the underlying substrate; a first impurity diffusion region, the first impurity diffusion The region is formed on a partial surface region of the first layer and is doped with an impurity having a second conductivity type opposite to the first conductivity type; the first impurity diffusion region does not reach the surface of the underlying substrate; A second impurity with a second conductivity type is expanded 9 587333. The invention is described as a scattered region. The second impurity diffusion region is placed on the first layer and is separated from the first impurity diffusion region in a planar direction. A certain distance, the second impurity diffusion region reaches the surface of the underlying substrate; and a first separation region, the first separation region is disposed between the first and Ditches second impurity diffusion region between domain 5 and contains a line formed on the first layer within the dielectric material placed in at least part of the inner region of the trench. A first layer having a high resistance is disposed between the first impurity diffusion region and the underlying substrate. The parasitic capacitance between the first impurity diffusion region and the underlying substrate can therefore be reduced. Since the dielectric material is disposed in the trench constituting the first separation region, the parasitic capacitance between the first and second ion diffusion regions can be reduced. Brief Description of the Drawings Fig. 1 is a plan view of a photosensitive element of a first embodiment. Fig. 2 is a cross-sectional view of the photosensitive element of the first embodiment. 15 Fig. 3 is a graph showing the impurity concentration distribution along the depth direction beside the trench of the photosensitive element of the first embodiment. Fig. 4 is a cross-sectional view showing a connection area between a separation area of one of the photosensitive elements of the first embodiment and the trench. ‘FIG. 5 is a plan view of a photosensitive element of a second embodiment. · 20 Fig. 6 is a plan view of a photosensitive element of a third embodiment. Fig. 7 is a plan view of a photosensitive element of a fourth embodiment. Fig. 8 is a plan view of a photosensitive element of a fifth embodiment. Fig. 9 is a plan view of a photosensitive element of a sixth embodiment. Figures 10A to 10G are cross-sectional views for describing a method of manufacturing a semiconductor element having the photosensitive element of the first embodiment combined with a bipolar transistor. 11A and 11B are cross-sectional views of a conventional photosensitive element. Embodiment C; 15 Detailed Description of the Preferred Embodiment FIG. 1 is a plan view of a semiconductor photosensitive element according to a first embodiment of the present invention. A trench 2 having a planar shape consistent with the periphery of a square is disposed on a surface layer of a semiconductor substrate. A partition area 3 connects the centers of the opposite sides of the square defined by the trench 2 to divide the interior of the trench 10 into two areas. The end of the partitioned area 3 abuts the side wall of the trench 2. The cathode regions la to Id are arranged in four regions partitioned by the partition region 3. Each of the cathode regions 1a to 1d is disposed at a distance from the trench 2 and the partition region 3. The surfaces of the cathode regions 15 to 1d and the separation region 3 are covered with an anti-reflection film which will be described later. The electrode lead openings 4a to 4d are formed corresponding to the cathode regions 1a to 1d. The anti-reflection film is inside the cathode regions 1 a to 1 d. An anode lead region 5 surrounds the outside of the trench 2. In addition, a trench 6 20 surrounds the exterior of the anode lead region 5. The second figure is for the edge A cross-sectional view of 2-8 2 is drawn at the dotted line shown in the i-th figure. 'P-type impurity in the surface layer of p-type stone ^ with an impurity concentration of i X 10H to i χ 1〇1W It is doped with ytterbium to form a p-type high impurity concentration layer u with a peak degree of about ... On 11 587333 发明, the invention explains that this P-type high impurity concentration layer 11 The crystal layer 12 is formed, and the 忒 P-type epitaxial layer 12 has a thickness of 10 to 20 μm and has a p-type impurity concentration equal to or lower than 1 × 1014 cm-3 on the upper surface side thereof. On the P-type epitaxial layer 12, an η-type epitaxial layer 13 is formed. The η-type epitaxial layer 5 has an impurity concentration of about 5 × 10 15 cm · 3 and • A thickness of 8 to 2 μm. On the surface of the η-type epitaxial layer 13, a field oxide film 15 is formed to define several active regions. • In the central active region shown in FIG. 2 In the η-type stupid crystal layer 10, the η-type cathode regions U and lb are formed. Although not depicted in FIG. 2, the cathode regions lc and ld are also formed in this active region. The The iso-cathode regions la-ld are n-type impurity diffusion regions doped with phosphorus and have an impurity concentration of 1 X 1015 to 1 x 1020 cm-3. The cathode regions la to Id reach the p-type epitaxial layer. The upper surface of 12. The structure in which the cathode regions 15 U to Id do not reach the upper surface of the P-type epitaxial layer 12 can also be applied. Φ For the n-type epitaxial layer between the cathode regions la and lb In 13, a partition region 3 is formed. The partition region 3 is a p-type impurity diffusion region doped with boron and has an impurity concentration of 1 × 1016 to 1 × 20cm-3. 20 The partition region 3 electrically separates the cathode regions la and lb and prevents leakage current from flowing between them. Preferably, the depth of the partition region 3 The anti-reflection film 16 is formed on the surfaces of the active regions in which the cathode regions 1a and 1b are formed. The anti-reflection film 16 has 12 587333 发明, invention description 5 10 15 20 The two-layer structure of an oxygen-cut film and -nitrogen-cut film can reduce the reflectance with respect to the light in the receiving wavelength range. These anode lead regions 5 are formed in The anode regions 5 are adjacent to the _-regions having the cathode region 13 and the ㈣ region in which they are formed. The anode lead region 5 is a p-type hetero-f diffusion region doped with boron and has an impurity concentration of up to i X. . The anode lead region 5 extends from the upper surface of the n-type telecrystalline layer 13 to the b-type high impurity desert layer 11. As will be explained later, the anode wire ㈣5 is formed by two ion implantation processes ... one before the n_wei crystal layer 13 is formed and the other after the n-type epitaxial layer 13 is formed. . -A reverse bias voltage is applied between the cathode region u and the anode lead region 5 and between the cathode region 1b and the anode lead region 5. The trench 2 is formed between the active regions in which the cathode regions ι & and lb are disposed therein and the active regions in which the anode lead region 5 is disposed. In addition, the trench 6 is formed so as to surround the anode lead region 5 together with the trench 2. The trenches 2 and 6 extend slightly deeper than the boundary between the P-type two impurity concentration layer U and the p-type worm crystal I 12 and have a width of about 1 μm. An oxygen film 18 having a thickness of about 0.3 μm is formed on the bottom and inner side walls of the trenches 2 and 6. A filler 19 made of polycrystalline silicon is buried in the trenches 2 and 6. A highly boron-doped channel blocking diffusion region 2Q is formed in a part of the p-type epitaxial layer 12 in contact with the trenches 2 and 6. The η-channel barrier diffusion region 20 has χ × 1016 to χχ 丨. Concentration of boron impurities. The η-channel blocks the diffusion region 20 and reduces the leakage current along the

13 587333 玖、發明說明 著該溝渠2之底部與側壁的流動。13 587333 (2) The invention explains the flow of the bottom and side walls of the trench 2.

在以上所述之第一實施例的光敏元件中，光電二極體 係由作為陽極的p-型磊晶層12與p-型高雜質濃度層u及 作為陰極的陰極區域la和lb構成。具有高電阻的p_型蠢 5晶層I2係被設置於該陰極區域la與p-型高雜質濃度區域 11之間。在該陰極與陽極之間的寄生電容係因此能夠被降 低比在第11A和11B圖中所示之在其中之陰極區域ι〇3與 P-型基體（陽極）1 00係直接接觸的習知光敏元件更多。 該溝渠2係被設置於該陰極區域丨a與陽極導線區域5 1〇之間。由於設置在該溝渠2中之氧化矽薄膜18的介電常數 係比矽的介電常數低，在它們之間的寄生電容係能夠被降 低。該溝渠2係被設置與該陽極導線區域5在該基體平面 方向上相隔一定的距離。因此，寄生降低效果係能夠被提 升。代替該氧化矽薄膜，由具有比矽之介電常數低之介電 15常數之介電材料製成的其他薄膜係可以被使用。In the photosensitive element of the first embodiment described above, the photodiode is composed of the p-type epitaxial layer 12 as the anode, the p-type high impurity concentration layer u, and the cathode regions la and lb as the cathode. A p-type p-type crystal layer I2 having a high resistance is provided between the cathode region 1a and the p-type high impurity concentration region 11. The parasitic capacitance system between the cathode and the anode can therefore be reduced compared to the conventional method in which the cathode region ι03 shown in Figs. 11A and 11B is in direct contact with the P-type substrate (anode) 100 series. More photosensitive elements. The trench 2 is disposed between the cathode region 丨 a and the anode lead region 510. Since the dielectric constant of the silicon oxide film 18 provided in the trench 2 is lower than that of silicon, the parasitic capacitance between them can be reduced. The trench 2 is provided at a distance from the anode lead region 5 in the plane direction of the substrate. Therefore, the parasitic reduction effect can be improved. Instead of the silicon oxide thin film, other thin film systems made of a dielectric material having a dielectric constant lower than that of silicon may be used.

第3圖疋為顯示在第2圖中所示之溝渠2之侧邊沿著 深度方向之雜質濃度分佈的圖表。該橫座標表示雜質濃度 而該縱座標表謂度。-虛線21表示t nn日日層13被 形成時被摻雜之n-型雜質的濃度。-實線22表示當該p- 2〇型蟲晶層12被形成時被摻雜之ρ-型雜質的濃度。一實線 23表示#該η•通道阻絕擴散區域2G被形成時被摻雜之ρ_ 型雜質的濃度。 在該虛線21與實線22 型磊晶層13與ρ-型磊晶層 之間的交叉點係對應於在該η· 12之間的界面。被摻雜來形成 14 587333 玖、發明說明 该η-通道阻絕擴散區域2〇的卜型雜質係留在該 Ρ-型磊晶 層12而不擴散至該η_型磊晶層13。那就是，該&通道阻 絕擴散區域2G係被設置與該η_魏晶層13在深度方向上 相隔一定的距離，而且係被形成於該ρ•型磊晶層12。結果 5 ’於在陰極區域la與η通道阻絕擴散區域之間之寄生 電谷上的增加係能夠被抑制。 該溝渠2可以被作成更深俾可設置該n•通道阻絕擴散 區域20僅接近該溝渠2的底部。藉由這結構，在該陰極區 域U與n_通道阻絕擴散區域2()之間的寄生電容係能夠被 1〇進步降低。為了實現這結構，在第2圖中所示的溝渠2 可以被作成比該溝渠6深。 μ再參閱帛1圖所示’一個n_通道阻絕擴散區域25 係被配置在一個包括該在分隔區域3與溝渠2之間之界面 的區域。 15 帛4圖是為沿著在第1圖中所示之點線A4-A4的橫截 面圖4刀隔區域3係置於該有源區域而且不延伸在該 場氧化薄膜15下面。該n_通道阻絕擴散區域25係被配置 在該於分隔區域3與溝渠2之間的場氧化薄膜15下面。該 η通道阻絕擴散區域25是為_個被摻雜有硼的型雜質擴 2〇散區域而且具有大約lxl〇lw的雜質濃度。 虡η-通道阻絕擴散區域乃能夠降低經由在第工圖中 斤示之溝渠2之側邊區域來在相鄰之陰極區域，例如，陰 極區域1&與化，之間流動的漏電流。 π 第5圖是為第二實施例之光敏元件的平面圖。在第！ 15 587333 玖、發明說明 圖中所示的第一實施例中，該溝渠2係單-地被配置在該 等陰極區域ia-ld與陽極導線區域5之間，然而，在第二 實施例巾’雙倍的溝渠2A和2B係被設置。那就是，兩個 溝渠係沿著分隔該等陰極區域la-ld與陽極導線區域5的 ’ 5方向被"又置。其他的結構係與第一實施例之光敏元件的那 些相同。 藉由配置兩個溝渠，在該等陰極區域la-ld與陽極導 線區域5之間的寄生電容係能夠被進一步降低。三個或者 · 更多個溝渠係可以被設置。 1〇 第6圖疋為第三實施例之光敏元件的平面圖。在第j 圖中所示的第-實施例中，該溝渠2的寬度係大約_， 然而，在第三實施例中，被設置於該等陰極區域u_id與 陽極導線區域5之間之溝渠2C的寬度係被作成較寬。於 該等陰極區域la-ld與陽極導線區域5之間的距離係因此 15比第一實施例之光敏元件的那個長。其他的結構係與在第 1圖中所示之第一實施例之光敏元件的那些相同m # ，包圍該陽極導線區域5之外圍之溝渠6的寬度係與第一 實施例之光敏元件之溝渠6的寬度相同。 · 藉由把該溝渠2C的寬度加寬比該第一實施例之溝渠2 · 20的寬度寬，在該等陰極區域la-ld與陽極導線區域5之間 的寄生電容係能夠被降低。如果被形成於該溝渠2C之底 部和内側壁上的氧化矽薄膜係被作成較厚的話，寄生電容 降低效果係能夠被進一步提升❶一氧化矽薄膜係可以被填 注於該溝渠2C的整個内部空間。 16 玖、發明說明 第7圖是為第四實施例之光敏元件的平面圖。在第i 圖中所示之第一實施例的光敏元件中，該分隔區域3是為 如在第2圖中所示的P-型雜質擴散區域，然而，在該第四 實施例中’一分隔區域3A係由一溝渠與填注於該溝渠内 的填料構成。一個構成該分隔區域3A的溝渠係從被設置 於該等陰極區域la-ld與陽極導線區域5之間的溝渠2分 支出來。藉由使用該溝渠結構的分隔區域3A，在該等陰極 區域la-ld與該第一實施例之分隔區域3之間的寄生電容 係能夠被降低。 第8圖是為第五實施例之光敏元件的平面圖。在第^ 圖中所示的第一實施例中，被設置於該陰極區域u與陽極 導線區域5之間的溝渠2係與被設置於該相鄰之陰極區域 lb與陽極導線區域5之間的溝渠2延續，而且該分隔區域 3的末端係緊靠該溝渠2的側壁。 在該第五實施例中，一個在兩個相鄰之陰極區域，例 如，陰極區域la與lb，之間的分隔區域沾係到達該陽極 導線區域5。那就是，該分隔區域3B的末端係緊靠該陽極 導線區域5的側壁。因此’―個在該陰極區域 線區域5之間的溝渠2D和—個在該陰極區域⑪與陽極導 線區域5之間的溝渠2E係由該分隔區域3B分隔。該等溝 渠2D和2E的末端係緊靠該分隔區域3B的側壁。一個在 該陰極區域lc與陽極導線區域5之_溝渠^和一個在 該陰極區域Id與陽極導線區域5之間的溝渠犯具有與該 等溝渠2D和2E之結構相同的結構。其他的結構係與第一 587333 玖、發明說明 實施例之光敏元件的那些相同。 在該第一實施例中，漏電流會經由該溝渠2的側邊區 域來在該等陰極區域1 a與1 b之間流動。在該第五實施例 中，於該陰極區域la與陽極導線區域5之間的溝渠2D及 5 於該陰極區域lb與陽極導線區域5之間的溝渠2E係由該 分隔區域3B分隔。因此，要防止漏電流沿著該溝渠2的 側邊區域流動是有可能的。 第9圖是為第六實施例之光敏元件的平面圖。在第8 圖中所示的第五實施例中，該溝渠2D係單一地被設置於 10该陰極區域1 a與陽極導線區域5之間，然而，在該第六實 施例中’對應於第五實施例之溝渠2D的一個溝渠2H沿著 刀隔違陰極區域la和陽極導線區域5的方向具有雙重的結 構。其他的溝渠2I，2J和2K亦具有雙重的結構。其他的結 構係與在第8圖中所示之第五實施例之光敏元件的那些相 15 同。 藉著使被設置於該陰極區域la與陽極導線區域5之間 的溝渠2D具有雙重的結構，於這些區域la與5之間的寄 生電容係能夠被降低。 接著’明參閱第i〇A至i〇G圖所示，一種製造第一實 2〇施例之光敏元件的方法將會被說明。於要在下面說明的方 法中，用於放大由該光敏元件所產生之光電流的雙極性電 晶體係在相同的時間被形成於與該光敏元件之基體相同的 基體上。 如在第10A圖中所示，硼離子係被植入一個具有大約 18 玖、發明說明 40Ω cm之電阻係數之p_型矽基體1〇的表面層内俾可藉此 形成-具有大約i x 1〇1W3之表面雜質濃度的ρ·型高雜 質;農度層11。在這ρ_型高雜質濃度層U上，一個高電阻 Ρ-型蠢日日層12，具有大約！ χ 1()14em_3之表面雜質濃度的 5層，係藉由化學氣相沉積法（CVD)來被形成。 硼離子係被植入到該p-型蟲晶層12的部份區域俾可 形成-陽極導線埋藏區域Sa。該陽極導線埋藏區域化係 到達讅P-型南雜質濃度層11而且係對應於在該P-型磊晶 層12中之在第2圖中所示的陽極導線區域5。該陽極導線 10埋藏區域5a具有1χ1〇16到lxl〇18cm-3的雜質濃度。 如在第10B圖中所示，鱗離子係被植入到該型蟲晶 層12的部份區域内俾可形成一心型ρ·通道阻絕擴散區域 3〇。該p-通道阻絕擴散區域3〇係被設置於該卜型磊晶層 12中而且係不到達該P-型高雜質濃度層11。在該P-通道 15阻絕區域30中的磷濃度是為lx 1016到lx 1〇w該鱗 濃度係被控制以致於_個足夠的崩潰f壓係被保證在該卜 型兩雜質濃度層11與P·通道阻絕擴散區域30之間及在一 個要被形成於該p-通道阻絕擴散區域3〇之卿電晶體之 集極區域與該P-通道阻絕擴散區域30之間。 20 接著，賴子係被植人至該12的部份區 域内俾可形成- η-型埋藏擴散區域31。在同一時間，與該 Ρ-通道阻絕擴散區域3G延續—起的—卜型埋藏擴散區域 32係被形成。該等η_型埋藏擴散區域31和32的銻濃度是 為 lxlO18 到 lx l〇2〇cm-3。 19 587333 玖、發明說明 删離子係被植入到該p.通道阻絕擴散區域3〇之表面 層的部份區域内俾可形成—埋藏擴散區域…於同一 時間’硼離子係被植入到—個對應於在第i圖中所示之分 隔區域3的區域内俾可形成一個下分隔區域。該p_型埋藏 5擴散區域33與下分隔區域3a的硼濃度是為1乂1〇16至1乂 1018cm·3 〇 在忒P-型磊晶層12上，一 n-型磊晶層13係藉著CVD 來被形成到0.8到2μηι的厚度。該卜型磊晶層13的卜型 雜質濃度是為大約5x l〇15cm·3。 1〇 硼離子係被植入到與該P-型埋藏擴散區域33接觸之 η-型磊晶層13的部份區域内俾可形成一 型井35。於同 一時間，硼離子係被植入到與該陽極導線埋藏區域5a接觸 之η-型磊晶層13的部份區域俾可形成一個上陽極導線區 域5b。該ρ-型井35與上陽極導線區域5b的硼濃度是為ι 15 X 1016到1 x 1018cm_3。該陽極導線埋藏區域5a與上陽極 導線區域5b構成在第2圖中所示的陽極導線區域5。 如在第10C圖中所示，於該n_型磊晶層13的表面上 ’石夕之區域氧化（LOCOS)用的光罩圖案40係被形成。該光 罩圖案40具有一個由一氧化矽薄膜與一氮化矽薄膜構成的 20兩層結構。硼離子係被植入到被形成有在第1圖中所示之 η-通道阻絕擴散區域25的區域内。該η-通道阻絕擴散區域 25的爛濃度是為大約1 X l〇17cnf3。由於硼離子係在 LOCOS之前被植入，該n_通道阻絕擴散區域25亦被設置 在該要於一稍後之處理下被形成的場氧化薄膜下面。 20 587333 玖、發明說明 藉由使用該光罩圖案40作為光罩，該n_型磊晶層13 的表面係區域地氧化。 如在第10D圖中所示，一埸氧化薄膜15係因此被形 成而且有源區域係被界定。該埸氧化薄膜丨5的厚度是為大 5約6⑻nm。接著，在第1圖中所示的溝渠2和6係被形成 。於同一時間，一溝渠42係被形成於在設置有pnp電晶體 之有源區域41b與設置有npn電晶體之有源區域41a之間 的邊界區域中。 在该4溝渠被形成之後，硼離子係被植入俾可形成在 10第2圖中所示的η-通道阻絕擴散區域2〇。該硼濃度是為j X 1〇16 到 1 X l〇18cm·3。 一氧化矽薄膜係被形成覆蓋該等溝渠2,6和42的内表 面和該基體表面。一多晶矽薄膜係被形成埋藏該等溝渠2,6 ί 42的内。卩。忒氧化石夕薄膜和多晶石夕薄膜係被回餘刻到僅 15留下在該等溝渠中的氧化矽薄膜和多晶矽薄膜。一氧化矽 薄膜係被形成於該基體的整個表面之上俾可以該氧化矽薄 膜覆蓋在該等溝渠内之多晶矽薄膜的上表面。 一防反射薄膜16係被形成在該基體的整個表面之上。 該防反射薄膜16具有-個由-氧化㈣膜與_氮化石夕薄膜 20構成的兩層結構。這些層係藉由，例如，熱氧化和來 被形成。 硼離子係被植入到在該下分隔區域3a之上的化型磊晶 層13俾可形成一上分隔區域3b。該删濃度是為i X ι〇ΐ6到 1 X 1〇2%ηΤ3。該下分隔區域3a和上分隔區域补構成在第 21 587333 玖、發明說明 2圖中所示的分隔區域3。接著，磷離子係被植入俾可形成 一陰極區域la。該磷濃度是為1 X 1〇15到1 X i〇2Gcm-3。石申 或銻係可以被使用代替磷。該分隔區域3和陰極區域ia的 雜質濃度係藉由考量光電二極體的敏感度和反應速度來被 5 適當地決定。 直到在第10E圖中所示之結構的處理將會作說明。一 個穿過該防反射薄膜16的開孔係被形成在形成有一電極的 位置。一第一層多晶矽薄膜係被形成在整個基體表面之上 到大約300nm的厚度。這多晶矽薄膜係被定以圖案俾可留 10下一覆蓋該被形成穿過該防反射薄膜16之開孔的第一層多 晶矽薄膜45。該多晶矽薄膜45亦留在該覆蓋陰極區域u 之表面的防反射薄膜16上。 磷離子係經由該多晶石夕薄膜45來被植入到該npn電晶 體的集極區域43。該磷濃度是為大約！ X i〇i9cm-3。該集 15極區域43係到達該卜型埋藏擴散區域31。於同一時間， η-型導線區域44係被形成到達該卜型埋藏擴散區域32 〇 用於形成外部基極的删離子係被植入到該覆蓋設置有 ηΡη電晶體之有源區域的多晶矽薄膜45a内。用於形成外 2〇部基極的磷離子係被植入到該覆蓋設置有pnp電晶體之有 源區域的多晶矽薄膜45b内。該硼與磷濃度是為大約工X l〇19cnT3。 由氧化矽製成的一中間絕緣薄膜46係被形成在該基體 的整個表面之上。射極窗46a和46b係被形成穿過該中間 22 587333 玖、發明說明 絕緣薄膜46。離子係經由該等射極窗來被植入俾可橫向地 連接内和外基極。侧壁間隔器係被形成於該等射極窗46a 和46b的内側壁上。 接著，用於形成一内基極的離子係經由該等射極窗 5 46a和46b來被植入到該n_型磊晶層13的表面層内。硼離 子係被植入到该ηρη電晶體的内基極47，而磷離子係被植 入到该ρηρ電晶體的内基極48。該硼和碌濃度是為大約！ X 1018cm-3 〇 在離子被植入之後，一回火處理係被執行。藉由這回 10火處理，在該多晶矽薄膜45a内的硼離子係擴散到該卜型 磊晶層13的表面層俾可形成外基極49。類似地，在該多 晶矽薄膜45b内的磷離子係擴散到該p-型井35的表面層 俾可形成一外基極5 0。 如在第10F圖中所示，一第二層多晶矽薄膜係被形成 15於該中間絕緣薄膜46上。磷離子係被植入到設置有該npn 電晶體之多晶矽薄膜的部份區域内，而硼離子係被植入到 6又置有該pnp電晶體的部份區域内。該磷與硼濃度是為工X 1 〇到1 X 1020cm 3。該多晶矽薄膜係被定以圖案俾可留下 由多晶矽製成的射極51和52在該等射極窗46a和46b中 2〇 。在該等射極51和52中的雜質係藉著回火處理來被擴散 到該η-型磊晶層13的表面層。 開孔係被形成穿過該中間絕緣薄膜46俾可形成一電晶 體之集極、基極和射極、一光電二極體之陰極和陽極等等 的導線電極。一第一層鋁電極55係被形成在這些開孔内。 23 玖、發明說明 在該第一層中間絕緣薄膜46上，一個由氧化矽製成的第二 層中間絕緣薄膜60係被形成。一開孔係被形成穿過該第二 層中間絕緣薄膜俾可形成該npn電晶體之基極的導線電極 第一層結電極5 6係被形成於這開孔内。由石夕玻璃與氮 化矽製成的一覆蓋薄膜61係被形成於該第二中間絕緣薄膜 60上。 如在第10G圖中所示，在該光電二極體光線接收區域 中 開孔係被形成從該覆蓋薄膜61到第一層中間絕緣薄 膜46穿過該三層。這時，覆蓋該防反射薄膜16之表面的 1〇第一多晶矽薄膜45作用如一蝕刻阻絕器。在該開孔被形成 之後，於該防反射層16上的多晶矽薄膜45係被移去。 藉由這製造方法，該下分隔區域3a係在p-型埋藏擴散 區域33被形成時的同一時間被形成。該上陽極導線區域 5b係在該p_型井35被形成時的同一時間被形成^在製造 15 處理之數目上的增加係能夠因此儘可能地被抑制。 本發明業已配合該等較佳實施例來作說明。本發明不 是僅受限於以上的實施例。很明顯的是，對於熟知此項技 術之人仕來說，各種變化、改良、組合等等係能夠被作成 〇 20 【圖式簡單說明】 第1圖是為一第一實施例之光敏元件的平面圖。 第2圖是為該第一實施例之光敏元件的橫截面圖。 第3圖是為顯示在該第一實施例之光敏元件之溝渠之 旁邊沿著深度方向之雜質濃度分佈的圖表。 24 587333 玖、發明說明 第4圖是為顯示一個在該第一實施例之光敏元件之一 分隔區域與該溝渠之間之連接區域的橫截面圖。 第5圖是為一第二實施例之光敏元件的平面圖。 第6圖是為一第三實施例之光敏元件的平面圖。 5 第7圖是為一第四實施例之光敏元件的平面圖。 第8圖是為一第五實施例之光敏元件的平面圖。 第9圖是為一第六實施例之光敏元件的平面圖。Fig. 3 is a graph showing the impurity concentration distribution along the depth of the side of trench 2 shown in Fig. 2; The abscissa indicates the impurity concentration and the ordinate indicates the degree. -The dashed line 21 indicates the concentration of the n-type impurity that is doped when the layer 13 is formed. -The solid line 22 indicates the concentration of the p-type impurity that is doped when the p-20 type worm crystal layer 12 is formed. A solid line 23 indicates the concentration of the ρ_-type impurity that is doped when the η • channel barrier diffusion region 2G is formed. The intersection between the dotted line 21 and the solid line 22-type epitaxial layer 13 and the p-type epitaxial layer corresponds to the interface between η · 12. Doped to form 14 587333 玖, description of the invention The b-type impurity of the n-channel blocking diffusion region 20 remains in the p-type epitaxial layer 12 without diffusing into the n-type epitaxial layer 13. That is, the & channel barrier diffusion region 2G is provided at a distance from the η-Wei crystal layer 13 in the depth direction, and is formed on the p-type epitaxial layer 12. As a result, the increase in the parasitic valley between 5 'between the cathode region la and the n-channel blocking diffusion region can be suppressed. The trench 2 can be made deeper, and the n • channel blocking diffusion region 20 can be set only near the bottom of the trench 2. With this structure, the parasitic capacitance between the cathode region U and the n-channel blocking diffusion region 2 () can be reduced by 10%. To realize this structure, the trench 2 shown in FIG. 2 can be made deeper than the trench 6. [Refer to Fig. 1 again] 'An n-channel blocking diffusion region 25 is arranged in a region including the interface between the partition region 3 and the trench 2'. Fig. 15 is a cross-sectional view taken along the dotted line A4-A4 shown in Fig. 4. The blade region 3 is placed in the active region and does not extend under the field oxide film 15. The n-channel barrier diffusion region 25 is disposed under the field oxide film 15 between the partition region 3 and the trench 2. The n-channel blocking diffusion region 25 is a diffusion region for one type impurity doped with boron and has an impurity concentration of about 1 × 10 lw. The 虡 η-channel blocking diffusion region is capable of reducing the leakage current flowing between adjacent cathode regions, for example, the cathode region 1 & through the side region of the trench 2 shown in the drawing. FIG. 5 is a plan view of the photosensitive element of the second embodiment. In the first! 15 587333 (1) In the first embodiment shown in the description of the invention, the trench 2 is a single-ground arrangement between the cathode regions ia-ld and the anode lead region 5. However, in the second embodiment, 'Double ditch 2A and 2B are set. That is, the two trenches are placed again along the direction of "5" separating the cathode regions la-ld and the anode lead region 5. The other structures are the same as those of the photosensitive element of the first embodiment. By arranging two trenches, the parasitic capacitance between the cathode regions la-ld and the anode lead region 5 can be further reduced. Three or more ditch systems can be set. 10 FIG. 6 is a plan view of the photosensitive element of the third embodiment. In the first embodiment shown in the j-th figure, the width of the trench 2 is approximately _. However, in the third embodiment, the trench 2C is provided between the cathode regions u_id and the anode lead region 5 The width is made wider. The distance between the cathode regions la-ld and the anode lead region 5 is therefore longer than that of the photosensitive element of the first embodiment. Other structures are the same as those of the photosensitive element of the first embodiment shown in FIG. 1. The width of the trench 6 surrounding the periphery of the anode lead region 5 is the same as that of the photosensitive element of the first embodiment. The width of 6 is the same. By widening the width of the trench 2C than that of the trench 2 · 20 of the first embodiment, the parasitic capacitance between the cathode regions la-ld and the anode lead region 5 can be reduced. If the silicon oxide thin film formed on the bottom and the inner wall of the trench 2C is made thicker, the parasitic capacitance reduction effect can be further improved. The silicon monoxide thin film can be filled in the entire interior of the trench 2C space. 16 发明. Description of the Invention Fig. 7 is a plan view of a photosensitive element of a fourth embodiment. In the photosensitive element of the first embodiment shown in FIG. I, the separation region 3 is a P-type impurity diffusion region as shown in FIG. 2. However, in the fourth embodiment, 'a The partition area 3A is composed of a trench and a filler filled in the trench. A trench constituting the partitioned area 3A is dispensed from two trenches provided between the cathode regions la-ld and the anode lead region 5. By using the separation region 3A of the trench structure, the parasitic capacitance between the cathode regions la-ld and the separation region 3 of the first embodiment can be reduced. Fig. 8 is a plan view of the photosensitive element of the fifth embodiment. In the first embodiment shown in FIG. ^, The trench 2 provided between the cathode region u and the anode lead region 5 is provided between the adjacent cathode region 1b and the anode lead region 5. The trench 2 continues, and the end of the partition region 3 is abutted against the side wall of the trench 2. In this fifth embodiment, one separate region between two adjacent cathode regions, e.g., the cathode regions 1a and 1b, reaches the anode lead region 5. That is, the end of the partition region 3B is abutted against the side wall of the anode lead region 5. Therefore, a trench 2D between the cathode area line area 5 and a trench 2E between the cathode area ⑪ and the anode line area 5 are separated by the separation area 3B. The ends of the trenches 2D and 2E abut the side wall of the partitioned area 3B. A trench between the cathode region 1c and the anode lead region 5 and a trench between the cathode region Id and the anode lead region 5 have the same structure as the trenches 2D and 2E. The other structures are the same as those of the first photosensitive member of the 587333, the description of the invention. In the first embodiment, a leakage current flows between the cathode regions 1 a and 1 b through a side region of the trench 2. In the fifth embodiment, the trenches 2D between the cathode region 1a and the anode lead region 5 and the trenches 2E between the cathode region 1b and the anode lead region 5 are partitioned by the partition region 3B. Therefore, it is possible to prevent leakage current from flowing along the side region of the trench 2. Fig. 9 is a plan view of the photosensitive element of the sixth embodiment. In the fifth embodiment shown in FIG. 8, the trench 2D is singularly provided between the cathode region 1 a and the anode lead region 5. However, in the sixth embodiment, “corresponding to the first One trench 2H of the trench 2D of the fifth embodiment has a double structure along the direction of the knife barrier against the cathode region la and the anode lead region 5. The other trenches 2I, 2J and 2K also have a dual structure. The other structures are the same as those of the photosensitive element of the fifth embodiment shown in FIG. By having a double structure of the trench 2D provided between the cathode region 1a and the anode lead region 5, the parasitic capacitance between these regions 1a and 5 can be reduced. Next, referring to Figures 10A to 10G, a method of manufacturing the photosensitive element of the first embodiment 20 will be explained. In a method to be described below, a bipolar transistor system for amplifying a photocurrent generated by the photosensitive element is formed on the same substrate as the substrate of the photosensitive element at the same time. As shown in FIG. 10A, the boron ion system is implanted into a surface layer of a p-type silicon substrate 10 having a resistivity of about 18 玖, a resistivity of 40 Ω cm, and can be formed therefrom-having about ix 1 〇 · W-type high impurity of surface impurity concentration; agronomic layer 11. On this p-type high impurity concentration layer U, a high-resistance P-type stupid layer 12 has approximately! Five layers with a surface impurity concentration of χ 1 () 14em_3 were formed by chemical vapor deposition (CVD). A boron ion is implanted into a part of the p-type worm crystal layer 12 to form an anode wire buried region Sa. The anodic lead buried region reaches the P-type south impurity concentration layer 11 and corresponds to the anodic lead region 5 in the P-type epitaxial layer 12 shown in Fig. 2. The buried region 5a of the anode lead 10 has an impurity concentration of 1x1016 to lx1018cm-3. As shown in Fig. 10B, the squamous ion system is implanted into a part of the worm crystal layer 12 to form a heart-shaped ρ · channel blocking diffusion region 30. The p-channel barrier diffusion region 30 is provided in the Bu type epitaxial layer 12 and does not reach the P-type high impurity concentration layer 11. The phosphorus concentration in the P-channel 15 rejection region 30 is lx 1016 to lx 10w. The scale concentration is controlled so that a sufficient collapse f pressure system is ensured in the two-type impurity concentration layers 11 and Between the P · channel barrier diffusion region 30 and between a collector region of a transistor to be formed in the p-channel barrier diffusion region 30 and the P-channel barrier diffusion region 30. 20 Then, the Laizi line was implanted into a part of the 12 area, and a -η-type buried diffusion area 31 could be formed. At the same time, the Bu-type buried diffusion region 32 is formed in conjunction with the P-channel blocking diffusion region 3G. The antimony concentration of the η-type buried diffusion regions 31 and 32 is lxlO18 to lxl02cm-3. 19 587333 发明, description of the invention The ion-implanted system is implanted into a part of the surface layer of the p. Channel blocking diffusion region 30, and can be formed-a buried diffusion region ... At the same time, a boron ion system is implanted into- An area corresponding to the divided area 3 shown in the i-th figure may form a lower divided area. The boron concentration of the p_type buried 5 diffusion region 33 and the lower separation region 3a is 1 乂 1016 to 1 乂 1018 cm · 3. On the 忒 P-type epitaxial layer 12, an n-type epitaxial layer 13 It is formed to a thickness of 0.8 to 2 μm by CVD. The Bu-type epitaxial layer 13 has a Bu-type impurity concentration of about 5 × 10 15 cm · 3. 10 A boron ion is implanted into a part of the n-type epitaxial layer 13 in contact with the P-type buried diffusion region 33, and a type-well 35 can be formed. At the same time, a boron ion is implanted into a part of the n-type epitaxial layer 13 in contact with the anode lead buried region 5a, and an upper anode lead region 5b can be formed. The boron concentration of the p-type well 35 and the upper anode lead region 5b is ι 15 × 1016 to 1 × 1018 cm_3. The anode lead buried region 5a and the upper anode lead region 5b constitute the anode lead region 5 shown in Fig. 2. As shown in FIG. 10C, a photomask pattern 40 for the area oxidation (LOCOS) of the ishiishi on the surface of the n-type epitaxial layer 13 is formed. The mask pattern 40 has a two-layer structure consisting of a silicon oxide film and a silicon nitride film. The boron ion system is implanted into a region where the n-channel blocking diffusion region 25 shown in Fig. 1 is formed. The rotten concentration of the n-channel blocking diffusion region 25 is about 1 × 1017cnf3. Since the boron ion was implanted before the LOCOS, the n-channel blocking diffusion region 25 was also disposed under the field oxide film to be formed in a later process. 20 587333 (ii) Description of the invention By using the mask pattern 40 as a mask, the surface system region of the n-type epitaxial layer 13 is oxidized. As shown in Fig. 10D, an oxide film 15 is thus formed and the active area is defined. The thickness of the hafnium oxide film 5 is about 5 nm. Next, trenches 2 and 6 shown in Fig. 1 are formed. At the same time, a trench 42 is formed in a boundary region between the active region 41b provided with the pnp transistor and the active region 41a provided with the npn transistor. After the four trenches are formed, a boron ion system is implanted so that the n-channel blocking diffusion region 20 shown in Fig. 2 can be formed. The boron concentration is j X 1016 to 1 X 1018 cm · 3. A silicon oxide film is formed to cover the inner surfaces of the trenches 2, 6 and 42 and the surface of the substrate. A polycrystalline silicon thin film is formed to bury these trenches 2,6 ί 42. Alas. The oxidized stone film and polycrystalline stone film are etched back to the silicon oxide film and polycrystalline silicon film which are left in these trenches only 15 times. The silicon oxide film is formed on the entire surface of the substrate, and the silicon oxide film can cover the upper surface of the polycrystalline silicon film in the trenches. An anti-reflection film 16 is formed over the entire surface of the substrate. The anti-reflection film 16 has a two-layer structure composed of a hafnium oxide film and a nitride nitride film 20. These layers are formed by, for example, thermal oxidation. A boron ion system is implanted on the chemically-activated epitaxial layer 13 'over the lower partition region 3a to form an upper partition region 3b. The deletion concentration ranges from i X 〇 〇6 to 1 X 102% ηΤ3. The lower divided region 3a and the upper divided region are supplemented by the divided region 3 shown in the figure 21, 587333 (2) and the description of the invention. Subsequently, a phosphorus ion system is implanted to form a cathode region la. The phosphorus concentration is 1 X 1015 to 1 X 102 Gcm-3. Shishen or antimony can be used instead of phosphorus. The impurity concentration of the partition region 3 and the cathode region ia is appropriately determined by considering the sensitivity and reaction speed of the photodiode 5. The processing up to the structure shown in Fig. 10E will be explained. An opening through the antireflection film 16 is formed at a position where an electrode is formed. A first layer of polycrystalline silicon thin film is formed over the entire substrate surface to a thickness of about 300 nm. This polycrystalline silicon thin film is set in a pattern so that it can be left next to cover the first polycrystalline silicon thin film 45 formed through the opening formed through the anti-reflection film 16. The polycrystalline silicon film 45 is also left on the anti-reflection film 16 covering the surface of the cathode region u. Phosphorus ions are implanted into the collector region 43 of the npn transistor through the polycrystalline silicon film 45. The phosphorus concentration is about! Xioi9cm-3. The 15-pole region 43 of the set reaches the Buried buried diffusion region 31. At the same time, the η-type lead region 44 is formed to reach the Buried buried diffusion region 32. The ion-exchange system used to form the external base is implanted into the polycrystalline silicon thin film covering the active region provided with the ηpn transistor. Within 45a. A phosphorus ion system for forming the outer 20 base is implanted into the polycrystalline silicon thin film 45b covering the active region provided with the pnp transistor. The boron and phosphorus concentration is approximately X1019cnT3. An intermediate insulating film 46 made of silicon oxide is formed over the entire surface of the substrate. The emitter windows 46a and 46b are formed through the middle 22,587,333, and an insulating film 46 is described. Ions are implanted via these emitter windows, which can connect the inner and outer bases laterally. Side wall spacers are formed on the inner side walls of the emitter windows 46a and 46b. Next, an ion system for forming an inner base is implanted into the surface layer of the n-type epitaxial layer 13 through the emitter windows 5 46a and 46b. A boron ion system is implanted into the inner base 47 of the? Ρn transistor, and a phosphorus ion system is implanted into the inner base 48 of the? N? Transistor. The boron and pyrene concentrations are for approx! X 1018cm-3 〇 After the ions are implanted, a tempering process is performed. By this heat treatment, the boron ions in the polycrystalline silicon thin film 45a are diffused to the surface layer of the Bu epitaxial layer 13 to form the outer base 49. Similarly, the phosphorus ions in the polycrystalline silicon thin film 45b diffuse to the surface layer 层 of the p-type well 35 to form an outer base 50. As shown in FIG. 10F, a second polycrystalline silicon thin film system is formed on the intermediate insulating film 46. Phosphorus ions are implanted into a part of the polycrystalline silicon thin film where the npn transistor is placed, and boron ions are implanted into a part of the area where the pnp transistor is placed. The phosphorus and boron concentration ranges from 1 × 10 to 1 × 1020 cm 3. The polycrystalline silicon thin film is patterned so that the emitters 51 and 52 made of polycrystalline silicon are left in the emitter windows 46a and 46b. The impurities in the emitters 51 and 52 are diffused to the surface layer of the n-type epitaxial layer 13 by a tempering process. An opening is formed through the intermediate insulating film 46 to form a wire electrode of a collector, a base and an emitter of a crystal, a cathode and an anode of a photodiode, and the like. A first layer of aluminum electrode 55 is formed in these openings. 23 (ii) Description of the invention On the first interlayer insulating film 46, a second interlayer insulating film 60 made of silicon oxide is formed. An opening is formed through the second intermediate insulating film. A wire electrode which can form the base of the npn transistor. A first layer of junction electrode 56 is formed in the opening. A cover film 61 made of Shixi glass and silicon nitride is formed on the second intermediate insulating film 60. As shown in Fig. 10G, openings are formed in the photodiode light receiving region to pass from the cover film 61 to the first intermediate insulating film 46 through the three layers. At this time, the first polycrystalline silicon film 45 covering the surface of the anti-reflection film 16 functions as an etch stopper. After the opening is formed, the polycrystalline silicon thin film 45 on the anti-reflection layer 16 is removed. With this manufacturing method, the lower partition region 3a is formed at the same time as the p-type buried diffusion region 33 is formed. The upper anode lead region 5b is formed at the same time when the p-type well 35 is formed. An increase in the number of manufacturing processes can be suppressed as much as possible. The invention has been described in conjunction with these preferred embodiments. The present invention is not limited only to the above embodiments. Obviously, for those who are familiar with this technology, various changes, improvements, combinations, etc. can be made. [Schematic description] Figure 1 is a photo sensor of the first embodiment Floor plan. Fig. 2 is a cross-sectional view of the photosensitive element of the first embodiment. Fig. 3 is a graph showing the impurity concentration distribution along the depth direction beside the trench of the photosensitive element of the first embodiment. 24 587333 2. Description of the Invention Fig. 4 is a cross-sectional view showing a connection region between a partition region of one of the photosensitive elements of the first embodiment and the trench. Fig. 5 is a plan view of a photosensitive element of a second embodiment. Fig. 6 is a plan view of a photosensitive element of a third embodiment. 5 FIG. 7 is a plan view of a photosensitive element of a fourth embodiment. Fig. 8 is a plan view of a photosensitive element of a fifth embodiment. Fig. 9 is a plan view of a photosensitive element of a sixth embodiment.

第10A至10G圖是為描繪製造具有與雙極性電晶體整 合在一起之該第一實施例之光敏元件之半導體元件之方法 10 的橫截面圖。 第11A和11B圖是為習知光敏元件的橫截面圖。 【圖式之主要元件代表符號表】 100 · p-型碎基體 101 * n-型蟲晶層 102 · 場氧化薄膜 103 · 陰極區域 104 · 分隔區域 105 * 防反射薄膜 106 · 陽極導線區域 108 · 溝渠 109 ♦ P"型高雜質濃度區域 2.·· 溝渠 3.·· 分隔區域 la * * 陰極區域 lb ♦· •陰極區域 lc… •陰極區域 Id· · •陰極區域 4a ·· •電極導線開孔 4b · ♦ •電極導線開孔 4c * * •電極導線開孔 4d· · •電極導線開孔 5 · · •陽極導線區域 6 * * •溝渠 10· · • P·型矽基體 11 · · • P-型高雜質濃度層 12·· ♦ p_型蠢晶層Figures 10A to 10G are cross-sectional views for describing a method 10 of manufacturing a semiconductor element having the photosensitive element of the first embodiment integrated with a bipolar transistor. 11A and 11B are cross-sectional views of a conventional photosensitive element. [Representative symbols for main components of the diagram] 100 · p-type broken substrate 101 * n-type worm crystal layer 102 · field oxide film 103 · cathode area 104 · partition area 105 * anti-reflection film 106 · anode lead area 108 · Ditch 109 ♦ P " type high impurity concentration area 2. ·· Ditch 3. ·· Separation area la * * Cathode area lb ♦ · • Cathode area lc… • Cathode area Id · · • Cathode area 4a ·· • The electrode lead is open Hole 4b · ♦ • Electrode lead opening 4c * * • Electrode lead opening 4d · · • Electrode lead opening 5 · · • Anode lead area 6 * * • Ditch 10 · · • P · type silicon substrate 11 · · • P-type high impurity concentration layer 12 ·· p_type stupid crystal layer

25 587333 玖、發明說明 13… η-型蠢晶層 15 · ·埸氧化薄膜 16…防反射薄膜 18 · ·氧化矽薄膜 19..填料 20· · η-通道阻絕擴散區域 21 · *虛線 22· ·實線 23 · ·實線 25* * η-通道阻絕擴散區域 2Α· ·溝渠 2Β· ·溝渠 2C· ·溝渠 2D· ·溝渠 2Ε· ·溝渠 2F· ·溝渠 2G…溝渠 2Η ·溝渠 3Α· ·分隔區域 5a· ·陽極導線埋藏區域 30· · 通道阻絕擴散區域 31 · · η-型埋藏擴散區域 32 · · η-型埋藏擴散區域 33 · · · ρ-型埋藏擴散區域 3a· ··下分隔區域 35…· p-型井 5b. ··上陽極導線區域 40· ··光罩圖案 42· · ·溝渠 41a ··有源區域 41b ·.有源區域 3b· ··上分隔區域 45· ♦·第一層多晶矽薄膜 43· ··集極區域 44· ·. η-型導線區域 45a ♦.多晶矽薄膜 45b ♦ ♦多晶矽薄膜 46· ··中間絕緣薄膜 46a ··射極窗 46b ·.射極窗 47* * * 亟 48. · ·内基極 49 · · ·外基極 50* ♦♦外基極 51…射極 52···射極25 587333 发明, invention description 13 ... η-type stupid crystal layer 15 · · 埸 oxide film 16 ... anti-reflection film 18 · · silicon oxide film 19. filler 20 · · η-channel blocking diffusion region 21 · * dotted line 22 · · Solid line 23 · · Solid line 25 * * η-channel blocking diffusion area 2A ·· Ditch 2B · · Ditch 2C · · Ditch 2D · · Ditch 2E · · Ditch 2F · · Ditch 2G ... Ditch 2Η · Ditch 3Α · · · Separation area 5a · Anode lead buried area 30 · Channel blocking diffusion area 31 · η-type buried diffusion area 32 · η-type buried diffusion area 33 · · ρ-type buried diffusion area 3a · · Lower partition Area 35 ... · p-type well 5b. · · Upper anode lead area 40 · · mask pattern 42 · · ditch 41a · · active area 41b · .. active area 3b · · · upper partition area 45 · ♦ First layer polycrystalline silicon film 43. Collector region 44. η-type lead region 45a ♦ Polycrystalline silicon film 45b ♦ Polycrystalline silicon film 46 · Intermediate insulating film 46a · Emitter window 46b · Emitter Window 47 * * * Urgent 48. · · Inner base 49 · · · Outer base 50 * ♦♦ Outer base 51 ... Emitter 52 ...

26 587333 玖、發明說明 55· ·第一層鋁電極 61· ··覆蓋薄膜 60· ·第二層中間絕緣薄膜 56 ♦ ♦第二層鋁電極26 587333 发明, description of the invention 55 · · first layer of aluminum electrode 61 · · · cover film 60 · · second layer of intermediate insulating film 56 ♦ ♦ second layer of aluminum electrode

2727

Claims (1)

587333 拾、申請專利範圍 1.一種半導體元件，包含·· 一底層基體，該底層基體具有至少一個由第一導電 類型之半導體製成的表面層； 一第一層’該第一層係形成於該底層基體上或之上 並且係由具有比該底層基體之表面層之電阻高之電阻的 半導體製成； ίο 一第一雜質擴散區域，該第一雜質擴散區域係被形 成於該第一層的部份表面區域中而且係被摻雜有與該第 一導電類型相反之第二導電類型的雜質，該第一雜質擴 散區域係不到達該底層基體的表面； 第導電類型的第二雜質擴散區域，該第二雜質 擴散區域係被設置於該第一層中而且係與該第一雜質擴 散區域在平面方向上相隔一定的距離，該第二雜質擴散 區域係到達該底層基體的表面；及 15 一第一分隔區域，該第一分隔區域係被設置於該第 與第一雜質擴散之間並且包含一個形成於該第一層中 的溝渠及至少被設置於該溝渠之部份内部區域中的介電 材料。 20 2·如申請專利範圍"項所述之半導體元件，更包含一防 反射薄膜，該防反射薄膜至少被形成於該第一雜質擴散 區域的部份表面區域上。 、月 3.如申請專利範圍第i項所述之半導體元件，更包含用於 把逆向偏壓電愿施加到該第一和第二雜質擴散 極。 电 28 拾、申請專利範圍 4·如申請專利範圍第1項所述之半導體元件，其中，該第 層包含一第一下層和一形成於該第一下層上的第一上 層，該第一下層係被定位從該第一上層到該底層基體而 且係由第一導電類型的半導體製成，該第一下層具有一 個比”亥第一導電類型之底層基體之表面層之雜質濃度低 的雜質濃度。 5·如申請專利範圍第4項所述之半導體元件，其中，該第 一分隔區域係到達一個比在該第一上與下層之間之邊界 深的位置。 6·如申請專利範圍第i項所述之半導體元件，更包含·· 一第二雜質擴散區域，該第三雜質擴散區域被設置 於與該第一雜質擴散區域相鄰之該第一層中、與該第一 和第二雜質擴散區域在平面方向上相隔一定的距離、及 被摻雜有第二導電類型的雜質，該第三雜質擴散區域係 不到達該底層基體的表面；及 一第二分隔區域，該第二分隔區域係被設置於在該 第與第二雜質擴散區域之間的第一層中，該第二分隔 區域係電氣地分隔該第一和第三雜質擴散區域， 其中，該第一分隔區域亦係被設置於該第二與第三 雜質擴散區域之間。 7·如申請專利範圍第6項所述之半導體元件，其中，該第 一分隔區域包含一個摻雜有第一導電類型之雜質的區域 〇 8·如申請專利範圍第7項所述之半導體元件，其中，該第二 29 拾、申請專利範圍 分隔區域係與該第一分隔區域接觸。 9·如申請專利細8項所述之半導體元件，其中，該第 一分隔區域之與該第一分隔區域接觸的區域除了用於形 成該第二分隔區域的雜質植入之外係被摻雜第一導電類 型的雜質。 10·如申請專利範圍第丨項所述之半導體元件，其中，該第 -分隔區域包含數個在該第_和第二雜質擴散區域被分 隔之方向上被設置的部份，該等部份中之每一者包含一 個形成於該第一層中的溝渠及至少被設置於該溝渠之部 份内部區域中的介電材料。 11·如申請專利範圍第！項所述之半導體元件，其中，該第 一分隔區域係被設置與該第二雜質擴散區域相隔。 12·如申請專利範圍第4項所述之半導體元件，其中： 該第一分隔區域係不到達一個在該第一層與該底層 基體之間的界面；及 具有比緊在該第一雜質擴散區域下面之區域之雜質 濃度高之雜質濃度之第一導電類型的一高雜質濃度區域 係形成於在該第一分隔區域之底部上的該第一層中，該 向雜質濃度區域係被設置在該第一下層中而且係不到達 該第一上層。 13. 如申請專利範圍第6項所述之半導體元件，其中，該第 二分隔區域包括一個形成於該第一層中的溝渠及至少被 设置於该溝渠之部份内部區域中的介電材料。 14. 如申請專利範圍第6項所述之半導體元件，其中，該第 拾、申請專利範圍 —分隔區域係被設置從—個在該第—與第二雜質擴散區 域之間的區域延續到—個在該第三與第二雜質擴散區域 之間的區域，而且該第二分隔區域緊靠該第一分隔區域 的侧壁。 15·如申請專利範圍第13項所述之半導體元件，其中，構 成該第二分隔區域的該溝渠係從構成該第一分隔區域的 該溝渠分支出來。 16·如申請專利範圍第7項所述之半導體元件，其中，該第 二分隔區域係到達該第二雜質擴散區域而且該第一分隔 區域係緊靠該第二分隔區域的側壁。 17·如申請專利範圍第i項所述之半導體元件，更包含一個 形成於該第一層之表面層中和上的雙極性電晶體，該雙 極性電晶體包含一個形成於該第一層中的集極區域、一 個被設置於該集極區域與該第一層之上表面之間且係與 ”亥集極區域和該第一層接觸的基極區域、及一個被設置 於該基極區域上且係由雜質摻雜多晶矽製成的射極區域 〇 18· —種半導體元件，包含： 一底層基體，該底層基體具有至少一個由第一導電 類型之半導體製成的表面層； 一第一層’該第一層係形成於該底層基體上而且係 由具有比該底層基體之表面層之電阻高之電阻的半導體 製成； 一第一雜質擴散區域，該第一雜質擴散區域係形成 31 587333 拾、申請專利範圍 於該第一層的部份表面區域中而且係被摻雜有與該第一 導電類型相反之第二導電類型的雜質，該第一雜質擴散 區域係不到達該底層基體的表面； 一第一導電類型的第二雜質擴散區域，該第二雜質 5 擴散區域係被設置於該第一層中而且係與該第一雜質擴 散區域在平面方向上相隔一定的距離，該第二雜質擴散 區域係到達該底層基體的表面； 一形成於該第一層中的溝渠，該溝渠包圍一個設置 有該第一和第二雜質擴散區域的區域；及 10 一介電材料，該介電材料係至少被設置於該溝渠的 部份内部區域中。 32587333 Patent application scope 1. A semiconductor element, including a bottom substrate having at least one surface layer made of a semiconductor of a first conductivity type; a first layer 'the first layer is formed on On or over the underlying substrate and made of a semiconductor having a higher resistance than the surface layer of the underlying substrate; a first impurity diffusion region formed on the first layer Part of the surface area is doped with impurities of the second conductivity type opposite to the first conductivity type, the first impurity diffusion area does not reach the surface of the underlying substrate; the second impurity of the second conductivity type is diffused A region, the second impurity diffusion region is disposed in the first layer and is spaced apart from the first impurity diffusion region in a plane direction by a certain distance, and the second impurity diffusion region reaches the surface of the underlying substrate; and 15 a first separation region, the first separation region is disposed between the first and the first impurity diffusion and includes a formed on the first The trench and at least partially disposed in the interior region of the trench in the dielectric material. 20 2. The semiconductor device according to the item "Scope of the Patent Application" further includes an anti-reflection film, and the anti-reflection film is formed on at least a part of a surface region of the first impurity diffusion region. 3. The semiconductor device as described in item i of the patent application range further includes a voltage for applying a reverse bias voltage to the first and second impurity diffusion electrodes. Electricity 28. Patent application scope 4. The semiconductor device according to item 1 of the patent application scope, wherein the first layer includes a first lower layer and a first upper layer formed on the first lower layer. The lower layer is positioned from the first upper layer to the lower substrate and is made of a semiconductor of a first conductivity type, the first lower layer having an impurity concentration higher than that of the surface layer of the lower substrate of the first conductivity type. Low impurity concentration. 5. The semiconductor device according to item 4 of the scope of patent application, wherein the first separation region reaches a position deeper than a boundary between the first upper and lower layers. 6. As claimed The semiconductor element described in item i of the patent scope further includes a second impurity diffusion region, the third impurity diffusion region being disposed in the first layer adjacent to the first impurity diffusion region and in contact with the first impurity diffusion region. A first impurity diffusion region and a second impurity diffusion region are separated by a certain distance in the plane direction, and are doped with impurities of the second conductivity type, the third impurity diffusion region does not reach the surface of the underlying substrate; and a second A separation region, the second separation region being disposed in a first layer between the first and second impurity diffusion regions, the second separation region electrically separating the first and third impurity diffusion regions, wherein, The first separation region is also disposed between the second and third impurity diffusion regions. 7. The semiconductor device according to item 6 of the scope of patent application, wherein the first separation region includes a doped first A conductive type impurity region 08. The semiconductor device as described in item 7 of the patent application range, wherein the second patent application and the patent application partitioned area is in contact with the first partition region. 9. If the patent is applied for The semiconductor device according to item 8, wherein a region of the first partition region that is in contact with the first partition region is doped with a first conductivity type except for an impurity implantation for forming the second partition region. 10. The semiconductor device according to item 丨 in the scope of the patent application, wherein the -separated region includes a plurality of regions separated in the direction in which the first and second impurity diffusion regions are separated. Each of these sections includes a trench formed in the first layer and a dielectric material disposed in at least a portion of the interior area of the trench. The semiconductor element according to item!, Wherein the first separation region is provided to be separated from the second impurity diffusion region. 12. The semiconductor element according to item 4 of the scope of patent application, wherein: the first separation region is Does not reach an interface between the first layer and the underlying substrate; and a high impurity concentration region system of the first conductivity type having an impurity concentration higher than that of a region immediately below the first impurity diffusion region Formed in the first layer on the bottom of the first separation region, the impurity concentration region is disposed in the first lower layer and does not reach the first upper layer. 13. The semiconductor device according to item 6 of the scope of patent application, wherein the second separation region includes a trench formed in the first layer and a dielectric material disposed at least in a portion of the interior region of the trench. . 14. The semiconductor device according to item 6 of the scope of patent application, wherein the first and the scope of patent application-the separation area is set to continue from an area between the first and second impurity diffusion areas to- A region between the third and second impurity diffusion regions, and the second separation region is abutting a sidewall of the first separation region. 15. The semiconductor device according to item 13 of the scope of patent application, wherein the trench constituting the second partition region is branched from the trench constituting the first partition region. 16. The semiconductor device according to item 7 of the scope of patent application, wherein the second partitioned region reaches the second impurity diffusion region and the first partitioned region is abutted against a side wall of the second partitioned region. 17. The semiconductor device according to item i of the patent application scope, further comprising a bipolar transistor formed in and on the surface layer of the first layer, the bipolar transistor including one formed in the first layer A collector region, a base region disposed between the collector region and the upper surface of the first layer and in contact with the "Hio collector region and the first layer, and a base region disposed on the base And an emitter region made of impurity-doped polycrystalline silicon on the region. A semiconductor device comprising: a bottom substrate having at least one surface layer made of a semiconductor of a first conductivity type; a first One layer 'The first layer is formed on the underlying substrate and is made of a semiconductor having a higher resistance than the surface layer of the underlying substrate; a first impurity diffusion region, the first impurity diffusion region is formed 31 587333 The patent application scope is in a part of the surface area of the first layer and is doped with an impurity of a second conductivity type opposite to the first conductivity type, and the first impurity diffuses The region does not reach the surface of the underlying substrate; a second impurity diffusion region of a first conductivity type, the second impurity 5 diffusion region is disposed in the first layer and is in a plane direction with the first impurity diffusion region Spaced a certain distance apart, the second impurity diffusion region reaches the surface of the underlying substrate; a trench formed in the first layer, the trench surrounding a region where the first and second impurity diffusion regions are disposed; and 10 A dielectric material that is disposed in at least a portion of the interior area of the trench. 32
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US6828644B2 (en) 2004-12-07
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