TW587253B - A voltage recovery switch without device breakdown issue in non-volatile memory - Google Patents

Abstract

A voltage recovery switch for neutralizing a first voltage and a second voltage in a non-volatile memory. The voltage recovery switch comprises a first PMOS transistor whereof a gate is electrically connected to a third voltage and a source is electrically connected to the first voltage; an NMOS transistor whereof a gate is electrically connected to a control signal and a drain is electrically connected to a drain of the first PMOS transistor; and a second PMOS transistor whereof a gate is electrically connected to a fourth voltage, a source is electrically connected to the source of the NMOS transistor, and a drain is electrically connected to the second voltage.

Description

587253 V. Description of the invention -------------------------------------- TECHNICAL FIELD TO THE INVENTION The present invention provides a voltage The recovery switch is suitable for helmet elements of non-volatile memory. … 70 仵, the voltage recovery switch of the Bayer problem. The prior art memory has always been its various memory (Non-Volati 1 meaning that the memory is cut off and volatilized under long-term storage (Flash application One of the most important and indispensable components in the storage of various kinds of electronic data in various electronic products on the market today, and in the memory, can be roughly divided into two categories, namely volatile (V ο 1 ati 1 e Mem ry) and non-volatile memory (Memory), the so-called non-volatile memory, the data stored in the Gu & name memory does not disappear because of the power State characteristics without power supply. Because of this characteristic, such non-volatile memories such as flash memory are widely used in different fields to meet the demands of various electronic products. The non-volatile memory in the conventional technology mostly uses a stacked gate technology, in which a memory cell (Me: 0 ^ y Cell) is formed on a substrate, which includes a drain, A source and a stack gate, and the stack gate usually contains a 587253. V. Description of the invention (2) ------------------------ -A floating gate and a gate), and between the oceanic gate and the base, the electrode (the control and the floating gate is separated by a dioxide layer and controlled by the sea gate) The operation principle of the non-volatile memory of the gate stack gate technology, and the use of a plurality of high-level voltages to the control gate is advantageous. The external or hot electron injection effect is used to change the floating gate. The daughter tooth changes the floating pole with the amount of the effect: =; The wrong digital electronic memory is used for data writing (Program) or for the purpose of the non-volatile (Erase). ', Delete as before The 'because of the complex voltage and a negative voltage of 10V are required for the deletion and deletion) The circuit will include a boost Level voltage to be due to the addition of non-volatile needs. However, after the non-volatile deletion operation (for example, the sexual memory will operate between the normal and 0V ground terminals), the multiple high-level voltages will be charged. However, if the multiple power supply voltages are used, (For example, Vdd, and a negative voltage of 10V, the direct power supply voltage is too high for non-transmitting memory to write data to the South level voltage. (For example, + 10V is usually in the nonvolatile memory. (Charge Pump) to generate the high-incidence § self-memory body for data writing and erasing memory to end data writing or data read operation), the non-volatile power supply voltage (for example, at this time + 3 ¥ The booster circuit will be turned off, and the charge that raises the level voltage through the power supply voltage directly flows into the +10 V positive voltage directly connected to the ground terminal), which will cause the load to flow and cause The jitter of its voltage value

Page 7 587253 V. Description of the invention (3) (Bounce), and this jitter phenomenon will become one of the main sources of noise in the circuit of the non-volatile body and possible malfunction reasons. The problem of the jitter phenomenon caused by the charge power supply voltage of the level voltage, the conventional technique uses a voltage recovery switch circuit (Voltage Recovery Swi tch), before the plurality of high level voltages are discharged through the electrical voltage, First, a path is formed between the plurality of high-level voltages (the positive voltage and the negative voltage), and the charges are electrically neutralized so that the positions of the plurality of high-level voltages gradually decrease, until the plurality of high-level voltages gradually decrease. After the voltage of the high level voltage reaches a certain level, it is connected to the power supply voltage for subsequent discharge. At this time, because the electricity in the high level voltage is no longer as much as before, the charge flows in. The resulting jitter is limited to an acceptable range. Please refer to FIG. 1. FIG. 1 shows a schematic diagram of the voltage-off circuit 10 in the conventional technology. The voltage recovery switch circuit 10 includes a metal oxide semiconductor transistor (hereinafter referred to as an NM0S transistor whose drain is electrically connected to the transistor). Positive voltage (+ 10 V), its gate voltage is the first control signal CTRL1;-P-type metal oxide semiconductor (hereinafter referred to as PM0S transistor) 14, its source is electrically connected to the source of the first crystal 12 Pole, its gate is electrically connected to a fixed voltage value (the source of sexual memory that flows into the system during the operation and the voltage level drops as described above, and the voltage is restored to a first N) 12, and L is connected to a The crystal NM0S is electrically connected to the ground of the first NMOS transistor i 6 in Figure 5.587253. 5. The description of the invention (4); and a second NMOS transistor i 6 whose drain is electrically connected to the drain of the P MOS transistor 14 and its gate. The electrode is electrically connected to a second control signal CTRL 2, and the source is electrically connected to the negative voltage (−1 0ν). For a detailed description of the voltage recovery switch circuit 10, please refer to the following document: JSSC 2000 Nov., " A Channel-Erasing 1.8V-Only 32Mb NOR Flash EEPROM with a Bitline Direct

Sensing Scheme ’’.

When data is written or deleted using the memory of the voltage recovery switch circuit 10, the first control signal CTRL1 and the second control signal CTRL2 control the first NMOS transistor 12 and the second NMOS transistor 16 respectively. It is turned off to prevent the positive voltage and the negative voltage from being neutralized and discharged due to the conduction of the voltage recovery switch circuit 10. Before the memory finishes writing data or deleting data and reads data, the first control signal CTRL 1 and the second control signal CTRL 2 respectively control the first NMOS transistor 12 and the second NMOS transistor 16 to make them Turn on so that the positive voltage and the negative voltage are neutralized and discharged due to the conduction of the voltage recovery switch circuit 10.

The opening and closing of the first NMOS transistor 12 can be directly controlled by using general logic signals (ie, the first control signal CTRL 1 switched between 3 V and 0 V), but the second NMOS transistor 16 is This is not possible because the source of the second NMOS transistor 16 is electrically connected to a large negative voltage (for example, a 10V). Therefore, if the second NMOS transistor 16 is to be turned off, the second control signal is turned off. CTRL2 must input a negative voltage V

Page 9 587253 V. Description of the invention (5) The second NMOS transistor 16 can be operated in a cut-off region (Cut-Off R e g i ο η). Therefore, the second control signal C T R L 2 must be a signal that switches between 3 V and the negative voltage V &, and in order to provide the negative voltage V NR, the circuit design of the memory is bound to be more complicated and the cost is increased. When the second NMOS transistor 16 is turned on, a voltage difference of 3V — (-10V) = 13V must be withstood between the gate and the source, which will cause a device breakdown of the second NMOS transistor. Opportunities have greatly increased. Summary of the Invention

Therefore, the main object of the present invention is to provide a voltage recovery switch circuit capable of preventing the component from crashing, so as to solve the conventional problems. According to the patent application scope of the present invention, a voltage recovery switch circuit is disclosed for neutralizing a first voltage and a second voltage in a non-volatile memory. The voltage recovery switch circuit includes a first P-type metal. An oxide semiconductor transistor, the gate of which is electrically connected to a third voltage,

Its source is electrically connected to the first voltage; a metal oxide semiconductor transistor, its gate is electrically connected to a control signal, and its drain is electrically connected to the drain of the first P-type metal oxide semiconductor transistor. And a second P-type metal oxide semiconductor transistor, its gate is electrically connected to a fourth voltage, its source is electrically connected to the source of the N-type metal oxide semiconductor transistor, and its drain is electrically connected to This second voltage.

Page 10 587253 V. Description of the invention (6) According to the patent application scope of the present invention, a method for neutralizing the first voltage and the second voltage by using the voltage recovery switch circuit described above includes the following steps: using the control A signal to turn off the N-type metal oxide semiconductor transistor, so that the voltage recovery switch circuit is in an off state; and using the control signal to turn on the N-type metal oxide semiconductor transistor, so that the voltage recovery switch circuit is in an on state, The first voltage and the second voltage are charged and discharged. The voltage recovery switch circuit of the present invention uses a control signal to control the opening and closing of the N-type metal oxide semiconductor transistor. Since the control signal is a general logic signal, there is no conventional technology for providing a negative voltage. V 両 makes the circuit design more complicated, and because the second P-type metal oxide semiconductor transistor is interposed between the N-type metal oxide semiconductor transistor and the second voltage, the N-type metal oxide semiconductor Transistors do not have the possibility of component breakdown due to the large voltage difference between their gate and source. Please refer to FIG. 2 for an embodiment. FIG. 2 shows a schematic diagram of the voltage recovery switch circuit 20 of the present invention. The voltage recovery switch circuit 20 is used to neutralize a first voltage V PQ and a voltage in a non-volatile memory. Second voltage V NEG. The voltage recovery switch circuit 20 includes a first PMOS transistor 22, the gate of which is electrically connected to a third voltage VBIAS1, and the source of which is electrically connected to the first voltage VPGS; 587253 丨 V. Description of the invention (7) NMOS transistor 24 Its gate is electrically connected to a control signal CTRL, its drain is electrically connected to the drain of the first PMOS transistor 22; and a second PMOS transistor 26, its gate is electrically connected to a fourth voltage v BIAS2 Its source is electrically connected to the source of the NMOS transistor 24, and its drain is electrically connected to the second voltage V NEG〇 ^ Please note that in this embodiment, the first voltage V p◦ and the second voltage V NEG It is the high-level positive voltage (such as + 10V) and the high-level negative voltage (such as _ 10v) generated by the boosting operation in order to write or delete data to the non-volatile memory. The control signal CTRL is a general logic signal (for example, switching between 3 levels of 0v). Third, the voltage v BIAS and the fourth voltage v bias are fixed bias voltage values. The third voltage fv bias is used to provide the bias voltage required by the first PM transistor 22 to determine the voltage. The circuit is closed. Twenty pairs of the first voltage Vp0 and the second voltage are neutralized and the fourth voltage Vbias is used to provide a bias voltage for the second PMOS transistor 26, so that the NMOS transistor 24 due to the second PMOS Transistor 26 does not cause the aforementioned component collapse problem, and it is grounded in the fourth Leisheng V BIAS county in FIG. Next, the voltage recovery switch η, 20 in FIG. 2 will be used to explain the method of neutralizing the first voltage V and the second voltage VNE in the voltage recovery switch circuit of the present invention.

Figure 3 shows the flowchart of the method for neutralizing the first voltage Vp0 and the second voltage VNE & by the voltage recovery switch in Figure 2. If the second place is not used in step 30, when the non-volatile memory performs data

Page 12 587253 I. 5 'Description of the Invention (8) When writing or deleting data, the operation requires a high level voltage, so the non-volatile memory usually uses a boost circuit included in it to generate High-level first voltage vP0 and second voltage 1 Vneg, and will switch the control signal CTRL to a logic value π 0 ”(for example, enter a ground voltage 0V) to turn off the NMOS transistor 24 and restore the voltage switch. Network 20 is in a cut-off state. #

In step 32, when the non-volatile memory reads data, since the operation does not need to use a high level voltage, the non-volatile memory uses a general power supply voltage (such as 3 V) for data The reading operation closes the boost circuit, and at the same time, the control signal is switched to a logic value. Γ (for example, the power supply voltage 3V) turns on the transistor 24 so that the voltage recovery switch circuit 20 is in a conducting state. At this time, due to the generation between the first voltage V PG and the second voltage V NE, a current path, the first voltage VP◦ and the second voltage VNEdf conduct electric charge and discharge, until the value of the first voltage VPG is equal to the third voltage VBIAS. After adding the value of the Threshold Voltage of the second PM0st crystal 22 to the value, the 'first PM0S transistor 22 will not be turned on, and the voltage recovery switch circuit> 20 will enter an off state. Next, as described in the prior art, the first to the first voltages V P are again applied. And the second voltage V NE is connected to the power supply voltage and continues to perform subsequent discharges until it reaches the Stand-By potential. At this time, the amount of charge in the first voltage V PQ and the first voltage V NEG is no longer obtained as before. There are many, so that the jitter phenomenon of the voltage value caused by the inflow of charges is limited to an acceptable range.

Page 13 587253 I. Explanation of the invention (9)

For example, if the value of the first voltage V PG is +1 0V, the value of the third voltage | VBIASi ^ is 3V ', and the threshold voltage of the first PMOS transistor 22 is 0 · 7 V, then After the first voltage V p◦ and the second voltage V NE and the voltage recovery switch circuit 20 are in the on state and start to neutralize and discharge, the absolute values of the first voltage v P0 and the second voltage V NEG ^ will start due to charge neutralization. When the value of the first voltage VPG drops to 3.7V, due to the voltage difference VSG between the source and gate of the first PMOS transistor 22 (equal to the first voltage VP0 minus the third voltage VBIAS々) (3 · 7V—3V = 0 · 7V) is equal to the threshold voltage of the first PM0S transistor 22, so the first PM0S transistor 22 will enter the cut-off region and the voltage will be restored. The circuit 20 enters a cut-off state. Please note that the value of the third voltage V biasA can be between 0V and the first voltage V according to actual needs. As described above, the voltage recovery switch circuit 20 can complete the actions of neutralizing the first voltage VPQ and the second voltage VneA.

Compared with the voltage recovery switch circuit of the conventional technology, the voltage recovery switch circuit of the present invention uses a control signal to control the opening and closing of the NMOS transistor. Since the control signal is a general logic signal, there is no practice In order to provide a negative voltage V to make the circuit design more complicated in the known technology, and because the second PM0S transistor is inserted between the NMOS transistor and the second voltage, the NMOS transistor will not be affected by its gate. The voltage difference between the source and the source is too large, and there is a possibility of component breakdown.

Page 14 587253

Page 15

587253 I _ " ~ 'I diagram brief description I diagram brief description:

I

I

FIG. 1 is a schematic diagram of a conventional voltage recovery switch circuit. FIG. 2 is a schematic diagram of a voltage recovery switch circuit according to the present invention. FIG. 3 is a flowchart of the operation of the voltage recovery switch circuit of FIG. 2.

I Symbol description:

10, 20 Voltage recovery switch circuit 12 '16 ^ 24 NMOS transistor 14 ^ 11, 26 PMOS transistor Page 16

Claims (1)

587253 VI. Scope of patent application1. A voltage recovery switch circuit (V ο 11 age R ecvery I Sw it ch) for neutralizing a first voltage and a second voltage in a non-volatile memory, The voltage recovery switch circuit includes: a first P-type metal oxide semiconductor transistor, the gate of which is electrically connected to a third voltage, and the source of which is electrically connected to the first voltage; an N-type metal oxide semiconductor A transistor whose gate is electrically connected to a control signal, and whose drain is electrically connected to the sum of the first P-type metal oxide semiconductor transistor; and A second P-type metal oxide semiconductor transistor has its gate electrically connected to a fourth voltage, its source is electrically connected to the source of the N-type metal oxide semiconductor transistor, and its drain is electrically connected to the first Two voltages. 2. The voltage recovery switch circuit according to item 1 of the scope of the patent application, wherein the first voltage is a positive voltage generated by the non-volatile memory through a boosting operation when writing or erasing data. 3. The voltage recovery switch circuit according to item 1 of the scope of patent application, wherein the third voltage is a positive voltage greater than 0V and less than the first voltage. 4. The voltage recovery switch circuit as described in item 1 of the scope of the patent application, wherein the second voltage is a negative voltage generated by the non-volatile memory through a step-up operation when writing or erasing data. Page 17 587253 6. Scope of patent application 5. The voltage recovery switch circuit as described in item 1 of the scope of patent application, wherein the fourth voltage is a ground voltage. 6. The voltage recovery switch circuit according to item 1 of the scope of the patent application, wherein the non-volatile memory further includes a power supply voltage, and when the control signal is a logic value "Γ ', its potential is the power supply voltage, When the control signal is a logic value "(Γ), its potential is the ground voltage. 7. The voltage recovery switch circuit as described in item 6 of the scope of patent application, wherein when the control signal is a logic value π Ο π, the N-type metal oxide semiconductor transistor is turned off, and the voltage recovery switch circuit is In a cut-off state. 8. The voltage recovery switch circuit according to item 6 of the scope of the patent application, wherein when the control signal is a logic value π Γ, the N-type metal oxide semiconductor transistor is turned on, and the voltage recovery switch circuit is at A conduction state. 9. The voltage recovery switch circuit according to item 8 of the scope of the patent application, wherein when the voltage recovery switch circuit is in the on state, the first voltage and the second voltage are charged with electricity and discharged until the first voltage is discharged. After the value of the voltage is equal to the value of the third voltage plus the threshold voltage of the first P-type metal oxide semiconductor transistor, the first P-type metal oxide semiconductor transistor will not conduct, and Makes the Page 18 587253 6. Scope of patent application The voltage recovery switch circuit enters a cut-off state. 10. A method of neutralizing a first voltage and a second voltage, used in a non-volatile memory, the non-volatile memory includes a voltage recovery switch circuit, the voltage recovery switch circuit includes: a first The gate of the P-type metal oxide semiconductor transistor is electrically connected to a third voltage, and the source thereof is electrically connected to the first voltage; the gate of the N-type metal oxide semiconductor transistor is electrically connected to a control signal. Its drain is electrically connected to the drain of the first P-type metal oxide semiconductor transistor; and a second P-type metal oxide semiconductor transistor, its gate is electrically connected to a fourth voltage, and its source is electrically The drain electrode is connected to the source of the N-type metal oxide semiconductor transistor, and the drain is electrically connected to the second voltage. The method includes the following steps: using the control signal to turn off the N-type metal oxide semiconductor transistor, so that the The voltage recovery switch circuit is in a cut-off state; and the control signal is used to turn on the N-type metal emulsified layer semiconductor transistor, so that the voltage recovery switch circuit is in a conductive state. State, and the first voltage and the second voltage and the charge and discharge flow. 1 1. The method as described in item 10 of the scope of patent application, wherein the first voltage is a positive voltage generated by the non-volatile memory through a step-up operation when writing or erasing data. Page 19 587253 VI. Scope of patent application 1 2. The method described in item 10 of the scope of patent application, wherein the third voltage is a positive voltage greater than 0 V and less than the first voltage. 1 3. The method as described in item 10 of the scope of patent application, wherein the second voltage is a negative voltage generated by the non-volatile memory through a step-up operation when writing or erasing data. 14. The method as described in item 10 of the scope of patent application, wherein the fourth voltage is a ground voltage. 15. The method according to item 10 of the scope of patent application, wherein the non-volatile memory further includes a power supply voltage. When the control signal is a logic value π 1π, its potential is the power supply voltage. When the control signal is at a logic value of π Ο π, its potential is the ground voltage. 16. The method according to item 15 of the scope of patent application, wherein when the control signal is at a logic value of π 0 π, the N-type metal oxide semiconductor transistor is turned off. 1 7. The method according to item 15 of the scope of patent application, wherein when the control signal is a logic value π Γ, the N-type metal oxide semiconductor transistor is turned on. 18. The method as described in item 10 of the scope of patent application, wherein when the voltage 587253 i Sixth, the scope of the patent application I When the switch circuit is in the on state, the first voltage and the second voltage will conduct charge circulation and discharge until the value of the first voltage is equal to the value of the third voltage plus the After the value of the threshold voltage of the first p-type metal oxide semiconductor transistor, the first p-type metal oxide semiconductor transistor will not be turned on, and the voltage recovery switch circuit will enter the cut-off state. Page 21