TW584955B - Method and apparatus for controlling current demand in an integrated circuit - Google Patents

Method and apparatus for controlling current demand in an integrated circuit Download PDF

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Publication number
TW584955B
TW584955B TW091107456A TW91107456A TW584955B TW 584955 B TW584955 B TW 584955B TW 091107456 A TW091107456 A TW 091107456A TW 91107456 A TW91107456 A TW 91107456A TW 584955 B TW584955 B TW 584955B
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Taiwan
Prior art keywords
circuit
power
power consumption
current
voltage
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TW091107456A
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Chinese (zh)
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David T Blaauw
Rajendran V Panda
Rajat Chaudhry
Vladimir P Zolotov
Ravindraraj Ramaraju
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Motorola Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)

Abstract

The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure (18), power consumption circuitry (20), and power consumption control circuitry (62) for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.

Description

玖、發明說明： 【發明所屬之技術領域】 本發明一般關於積體電路，及特別關於控制一積體電路 中之電流需求。 【先前技術】 一微處理器，微控制器或任何其他形式的積體電路或晶 片的電源供應電壓隨著其電能需求之改變所造成的電壓過 低及過高而損壞。電能需求之改變可能發生在一積體電路 所執行的不同指令流具有不同電能需求時，且在某些狀況 下，該改變是劇烈的，如當積體電路離開或進入靜止狀態 時。此導致一問題，因為若電源供應電壓改變超過可接受 範圍，積體電路會不正常動作。 在電流劇烈改變期間的大的電壓變化主要由封裝、接 線、一晶片上互連線中的寄生電感所產生。因此，電源供 應電壓之過高或過低之量則直接正比於dl/dt · L/C，其中 L是封裝及晶片上互連線的電感及C是積體電路（或晶片上） 去耦合電容。 一個解決此問題的方案係增加積體電路去耦合電容，使 得電壓過低或過高的量減少。然而，由於在積體電路内需 要大面積以置放該等去耦合電容，以較大積體電路分離電 容作為解決方案的可行性受到限制。而且，因為電源供應 電壓的過多或過低的量是正比於去耦合電容的增加的平方 根，去耦合電容的任何增加量的效果則被減少。此外，當 微處理器，微控制器，或其他積體電路變得更快且電流消 耗增加時，電源供應電壓過多及過低的問題更加惡化。因 此’需要監視和控制電源供應電壓的過多及過低問題以保 持在可接受範圍。 【發明内容】 如在此所述，術語”匯流排”指的是多個用於傳送一個或 夕個不同形式資訊，如資料、位址、控制、或狀態的訊號 或導體。’，有效”及”無效”（或”失效”）則用於表示一訊號、狀 態位元、或相似裝置各別在其邏輯為真或邏輯為偽的狀 匕、若邏辑真狀版為一邏輯壹，則邏輯偽狀態為一邏輯零。 及若邏輯真狀態為一邏輯零，則邏輯偽狀態為一邏輯壹。 本金明的具體貪施例一般關於監視和控制電能消耗電路 (如一積體電路）的電能消耗（如電流需求）以防止供給電壓 過低、過高及振盪所導致的破壞。例如，本發明的一方面 是關於-種控制積體電路内電流需求的方法，該積體電路 具有電能消耗電路。該方法包括檢測是否至少一預定過高 及一預定過低之-出現或如所預測在—電源供應電壓内， 及如果在胃電能供應電壓内檢測到—職過高ϋ定過 低，則控制由該電能消耗電路所消耗的電流以確保電源供 應電壓將保持在-預定電源供應電壓位準之—預定邊界 内。 1 本發明的另一方面是關於一包各 G ο私备去牵馬合結構的積 電路，以在電源供應電壓位準 战」時棱供電流及用以在 源供給電壓位準增大時消耗雷& 一 千曰人1鳥。孩積體電路也包含用 消耗電能的電能消耗電路及用 用以控制至少電能消耗電路 584955 電壓而提供或消耗電流 〜、知髌電路電容分離結構18 般A系統10内不執行供應或消 巧耗私，鳥以外的其他功能）。 了以理解的是，圖！的系統1〇只 奋攸4 ΗΓ日 疋間早的一個固有電答或 5際相關元件的概圖。因此，熟知本技藝之人士可瞭解一 耦合至一電路板的封裝積體 胃、 上 _ ^ J Μ不冋形式呈現。例 口 ’系統10可使用一更複雜或更簡單的表達方式。 若板位階分離結構16提供W電容，則板位階去耗合結 構16可有效使封裝6屏蔽而免於板電能互連線η導入的電 感’使得-標稱怔定電壓出現在節點24。然而，即使板位 階，路4的電感可以由足夠高水準的板位階分離結構“所 屏蔽，寄生電感會在節點24後由封裝相互連接丨4導入。因 此’電源供應電壓過高及過低係直接正比於di/dt · l/c， /、中L疋封裝6(亦即，封裝互連線14)及積體電路電能互連 線22的電感，且c是經由積體電路電容分離結構^所提供， 及di/dt指的是電能消耗電路2〇所需求的電流的改變率。 因此，如上所述，為了減少供應電壓過高及過低的振幅， 孩封裝電感（L)可被減少或者是積體電路去耦合電容（c)可 以增加。然而，如上所述，增加c值及減少L值存有限制。 例如，如上所述，為了增加c，積體電路8内需要更多面積。 而且’當科技進步及要製造更複雜的積體電路時，封裝的 寄生電感就不可能減少。例如，因為封裝互連線14及積體 電路電能互連線22的寄生電感是與積體電路及封裝的實際 尺寸有關，其對減少L而超過一特定位準以上即存在有限 制。此外，增加C或減少L的效果變小，因為L/C是在平方 -10- 高的增加閥限值，且電壓波形67將最後穩定在一低電能標 稱Vdd位準附近。因此，電能間歇性增加將增加整個轉換時 間，因此使得整個dt 83現在大於dt81而不會有電能的間歇 性增加，因此導致dl/dt減少且一控制的電壓供應過高。 相似地，為說明圖3所示的問題，如參考圖5和圖6所示 者，電能消耗可能間歇地中斷或間歇地增加，，端視是否 電流轉換從部份電能操作至全電能操作或全電能操作至部 份電能操作而定。經由斷續中斷或增加電能消耗，在低電 能指令流和高電能指令流之間或高電能指令流和低電能指 令流之間的轉換時間（如dt)則分別增加，因此減少整體的 dl/dt。如圖5和6所示，這可控制因為在電能位階之間較快 電流轉換所造成的的減幅振盪效應。 圖7說明電能中斷電路的間歇中斷以說明圖4所述問題。 為防止匹配系統10的電源供給網路共振頻率的週期性高電 能及低電能指令所造成的破壞性電壓過高或過低，電能消 耗可以被中斷（如部分48和52)此造成最終相位偏移，該最終 週期型態與共振頻率不匹配。此外，電能消耗可以間歇地 增加（部分50和54)，其與間歇中斷（部分48和52)—同控制 Vdd的所有減幅振盪。每當Vdd到達一對應閥限時，電能會 被減少、增加或返回至正常電能消耗。當電流轉換從部份 電能操作至全電能操作（如轉換從執行低電能作動至高電 能操作）時，Vdd減少直至到達較低減少的閥限（在點71)為 止，在此點正常電能消耗被中斷（如部分48)。Vdd接著增加 直至到達較高的減少閥限（在點73)為止，在此點電能消耗電 -17- 584955 及一閥限值並提供一控制訊號至電能消耗減少控制電路64 或電能消耗增加控制電路66。例如，比較器68和70每個皆 提供一控制訊號至減少控制電路64，且比較器72和74每個 則提供一控制訊號至增加控制電路66。當對應閥限到達時 這些控制訊號則因此確定執行。说明 Description of the invention: [Technical field to which the invention belongs] The present invention relates generally to integrated circuits, and in particular to controlling current demand in an integrated circuit. [Previous Technology] A microprocessor, microcontroller, or any other form of integrated circuit or chip's power supply voltage is too low and too high to cause damage due to changes in its power requirements. Changes in electrical energy demand may occur when different instruction streams executed by an integrated circuit have different electrical requirements, and in some cases, the change is dramatic, such as when the integrated circuit leaves or enters a stationary state. This leads to a problem because if the power supply voltage changes beyond an acceptable range, the integrated circuit may malfunction. Large voltage changes during drastic changes in current are mainly caused by parasitic inductance in the package, wiring, and interconnections on a chip. Therefore, the amount of power supply voltage that is too high or too low is directly proportional to dl / dt · L / C, where L is the inductance of the package and the interconnect on the chip and C is the integrated circuit (or on-chip) decoupling capacitance. One solution to this problem is to increase the decoupling capacitance of the integrated circuit so that the amount of voltage is too low or too high. However, since a large area is required in the integrated circuit to place such decoupling capacitors, the feasibility of using a larger integrated circuit to separate the capacitors as a solution is limited. Furthermore, because the amount of excessive or low power supply voltage is proportional to the square root of the increase in decoupling capacitance, the effect of any increase in decoupling capacitance is reduced. In addition, as microprocessors, microcontrollers, or other integrated circuits become faster and current consumption increases, the problem of excessive and low power supply voltages worsens. Therefore, it is necessary to monitor and control the excessive and low voltage of the power supply to keep it within acceptable range. [Summary] As described herein, the term "bus" refers to a plurality of signals or conductors used to transmit one or more different forms of information, such as data, address, control, or status. ', Valid' and 'invalid' (or 'invalidate') are used to indicate that a signal, status bit, or similar device has a logic of true or false, respectively. A logical one means that the logical pseudo state is a logical zero. And if a logical true state is a logical zero, then the logical pseudo state is a logical one. The specific embodiments of the present invention are generally related to monitoring and controlling power consumption circuits (such as a product). Power circuit (such as current demand) to prevent the supply voltage from being too low, too high, and damage caused by oscillation. For example, one aspect of the present invention relates to a method for controlling the current demand in a product circuit. The body circuit has a power consumption circuit. The method includes detecting whether at least one predetermined over-high and one predetermined under-low occur or are predicted to be within-the power supply voltage, and if detected within the gastric power supply voltage-the job is too high If the setting is too low, the current consumed by the power consumption circuit is controlled to ensure that the power supply voltage will remain within a predetermined boundary of the predetermined power supply voltage level. 1 Another aspect of the present invention On the one hand, it is about a package of integrated circuits that are designed to pull the horses, so as to supply current at the time of the power supply voltage level and to consume lightning when the level of the source supply voltage increases. Qian Yueren is a bird. The product circuit also includes a power consumption circuit that consumes power and a current that is used to supply or consume power to control the voltage of at least the power consumption circuit 584955 ~, knowing the circuit capacitor separation structure 18. Generally, no supply or consumption is performed in the A system 10 Private, other functions than birds). To understand, the picture! The system is only a schematic diagram of an inherent electrical response or interrelated component of the early 4th day. Therefore, those skilled in the art can understand that a packaged body coupled to a circuit board is presented in the form of a stomach. For example, the system 10 may use a more complex or simpler expression. If the plate-level separation structure 16 provides W capacitance, the plate-level deconsumption structure 16 can effectively shield the package 6 from the inductance induced by the plate power interconnection line η, so that a nominal nominal voltage appears at the node 24. However, even at the plate level, the inductance of the circuit 4 can be shielded by a sufficiently high level of the plate level separation structure, and the parasitic inductance will be introduced from the package to each other after the node 24. Therefore, 'the power supply voltage is too high and too low. Directly proportional to di / dt · l / c, /, the inductance of the medium L 疋 package 6 (ie, the package interconnection 14) and the integrated circuit power interconnection 22, and c is a capacitor separation structure via the integrated circuit ^ Provided and di / dt refer to the rate of change of the current required by the power consumption circuit 20. Therefore, as described above, in order to reduce the excessively high and low amplitude of the supply voltage, the package inductance (L) can be Decreasing or increasing the decoupling capacitance (c) of the integrated circuit can be increased. However, as described above, there are restrictions on increasing the value of c and decreasing the value of L. For example, as described above, in order to increase c, more is required in the integrated circuit 8. Area. Also, as technology advances and more complex integrated circuits are to be manufactured, the parasitic inductance of the package cannot be reduced. For example, because the parasitic inductance of the package interconnect 14 and the integrated circuit power interconnect 22 are The actual circuit and package There are restrictions on reducing L beyond a certain level. In addition, the effect of increasing C or decreasing L becomes smaller, because L / C is an increase of the threshold value in the square -10- high, and the voltage The waveform 67 will finally stabilize near a low power nominal Vdd level. Therefore, an intermittent increase in power will increase the entire conversion time, so that the entire dt 83 is now greater than dt81 without an intermittent increase in power, which results in dl / dt decreases and a controlled voltage supply is too high. Similarly, to illustrate the problem shown in Figure 3, as shown in Figures 5 and 6, the power consumption may be intermittently interrupted or increased intermittently, depending on whether the current Switch from partial power operation to full power operation or full power operation to partial power operation. Through intermittent interruption or increased power consumption, between low power instruction flow and high power instruction flow or high power instruction flow and low The conversion time (such as dt) between the power instruction streams is increased respectively, thus reducing the overall dl / dt. As shown in Figures 5 and 6, this can control the reduction caused by the faster current conversion between power levels. Oscillation effect. Fig. 7 illustrates the intermittent interruption of the power interruption circuit to illustrate the problem described in Fig. 4. In order to prevent the periodic high energy and low energy commands caused by the resonance frequency of the power supply network of the matching system 10 from being too destructive or too high, Too low, the power consumption can be interrupted (such as sections 48 and 52), which causes a final phase shift, the final period pattern does not match the resonance frequency. In addition, the power consumption can be increased intermittently (sections 50 and 54), which Intermittent Interruptions (Parts 48 and 52) —Same as all damping oscillations that control Vdd. When Vdd reaches a corresponding threshold, the power will be reduced, increased, or returned to normal power consumption. When the current conversion is operated from partial power to full When power operation (such as switching from performing a low power operation to high power operation), Vdd decreases until a lower reduced threshold is reached (at point 71), at which point normal power consumption is interrupted (eg, section 48). Vdd then increases until it reaches a higher reduction threshold (at point 73), at which point power consumption -17-584955 and a threshold value and provides a control signal to power consumption reduction control circuit 64 or power consumption increase control Circuit 66. For example, the comparators 68 and 70 each provide a control signal to the decrease control circuit 64, and the comparators 72 and 74 each provide a control signal to the increase control circuit 66. These control signals are therefore determined to be executed when the corresponding threshold is reached.

減少控制電路64提供一控制訊號84至時脈調整電路78。 控制訊號84則執行以響應送至減少控制電路64的輸入。例 如，當較低減少閥限達到時，控制訊號84可以執行。時脈 調整電路78也接收CLK(一時脈訊號）並輸出ADJUSTED CLK(調整後的時脈訊號）。例如，在一具體實施例中，時脈 調整電路78可為時脈閘控電路，其中ADJUSTED CLK為閘 控時脈訊號。CLK可為電能消耗電路20中的任何閘控時脈 訊號。例如，其可以是一全區或局部時脈。而且，時脈調 整電路78可將電能消耗電路20内的所有時脈訊號調整進一 步向下。例如，時脈調整電路78可致動電能消耗電路20内 既有電能管理電路以調整時脈。此外，時脈調整電路78可 替換為其他電能中斷電路，如管路停止電路，其係導致電 能消耗電路内管路線停止而非中斷任何時脈訊號。此外， 其他電能中斷電路延遲或停止所有可能的架構電路而非管 路的可被使用。在替代具體實施例中，所有其他電路可使 用來取代時脈調整電路78以中斷電能消耗電路20的電能消 耗（如電流需求）。 增加控制電路66提供一控制訊號82至一電能消耗電路 80。電能消耗電路80 ’則搞合在Vdd和地之間及被模擬為一 -19- 584955 二Γ較高增加閥限達到時。當控制訊號82被執行時， =耗電⑽被致能以增加㈣_路2㈣電 (如^需求）。電能消耗電⑽可以是電能消耗電路2〇的— 既有邵分，其可用以依需要消耗電能。例如，電能消耗電 二。：包括被增加電能以增加電能消耗的電路閒置區塊。 在曰代具體實施例中，電能消耗電路8〇可以是 路20内可用來只增加電能消耗的電路。 匕y私 圖8可參考圖5-7而更進—步瞭解。例如，如圖μ所示， 當vdd到達較低減少閥限值時，比較器7g執行其控制訊號至 減少控制電賴，其響應接收來自比較器Μ的執行控訊 號，而執行控制訊號84。時脈調整電路78接著致能電能消 耗中斷直至比較器68檢測到較高減少閥限已到達為止，在 該較高減少闕限點’控制訊號84被抑能且正常電能消耗再 繼續。:相似地，如圖5_7所示，當Vdd到達較高閥限值時， 匕較m 72執行其控制訊號至增加控制電路，其響應而執 仃控制訊號82。電能消耗電路8〇接著使電能消耗增加，直 到比較器74偵測到已達到較低增加閥限為止，在此點，控 制訊號82被抑能且正常電能消耗再繼續。 二 雖然-四點控制系統利用兩組較高及較低閥限說明，但 =於一般控制原理的替代方法可被使用。例如，電能控制 包各62可被„又汁以不僅監控絕對電壓值也監視電壓改變 率。或者，替代控制系統可增量地改變任何分佈電路，例 如電能消耗電路80的電能消耗，同樣的會以電能消耗電 -20- 效益、其他優點和問題解答已參考特定具體實施例如上 所馬述》而，效益、優點、問題解答及所有可能導致上 ’義K兀件並非解釋為本發明中請專利範圍之一關鍵、 必需或基本之特徵或元件。如在此使用的術語，，，包含"，” :有或“可其他芡化係用以涵蓋-非除外的包含，使得包 7、、且70件的—程序、方法、物件或裝置並不僅包括該等 /件而疋可以包括其他未明確列於或固有於此種程序、方 法、物件或裝置的元件。 【實施方式】 【圖式簡單說明】 α本發明隸由範例及未限於之該㈣圖說明，其中相同 號碼表示相同元件，及其中： 圖1說明根據本發明的一具體實施例之系統的部份方塊 圖及部份示意圖； 圖2說明對應於電能管理暫態之電流和電壓波形，· 圖3說明對應於流入電能暫態的電流和電壓波形； 圖4說明對應於週期電能暫態的電流和電壓波形； 圖5-7說明根據本發明的具體實施例之電流和電壓波形，· 圖8說明根據本發明的具體實施例，圖1的電能消耗電路 之一部份之方塊圖。 習知本技者瞭解附圖之元件僅為簡單及清楚之說明目的 及並非70全等比例畫出。例如，附圖内元件的部份尺寸可 相對其他元件予以放大以協助增加瞭解本發明的具體實施 -22- 584955 例。 【圖式元件符號說明】 4 板 6 封裝 8 積體電路 10 系統 11 板電能互連線 12 電源供應 14 封裝互連線 16 板去耦合結構 18 積體電路電容性去耦合結構 20 電能消耗電路 22 積體電路電能互連線 24 節點 30 電流波形 31 平坦部分 32 波形 33 部分 34 電壓波形 36 點 37 點 38 電壓波形 39 點 41 暫態時間The reduction control circuit 64 provides a control signal 84 to the clock adjustment circuit 78. The control signal 84 is executed in response to an input sent to the reduction control circuit 64. For example, when the lower reduction threshold is reached, the control signal 84 may be executed. The clock adjustment circuit 78 also receives CLK (a clock signal) and outputs ADJUSTED CLK (an adjusted clock signal). For example, in a specific embodiment, the clock adjustment circuit 78 may be a clock gated circuit, where ADJUSTED CLK is a gated clock signal. CLK may be any gated clock signal in the power consumption circuit 20. For example, it can be a global or local clock. Moreover, the clock adjustment circuit 78 can adjust all the clock signals in the power consumption circuit 20 further down. For example, the clock adjustment circuit 78 may activate an existing power management circuit in the power consumption circuit 20 to adjust the clock. In addition, the clock adjustment circuit 78 may be replaced with other power interruption circuits, such as a pipeline stop circuit, which causes the internal circuit of the power consumption circuit to stop instead of interrupting any clock signal. In addition, other power interruption circuits delay or stop all possible architectural circuits rather than the use of circuits. In alternative embodiments, all other circuits may be used in place of the clock adjustment circuit 78 to interrupt the power consumption (e.g., current demand) of the power consumption circuit 20. Adding the control circuit 66 provides a control signal 82 to a power consumption circuit 80. The power consumption circuit 80 ′ is matched between Vdd and ground and is simulated as -19- 584955 when two higher increase thresholds are reached. When the control signal 82 is executed, the power consumption is enabled to increase the power of the circuit (such as the demand). The power consumption battery can be the power consumption circuit 20-an existing Shaofen, which can be used to consume power as needed. For example, electricity consumes electricity. : Includes unused blocks of circuits that have been increased in power to increase power consumption. In a specific embodiment, the power consumption circuit 80 may be a circuit in the circuit 20 that can be used to increase only the power consumption. Figure 8 can be further referred to Figure 5-7-further understanding. For example, as shown in Figure µ, when vdd reaches a lower reduction threshold value, the comparator 7g executes its control signal to the reduction control signal, and in response to receiving the execution control signal from the comparator M, it executes the control signal 84. The clock adjustment circuit 78 then enables interruption of power consumption until the comparator 68 detects that a higher reduction threshold has been reached, at which control signal 84 is disabled and normal power consumption continues. : Similarly, as shown in Figure 5_7, when Vdd reaches a higher threshold value, the dagger m 72 executes its control signal to increase the control circuit, and it executes the control signal 82 in response. The power consumption circuit 80 then increases the power consumption until the comparator 74 detects that the lower increase threshold has been reached. At this point, the control signal 82 is disabled and normal power consumption continues. Two Although the four-point control system is described using two sets of higher and lower thresholds, alternatives to general control principles can be used. For example, each of the power control packets 62 may be monitored to monitor not only the absolute voltage value but also the rate of change of the voltage. Alternatively, the alternative control system may incrementally change the power consumption of any distribution circuit, such as the power consumption of the power consumption circuit 80. With the power consumption of -20- benefits, other advantages and answers to questions have been referred to specific specific implementation examples described above, and the benefits, advantages, answers to questions and all the elements that may lead to the above is not to be interpreted in the present invention. One of the key, required, or essential features or elements of the patent scope. As the term is used herein, includes ",: has or "may be other inclusive systems to cover-non-exclusive inclusions, such that And 70 pieces—the program, method, object, or device does not only include these / pieces, but may include other elements not explicitly listed or inherent in such a program, method, object, or device. [Embodiment] [Figure] Brief description of the formula] α The present invention is illustrated by an example and not limited to this figure, wherein the same number represents the same element, and among them: FIG. 1 illustrates a device according to the present invention. Partial block diagram and partial schematic diagram of the system of the embodiment; Fig. 2 illustrates current and voltage waveforms corresponding to power management transients, and Fig. 3 illustrates current and voltage waveforms corresponding to incoming power transients; Fig. 4 illustrates corresponding to Current and voltage waveforms of periodic electrical energy transients; Figures 5-7 illustrate current and voltage waveforms according to a specific embodiment of the invention; Figure 8 illustrates a part of the power consumption circuit of Figure 1 according to a specific embodiment of the invention The block diagram of the art. The person skilled in the art understands that the elements of the drawings are only for simple and clear illustration purposes and are not drawn in full scale. For example, the dimensions of some elements in the drawings can be enlarged relative to other elements to help increase Understand the specific implementation of the present invention -22- 584955. [Illustration of symbolic components of the diagram] 4 board 6 package 8 integrated circuit 10 system 11 board power interconnection 12 power supply 14 package interconnection 16 board decoupling structure 18 product Body Circuit Capacitive Decoupling Structure 20 Power Consumption Circuit 22 Integrated Circuit Power Interconnection Line 24 Node 30 Current Waveform 31 Flat Section 32 Waveform 33 Section 34 Pressure waveform 36 the voltage waveform points 37 points 38 39 41 transient time points

-23 - 波形 暫態時間 波形 中斷的電能消耗部分 間歇性增加的電能消耗部分 上升部分 中斷的電能消耗部分 增加的電能消耗部分 間歇性增加的電能消耗部分 點 點 監視電路 點 電能消耗控制電路 電能消耗減少控制電路 電壓波形 電能消耗增加控制電路 電壓波形 比較器 電流波形 比較器 點 比較器 點 -24- 比較器 點 點 時脈調整電路 波形 電能消耗電路 暫態時間 控制信號 暫態時間 控制信號 -25 --23-Waveform transient time Waveform interrupted power consumption part intermittently increased power consumption part Rising part interrupted power consumption part Increased power consumption part intermittently increased power consumption part Point monitoring circuit Point power consumption control circuit Power consumption Reduce control circuit voltage waveform power consumption Increase control circuit voltage waveform comparator current waveform comparator point comparator point -24- comparator point clock adjustment circuit waveform power consumption circuit transient time control signal transient time control signal -25-

Claims (1)

執行提供給該電能消耗電路的至少一部分之一時脈的 停止和開始之一。 6. —種積體電路，包含： 一種電容性去耦合結構（18)，用以在電源供應電壓位準 減少時提供電流，及在電源供應電壓增加時消耗電流； 電能消耗電路（20)，用以消耗電能；及 電能消耗控制電路（62)，用以控制該電能消耗電路的至 少一部分所消耗的電流， 該電能消耗控制電路耦合至該電能消耗電路。 7. 如申請專利範圍第6項之積體電路，其中該電能消耗控制 電路包含： 電能消耗減少控制電路（64)，用以減少由該電能消耗電 路的至少一部分所消耗的電流； 電能消耗增加控制電路（82)，用以增加由該電能消耗電 路的至少一部分所消耗的電流；及 監視電路（60)，用以比較一電源供應電壓與一預定電 壓，該監視電路耦合至該電能消耗減少控制電路及至該 電能消耗增加控制電路。 8. 如申請專利範圍第7項之積體電路，另包含： 電能消耗電路（80)，被耦合以從該電能消耗增加控制電 路接收至少一控制訊號，該電能消耗電路選擇性地消耗電 能。 9. 如申請專利範圍第6項之積體電路，另包含： 時脈調整電路，被耦合以從該電能消耗增加控制電路接 584955 收至少一控制訊號，該時脈調整電路調整一提供至該電 能消耗電路之至少一部分的時脈訊號，其中該時脈調整 電路選擇性地中斷該提供至該電能消耗電路之至少一部 分的時脈訊號。 10. —種積體電路，包含： 電能消耗電路（20)，用以消耗電能； 電能消耗控制電路（62)，用以控制該電能消耗電路的至 少一部分所消耗的電流，該電能消耗控制電路耦合至該 電能消耗電路，其中該電能消耗控制電路包含監視電路 (60)，用以比較一電源供應電壓與一預定電壓；及 時脈調整電路（78)，耦合至該電能消耗控制電路，該時 脈調整電路調整一提供至該電能消耗控制電路之至少一 部分的時脈訊號。One of stop and start of one of the clocks provided to at least a part of the power consumption circuit is performed. 6. —A kind of integrated circuit, comprising: a capacitive decoupling structure (18) for supplying current when the power supply voltage level decreases and consuming current when the power supply voltage increases; power consumption circuit (20), And a power consumption control circuit (62) for controlling a current consumed by at least a part of the power consumption circuit, the power consumption control circuit being coupled to the power consumption circuit. 7. The integrated circuit of item 6 of the patent application scope, wherein the power consumption control circuit includes: a power consumption reduction control circuit (64) for reducing a current consumed by at least a portion of the power consumption circuit; and an increase in power consumption A control circuit (82) for increasing the current consumed by at least a portion of the power consumption circuit; and a monitoring circuit (60) for comparing a power supply voltage with a predetermined voltage, the monitoring circuit being coupled to the power consumption to reduce The control circuit and the power consumption increase control circuit. 8. If the integrated circuit of item 7 of the patent application scope further includes: a power consumption circuit (80) coupled to receive at least one control signal from the power consumption increase control circuit, the power consumption circuit selectively consumes power. 9. If the integrated circuit of item 6 of the patent application scope further includes: a clock adjustment circuit coupled to receive at least one control signal from the power consumption increase control circuit 584955, the clock adjustment circuit is provided to the A clock signal of at least a portion of the power consumption circuit, wherein the clock adjustment circuit selectively interrupts the clock signal provided to at least a portion of the power consumption circuit. 10. An integrated circuit comprising: a power consumption circuit (20) for consuming power; a power consumption control circuit (62) for controlling a current consumed by at least a portion of the power consumption circuit, the power consumption control circuit Coupled to the power consumption circuit, wherein the power consumption control circuit includes a monitoring circuit (60) for comparing a power supply voltage with a predetermined voltage; a clock adjustment circuit (78) is coupled to the power consumption control circuit, at this time The pulse adjustment circuit adjusts a clock signal provided to at least a part of the power consumption control circuit. (本說明書格式、順序及粗體字，請勿任意更動，※記號邵分請勿填窝） ※申請案號：、斤/ ※申請θ期：炎\代㈣丨小丨L下斗 壹、發明名稱：（中文/英文） 於積體電路中控制電流需求之方法與裝置 METHOD AND APPARATUS FOR CONTROLLING CURRENT MAND IN AN INTEGRATED CIRCUIT C、申請人··（共1人） 姓名或名稱：（中文/英文） 美商摩托羅拉公司/MOTOROLA INC. 代表人：（中文/英文） 派翠西亞 S.高達/PATRICIAS. GODDARD 住居所或營業所地址：（中文/英文） 美國伊利諾州史勘伯市東阿崗崑路1303號摩托羅拉中心 CORPORATE OFFICES51303 EAST ALGONQUIN ROAD?SCHAUMBURG5ILLINOIS 60196?U.S.A. 國籍：（中文/英文） 美國/U.S.A. 參、發明人：（共5人） 姓名：（中文/英文） 1·大衛 T.布勞/DAVIDT.BLAAUW 2·瑞傑專 V.潘達/RAJENDRANV.PANDA 3. 拉傑修瑞/RAJATCHAUDHRY 4. 佛拉迪米爾P.索洛托/VLADIMIR P. ZOLOTOV 5. 拉文卓拉拉瑪瑞裘/RAVINDRARAJRAMARAJU 轉 中(Please do not change the format, order and boldface of this manual. ※ Please do not fill in the box with the mark.) ※ Application number :、 catty / ※ Application θ period: Yan \ 代 ㈣ 丨 小 丨 L 下 斗 一 、 Title of Invention: (Chinese / English) METHOD AND APPARATUS FOR CONTROLLING CURRENT MAND IN AN INTEGRATED CIRCUIT C, Applicant ... (1 person) Name or Name: (Chinese / English) ) Motorola Inc./MOTOROLA INC. Representative: (Chinese / English) Patricia S. Gundam / PATRICIAS. GODDARD Address of Residence or Business Office: (Chinese / English) East Algonquin, Scottsboro, Illinois, USA Motorola Center, No. 1303 Road Corporate OFFICES51303 EAST ALGONQUIN ROAD? SCHAUMBURG5ILLINOIS 60196? USA Nationality: (Chinese / English) US / USA Participants and inventors: (Total 5 persons) Name: (Chinese / English) 1 David T. Blau /DAVIDT.BLAAUW 2 · J. V. Panda / RAJENDRANV.PANDA 3. RAJATCHAUDHRY 4. Vladimir P. Soloto / VLADIMIR P. ZOLOTOV 5. Ravenzo Lalamariju / RAVINDRARAJRAMARAJU to 丨號專利申請案 書替換頁(93年1月） 邪^所4耗的電流的電能消耗控制 控制雷致鈿人 布」包路，其中該電能消耗 %路耦合至該電能消耗電路。 本發明的另一方面是關於一積體 泰处AA A %合具包含用以消耗 %此的電能消耗電路及耦合至該電能 自耗 該雷处、%把，肖耗電路，用以控制 兒此消耗電路至少一部份所消耗 雷致。彳、_ 和日^ %机的電能消耗控制 、及徂/Μ消耗控制電路包含監控電路，用以比較-電 源供應電壓與一預定電龎令籍 沪'、… 4 4積體電路也包含耦合至該電 月匕/肖耗fe制電路的時脈調整電路， 供至一 ％ m寺脈_整電路調整提 /、 ％此肩耗電路的一邵分之一時脈訊號。 圖1說明根據本發明的一具體實施例之系統1()。圖i是系 ㈣的-簡化及概約電路模型。在—具體實施例，系統1〇 電源供應龍系統。因此4統1G可包括其他或不同 ^圖1所不者的固有或寄生元件。系統1〇包括一電源供應 ，其輕合至板位階電路4，該電路4則搞合至一連結一積 體電路8的封裝6。板位㈣路4包_合至板絲合結構16 的板電能互連線u。封裝6包括封裝相互連接線14，且積體 2 = 8包括搞合至積體電路電容去耦合結構“的積體電路 電能互連線22 ’以及電能消耗電路2〇。積體電路去耦合結 構18及電能消耗電路2〇也搞合至電源供應12及板去搞合結 構 16。 σ 系統10說明從電源供應12流至電能消耗電路2〇的電流。 電源供應12則供給一恆定電壓。例如電源供應12可以是電 源調整器，電池或其他類似者。也請注意，電源供應。也 可被包括成為電路板，例如板位階電路4的部份，或可 O:\77\77830-930109.doc -8 - 赛專利申請案 ， ί文ϋ書替換頁(93年1月） 以是如圖1所示的外部電源供應（如在汽車應用中）。電流從 電源供應1 2流經板位階電路4。板位階電路4包括代表電路 板電能線路的固有和寄生電感的板電能相互連線11。而 且，板位階電路4可包括板去耦合結構16,其在一具體實施 例（圖1所示者）為一去耦合電容元件。此去耦合電容元件包 括固有電阻和電感，如圖1的板去耦合結構16所示。電流接 著從板位階電路4流經封裝6内的封裝接線。該等封裝接線 也包括一如封裝互連線電感14。電流接著在到達電能消耗 電路20内裝置前流經積體電路電能互連線22。積體電路電 能互連線22則經由系統10内一電阻和電感所形成。 在流經積體電路互連線22後，電流到達電能消耗電路 20，其在圖1内由一可變電阻（如可變負載）所表示。例如， 電能消耗電路20可包括操作電路，例如微處理器核心的邏 輯閘。然而，在替代具體實施例中，電能消耗電路20可包 括所有涉及積體電路8的操作及需要電流的電路。亦即’電 能消耗電路20—般執行某種功能而非僅提供及接收電流。 平行於電能消耗電路20的是積體電路電容去耦合結構 18。該等分離結構18可以多種不同方式形成。例如，在一 具體實施例中，這些結構可以是被動元件，例如電容，或 在替代具體實施例中，可以是主動裝置，例如組態成為電 容元件的MOS電晶體。在電源供應電壓位準降低時，積體 電路電容分離結構1 8提供電流至電能消耗電路20，且同樣 地，當電源供應電壓位準減少時消耗電流。因此積體電路 電容分離結構18的功能是響應來自電源供應12的電源供應 O:\77\77830-930l09.doc -9- 號專利申請案 第（Μ] 中文說明書替換頁(93年i月) 根内（如經由增加C或減少L所得到的9的減少轉換成實際減 少只有3)。本發明的具體實施例因此提供解答是集中在減 V dl/dt以減少供應電壓過多或過少的量。例如，為減少 dl/dt，dl可被減少或七可被增加，或兩者之結合，以協助控 制供應電壓過多或過低。因此，一種用以監視該供應電壓 及控制電能消耗電路20的電流需求可有效地減少dI/dt，並 將於下面更進一步討論。（而且請注意當時脈被調整以減少 需求電流時，本發明的具體實施例也可增加有效去耦合電 容（C)) 〇 圖2-4說明各種的電流⑴及電壓（Vdd)波形，其中〗指的是 電能消耗電路20所消耗的電流，Vdd則為電能消耗電路2〇 可看到的供給電壓。請注意電壓波形係在時間上對應電流 波形及說明當電能消耗電路2〇的電流消耗改變時，vdd對電 流的響應。圖2-4的波形說明說明導致供給電壓過多和過低 的電流改變的範例。 圖2說明對應於電能管理暫態的電流和電壓波形。例如， 圖2的波形對應於從一低電能狀態轉移至完全電能操作的 電能消耗電路20。（請注意雖然圖2未示，電能管理暫態在 完全電能操作的轉移回至低電能狀態時也可能發生。）因 此，在一電能管理暫態期間，電能消耗電路2〇在一低電能 狀態下操作，且該供給電壓（vdd)則位於一低電能標稱位 準。該電能管理狀態可指的是在一關閉狀態、一低電能狀 態（如在一靜止或暫停模式等）或其他類似者的電能消=電 路20田私把上升、重置或從睡眠狀態恢復等等時，電汸 O:\77\77830-930109.doc -11 - 第0911074^56號專利申請案 中文說明書替換頁(93年1月） 在一轉移時間會回升到影響Vdd電壓位準的完全電能操作 (至少部分是由於存在於低電能狀態及全電能狀態之間之 大的dl)。 例如，在一電能管理狀態期間，當電流位準位於低電能 狀態位準時，Vdd則在其低電能標稱Vdd位準。在轉換時間 的期間，當電流暫態從低電能狀態轉換至全電能操作（例如 當重置或電能上升時）時，Vdd低於低電能標稱Vdd位準之 下。在穩定於一全電能標稱Vdd位準之前（對應於全電能操 作），Vdd接著持續振盪（過低或過高）。相同地也發生在從 全電能操作到低電能狀態（未顯示）的轉移，其中Vdd首先超 過全電能標稱Vdd之上，接著在穩定於低電能標稱Vdd之前 持續振盪或減幅振盪。 供應電壓過高或過低都會破壞電能消耗電路20。例如， 過低會負向地影響到速度路徑因而導致效能損失。過低也 可使電能消耗電路20無法保持諸狀態，因而損壞到電能消 耗電路20。相同地，過高可能導致某些路徑執行太快，因 而破壞到電能消耗電路20所界定之保持時間，或可能引發 可靠度的問題，例如電晶體的薄氧化物的劣化。因此，任 何位準的過低和過多必須被控制以防止對電能消耗電路20 的損傷並確保電能消耗電路20的操作正常。 圖3說明對應於流入電能暫態的電流和電壓波形。例如， 當執行消耗電能低的資源的指令時，電能消耗電路20是位 於要求部份電能操作。然而，在指令流内，電能消耗電路 2 0可執行要求消耗較高電能的資源的指令。在該等高 O:\77\77830-930109 doc -12- 第O9U074%號專利申請案 中文說明書替換頁(93年1月） 電能指令期間，電能消耗電路20以高或全電能操作。在部 份電能操作和全電能操作間的電流轉移是小於圖2在低電 能狀態和全電能狀態之間（因此導致較低之dl);然而，該轉 移時間在低電能指令流和一高電能指令流間是比較快的， 也表示較小的dt。因此，因為Vdd是正比於電流對時間（dl/dt) 的改變率，在穩定於全電能標稱Vdd處或附近之前，短的轉 移時間對應於較小dt值，其同樣導致Vdd振盪（亦即減幅振 盪）於其部分電能標稱Vdd位準附近。再次，此減幅振盪動 作導入電壓供應過低和過高，其可能損壞電能消耗電路20。 圖4說明對應於週期性電能暫態的電流和電壓波形。例 如，電能消耗電路20可能重覆地執行一系列可能包括高電 能指令和低電能指令的指令。該等指令可能導致一重覆性 週期樣型，交替於以全電能操作的高電能指令及以低電能 操作的低電能指令之間，因此導致一如圖4所示的週期性電 流消耗波形。此週期樣型可能符合系統10的電源供應網路 的共振頻率，造成Vdd在每一週期内以一持續增加比率過高 或過低。這將導致如圖4所示的電能消耗電路20内之毀滅性 的電壓過高和過低。（請注意系統10的電源供應網路指的是 由電源供應12、板電能互連線11、板去耦合結構16、封裝 互連線14，積體電路電容性去耦合結構1 8以及積體電路互 連線22所形成的電氣網路。在替代性具體實施例，該電源 供應網路可包括比上述所列更多或更少的元件。） 在圖2 - 4所不的母個問題都可能造成電能消耗電路2 0的 破壞性影響，且需要說明每個狀況。此外，許多問題性暫 O:\77\77830-930109.doc -13- 第0911074为(號專利申請案 中文說明書替換頁(93年1月） 態會不可預期地發生在電能消耗電路2〇内，因此無法事先 防止。例如，圖3和4可能是一指令流内無預先通知而發生 的一特別序列指令所造成的。而且，因為各種不同指|流 可能造成這些問題，所以可以認知的是，吾人可以故意設 計該等指令流並藉此產生破壞性電腦病毒。此外，並不需 要特定指令以產生破壞性指令流，其意味著大量不同的$ 計選擇皆可用來產生會攻擊任何型式的電能消耗電路2 〇的 病毒。因此，微處理器、微控制器或其他積體電路等非負 責或控制該等電壓過低及過高者（可預測及不可預測者）會 受到該等危險的電腦病毒的影響。 例如，孩等病毒（亦即危險的碼段）可能被傳送到一個人電 腦（PC)處理器，其中它們可以反覆地嘗試且最後成功地造 成電流以PC處理器的共振波頻率來振盪，因而導致破壞性 過多或過低而摧毁PC處理器。此外，該等病毒也可能被寫 入以產生快或大的電能暫態，造成供應電壓的危險性過高 或過低而無法彌補地損壞PC處理器。因此單單一個人即可 以全球地散布一電腦病毒至任何直接至網際網路的電腦而 可此造成典法彌補地損壞。此外，在時脈速度變高時，該 等電壓供應的過高及過低所造成的問題的程度即會增加。 (例如，當時脈速度變高時，共振頻率大致會因為使用更多 去輕合裝置而減少。這使得一指令流内的電能轉換更容易 過多、過低以及共振頻率振盪。） 為說明圖2所導致的問題，電能消耗電路20的電能消耗可 、門歇丨生地被中辦以藉由增加以來減少以/以。電能消耗可 O:\77\77830-930109.doc -14- 第09110才\56號專利申請案 中文說明書替換頁(93年1月） 藉由仔止全區或任何局部時脈，停住電能消耗電路汕内的 處理器流，中斷發出新的指令，或減少部份電能消耗電路 20的電能來中斷。因此，可使用任何減少電能消耗的裝置 以中斷兒成消耗並控制電能消耗電路的冑流需求。 圖5說月⑼一低電能狀態至一包括中斷電能消耗的全 私把彳不作的|怨。忒等電流的改變造成vdd的改變。電流波 形30及電壓波形34對應於圖2的電能管理暫態。利用本發明 中斷電能消耗電路20的f能消耗的具體實施例，最終的電 流波形是波形32及對應電壓波形38。請注意，電壓波形％ 不再包括和電壓波形34相同量的過低及過高。亦即，電壓 波形38造成一保持在一預定容限範圍内的受控制的減幅振 盪，如同電能消耗電路2〇所容許的。 圖5也說明Vdd的一較高減少閥限及一較低減少閥限。因 此，如圖5所tjt，當電壓波形38從低電源標稱vdd降至較低 的減少閥限（在點36處）時，每當Vdd低於較低減少閥限（以 響應增加的I)，電能消耗被中斷（藉此減少電流需求）。電能 如示波形32的平坦部分（部分31)所示保持中斷直至電壓波 形增加並觸及較高減少閥限（在點37處）。當到達較高閥限 時，標稱電能消耗再繼續並從電能消耗中斷前掉落的相同 €把位準轉移至全電此操作，如波形3 2的上升部分所示（緊 接部分3 1之後）。Vdd再次減少直至到達較低減少閥限（在點 39)，在此處電能消耗將再度中斷（部分33)。最後，Vdd將 不再減少並超過閥限值，且該電壓波形將最後穩定在一全 電能標稱Vdd位準附近。因此，電能消耗中斷偏移每一 O:\77\77830-930109.doc -15- 第091107456號專利申請案 中文說明書替換頁(93年1月） 中斷期間的暫態且整個dt43現在大於dt41而無中斷，因此造 成一 dl/dt減少及一受控制的電壓供應過低。 圖6說明電能消耗電路20從全電能操作轉移降至低電能 狀態。請注意波形單純為圖5的波形的反轉。電流波形69及 電壓波形65對應於上述討論的電能管理暫態問題（請注意 該等波形69和65為圖2的電流和電壓波形反轉）。利用本發 明間歇地增加電能消耗電路20電能消耗的具體實施例，最 終的電流波形是波形79且對應的電壓波形67。因此，為減 少dl/dt，電能消耗可能間歇地增加，下文將更進一步討論。 電能消耗電路20的電能消耗（例如電流需求）可以經由開啟 (如增加電能）電能消耗電路20的閒置區塊，發出高電能指 令，開啟電能消耗負載或相似者而增加。因此，di/d〖經由 增加dt而增加，增加wdI/dt有助於控制電壓減幅振盪。 圖6也說明Vdd的一較高增加閥限及一較低增加閥限。因 $ ,如圖6所示，當電壓波形67從高電能標稱vdd上升至較 高增加閥限（在點57)時，每當Vdd上升到較高增加間限（以 響應I減少），電能消耗被增加（藉此增加電流需求）。電能如 波形79的上升部分（部分51)所示地保持增加直至電壓波形 67減少並觸及較低增加閥限（在點59)。當到達較低的增加闕 限時’ %電能消耗再繼續且從如波形79(緊接著部分⑴ 的減少部分所示’從如果電能消耗已持續而無間歇性斷續 增加，電能消耗會到達的點轉移至低電能狀態。㈣再次增 :直較高的增加閥限（點61)為止，在此點電能消耗則 再/人增加（邵分53)。最後，州將不再增加並超過較 O:\77\77830-930l09.doc -16- 號專利申請案 中文說明書替換頁(93年1月） 路20的標稱電能消耗再繼續。當電流持續轉換至全電能操 作時，Vdd持續正常響應電能消耗電路20所消耗的電流直至 較高的增加閥限或較低的減少閥限之一達到為止。 在圖7所示的具體實施例中，導致電流需求改變的Vdd所 觸及下一閥限是較高增加閥限（在點75)，在此點電能消耗增 加（部分50)。當Vdd觸及較低增加閥限（在點77)時，該電能 的增加被中斷，在該較低增加閥限，標稱Vdd響應再繼續。 請注意在該等電能消耗被中斷部分期間（如部分48和52)，該 最終的波形42則被相等於中斷期間的量所偏移，因此持續 地對波形42進行相位偏移。電能消耗增加（如部分50和54) 的期間不可能導致該波形的進一步相位偏移；然而，它們 以有助於控制如波形46所示的電壓減幅振盪效應。因此， 電能中斷部分48和52及電能增加部分50和54的結合有助於 確保電流波形在延伸的週期時間不會匹配共振頻率及藉由 確保位準保持在可接受的範圍内而有助於控制Vdd的減幅 振盪效應。請注意，雖然圖7僅說明在每一部分電能/全電 能暫態期間的一中斷或增加，該等電壓閥限可以被設計以 產生任何數量的電能消耗的中斷或增加。 圖8說明電能消耗電路20的一部分之方塊圖，包括具監視 電路60、電能消耗減少控制電路64及電能消耗增加控制電 路66的電能消耗電路62。電能消耗控制電路62接收較高減 少閥限、較低減少閥限、較高增加閥限及較低增加閥限以 依所需地中斷或增加電能消耗（如參考圖5-7所述）。因此， 監視電路60内比較器68、70、72和74，每個皆接收Vdd O:\77\77830-930109doc -18- 584955 補^* Ιό號專利申請案 —中叉說明書替換頁(93年1月） 路，例如電能消耗電路20逐量地減少電能消耗。因此，更 多智慧型控制電路可使用以獲致更多控制。替代地，圖㈣ 電流控制可藉由結合部份閥限電壓位準及使用一單值來簡 化。例如，不使用一單獨的較高減少閥限及較低減少閥限， 他們可被結合成一單一減少閥限值。相似地，較高增加閥 限及較低增加閥限也可結合為一單一增加的間限值。因 此，圖8的方塊圖為一具體實施例的—簡單說明，但可以更 間化或更複雜，端视控制期《量而<。而丨，在替代具體 實施例中，所有使用在電能消耗電路2〇的間限值可以為= 用者所可程式化而非固定。這樣容許使用者有-更大程产 的彈性。 & 在先前說明中，本發明已參考特定具體實施例予以說 明。無論如何，習知本技藝者瞭解到，在不恃離如申請專 利範圍所述之本發明的範脅下可以進行不同改良和變化。 例如、:雖然本發明的具體實施例已大致參考微處理器而說 ，月〜月匕消耗控制電路可使用以控制任何積體電路的電 “求-且不限制於微處理器。而且雖然電能控制電路a如 圖8所不為直接檢測電源供應電壓，可使用其他例如藉由咸 測電源供應電流、電能、訊號延遲及訊號頻率之至少一: t決定電源供應電壓⑽)的裝置。因此，該等說明和圖或 的範圍内。而非限制’且所有該等改良皆可包含在本發明 C本發明已針對特定傳電位 習知技藝者知道這些傳導型式和電位極性可被迷’ O:\77\77830-930I09.doc -21 - 584^5*5： 年 拾、申請專利範固： L 一種用以控制一具有電能消耗 求乏女氺二、、丄^ 包路<積體電路内電流需 K万法，孩万法包含下列步驟： 檢測是否一預定過高及一 如所箱细/十 ，、疋過低的至少一個出現或 所了員々月在一電源供應電壓中· 1 ? 如果該預定過高及預定過低之— 被檢測到，控制由該電能消耗：：：電源供應電壓中 該電源供給電壓將保持在—預定：所消耗之電流以確保 預定範圍内。 ^電源供應電壓位準白卜 2. 如申請專利範圍第丨項之方法， 驟： ，、中孩檢測步騾包含一步 比較該電源供應電壓與一參考雨 含下列步驟： 考^’其中該比較步驟包 比較該電源供應電壓與一第一參考電壓，·及 如果該電源供應電壓低於該第—三 預定過低已發生； 參考電壓，則檢測出該 比較該電源供應電壓與—第二參考電壓；及 如果該電源供應電壓高於該第二參^厭^, 預定過高已發生。 土，刈檢測出該 3 ·如申請專利範圍第1项之方法，貧 蚀w… 法其中Μ控制步驟並不需要 使用去李馬合電客。 1而責 4.如申請專利範圍第0之方法，其中該控制步 選擇地相位移該電能消輕電路内電流。 匕含. 5 ·如申请專利範圍弟1项之方、、夫，觉士七4、；〇· 万法其中⑽制步驟另包含：Replacement page of Patent Application No. 丨 (January 1993) Electricity consumption control of the current consumed by the control circuit is controlled. The electric energy consumption circuit is coupled to the electric energy consumption circuit. Another aspect of the present invention relates to an integrated circuit AA A% assembly comprising a power consumption circuit for consuming %% and a power consumption circuit coupled to the power self-consumption mine,%, and a consumption circuit for controlling This consumes at least a portion of the consumption circuit. The power consumption control of 彳, _, and ^% units, and the 徂 / Μ consumption control circuit include a monitoring circuit to compare the power supply voltage with a predetermined power supply voltage, and the integrated circuit also includes coupling. To the clock adjustment circuit of the electric moon / xiao consumption circuit, it is supplied to a% m pulse_adjustment circuit, which is a half of the clock signal of this shoulder circuit. FIG. 1 illustrates a system 1 () according to a specific embodiment of the present invention. Figure i is a simplified-simplified and approximated circuit model. In a specific embodiment, the system 10 power supply system. Therefore, the 4G 1G may include other or different ^ inherent or parasitic elements not shown in FIG. 1. The system 10 includes a power supply which is light-coupled to the board level circuit 4 which is coupled to a package 6 connected to an integrated circuit 8. The board position circuit 4 packs_ the board electrical interconnection line u connected to the board wire structure 16. Package 6 includes package interconnection lines 14 and integrated product 2 = 8 includes integrated circuit electrical energy interconnection line 22 'coupled to integrated circuit capacitive decoupling structure "and integrated circuit power consumption circuit 20. Integrated circuit decoupling structure 18 and the power consumption circuit 20 are also connected to the power supply 12 and the board to connect the structure 16. The σ system 10 describes the current flowing from the power supply 12 to the power consumption circuit 20. The power supply 12 supplies a constant voltage. For example The power supply 12 can be a power conditioner, a battery or the like. Please also note that the power supply. It can also be included as part of a circuit board, such as board level circuit 4, or can be O: \ 77 \ 77830-930109. doc -8-Sai patent application, replacement page of the textbook (January 1993) So the external power supply as shown in Figure 1 (such as in automotive applications). Current flows from the power supply 1 2 through the board level Circuit 4. The board level circuit 4 includes board power interconnections 11 that represent the inherent and parasitic inductance of the power circuit of the circuit board. Moreover, the board level circuit 4 may include a board decoupling structure 16, which in a specific embodiment (as shown in Figure 1) (Shower) for one Decoupling capacitor element. This decoupling capacitor element includes inherent resistance and inductance, as shown in the board decoupling structure 16 of Figure 1. Current then flows from the board level circuit 4 through the package wiring in the package 6. The package wiring also includes Just like the package interconnection line inductor 14. The current then flows through the integrated circuit power interconnection line 22 before reaching the device in the power consumption circuit 20. The integrated circuit power interconnection line 22 is formed by a resistor and an inductor in the system 10 After flowing through the integrated circuit interconnect 22, the current reaches the power consumption circuit 20, which is represented by a variable resistor (such as a variable load) in FIG. 1. For example, the power consumption circuit 20 may include an operation circuit, For example, a logic gate of a microprocessor core. However, in alternative embodiments, the power consumption circuit 20 may include all the circuits related to the operation of the integrated circuit 8 and circuits that require a current. That is, the 'power consumption circuit 20 typically performs some kind of Function rather than just supplying and receiving current. Parallel to the power consumption circuit 20 is the integrated circuit capacitor decoupling structure 18. The separation structures 18 can be formed in a number of different ways. In a specific embodiment, these structures may be passive elements, such as capacitors, or in alternative embodiments, may be active devices, such as MOS transistors configured as capacitive elements. When the power supply voltage level decreases The integrated circuit capacitor separation structure 18 provides current to the power consumption circuit 20, and similarly, consumes current when the power supply voltage level decreases. Therefore, the function of the integrated circuit capacitor separation structure 18 is to respond to the power from the power supply 12 Supply O: \ 77 \ 77830-930l09.doc -9- Patent Application No. (M) Chinese Specification Replacement Page (January 1993) Root within (such as the reduction of 9 obtained by increasing C or decreasing L into The actual reduction is only 3). The specific embodiment of the present invention therefore provides a solution focused on reducing V dl / dt to reduce the amount of supply voltage that is too much or too little. For example, to reduce dl / dt, dl can be reduced or seven can be increased, or a combination of the two to help control excessive or low supply voltage. Therefore, a current demand for monitoring the supply voltage and controlling the power consumption circuit 20 can effectively reduce dI / dt, and will be discussed further below. (Please also note that when the clock is adjusted to reduce the required current, the specific embodiment of the present invention can also increase the effective decoupling capacitance (C)). Figure 2-4 illustrates various current and voltage (Vdd) waveforms, where: Refers to the current consumed by the power consumption circuit 20, and Vdd is the supply voltage that the power consumption circuit 20 can see. Please note that the voltage waveform corresponds to the current waveform in time and explains the response of vdd to the current when the current consumption of the power consumption circuit 20 changes. The waveforms in Figure 2-4 illustrate examples of current changes that result in excessive and low supply voltages. Figure 2 illustrates current and voltage waveforms corresponding to power management transients. For example, the waveform of FIG. 2 corresponds to a power consumption circuit 20 that transitions from a low power state to full power operation. (Please note that although not shown in Figure 2, the power management transient may also occur when the full power operation is transferred back to the low power state.) Therefore, during a power management transient, the power consumption circuit 20 is in a low power state. And the supply voltage (vdd) is at a low power nominal level. The power management state may refer to a power-off state in a closed state, a low-power state (such as in a stationary or pause mode, or the like), or the like. The circuit rises, resets, or resumes from a sleep state. At the same time, the electric card O: \ 77 \ 77830-930109.doc -11-Replacement page of the Chinese specification of Patent Application No. 0911074 ^ 56 (January 1993) will rise to a complete level that affects the Vdd voltage level within a transfer time. Power operation (at least in part due to the large dl that exists between the low power state and the full power state). For example, during a power management state, when the current level is at a low power state level, Vdd is at its low power nominal Vdd level. During the transition time, when the current transient transitions from a low power state to full power operation (such as when resetting or power up), Vdd is below the low power nominal Vdd level. Vdd continues to oscillate (too low or too high) before stabilizing at a full power nominal Vdd level (corresponding to full power operation). The same happens at the transition from full power operation to a low power state (not shown), where Vdd first exceeds the full power nominal Vdd, and then continues to oscillate or oscillate before stabilizing at the low power nominal Vdd. If the supply voltage is too high or too low, the power consumption circuit 20 will be destroyed. For example, too low will negatively affect the speed path and cause a loss of performance. If it is too low, the power consumption circuit 20 cannot be maintained, and the power consumption circuit 20 is damaged. Similarly, too high may cause some paths to execute too fast, thereby destroying the hold time defined by the power consumption circuit 20, or may cause reliability issues, such as the degradation of the thin oxide of the transistor. Therefore, any level that is too low and too high must be controlled to prevent damage to the power consumption circuit 20 and ensure that the operation of the power consumption circuit 20 is normal. Figure 3 illustrates the current and voltage waveforms corresponding to the transients of the incoming electrical energy. For example, when an instruction that consumes low-power resources is executed, the power-consuming circuit 20 is positioned to require a portion of the power to operate. However, within the instruction stream, the power consumption circuit 20 can execute instructions that require resources that consume higher power. During the high-level O: \ 77 \ 77830-930109 doc -12- O9U074% patent application Chinese manual replacement page (January 1993), the power consumption circuit 20 operates with high or full power. The current transfer between partial power operation and full power operation is less than that shown in Figure 2 between the low power state and the full power state (hence a lower dl); however, the transfer time is between a low power instruction flow and a high power The instruction flow is relatively fast and also indicates a smaller dt. Therefore, because Vdd is proportional to the rate of change of current to time (dl / dt), before settling at or near full power nominal Vdd, a short transfer time corresponds to a smaller dt value, which also causes Vdd to oscillate (also That is, the amplitude-decreasing oscillation) is near the nominal Vdd level of part of the electrical energy. Again, this amplitude-reducing operation introduces too low and too high a voltage supply, which may damage the power consumption circuit 20. Figure 4 illustrates current and voltage waveforms corresponding to a periodic electrical energy transient. For example, the power consumption circuit 20 may repeatedly execute a series of instructions that may include a high power instruction and a low power instruction. These instructions may result in a repeating cycle pattern that alternates between high power instructions operating at full power and low power instructions operating at low power, thus resulting in a periodic current consumption waveform as shown in FIG. 4. This period pattern may correspond to the resonance frequency of the power supply network of the system 10, causing Vdd to be too high or too low at a continuous increase rate in each cycle. This will cause the devastating voltage in the power consumption circuit 20 shown in Fig. 4 to be too high and too low. (Please note that the power supply network of the system 10 refers to the power supply 12, the board power interconnection 11, the board decoupling structure 16, the package interconnection 14, the integrated circuit capacitive decoupling structure 18, and the integrated circuit. Electrical network formed by circuit interconnects 22. In alternative embodiments, the power supply network may include more or fewer components than those listed above.) The issues not shown in Figures 2-4 Both may cause destructive effects of the power consumption circuit 20, and each situation needs to be explained. In addition, many problematic temporary O: \ 77 \ 77830-930109.doc -13- No. 0911074 is (No. Patent Application Chinese Specification Replacement Page (January 1993). State will unexpectedly occur within the power consumption circuit 20 Therefore, it cannot be prevented in advance. For example, Figs. 3 and 4 may be caused by a special sequence of instructions that occur without prior notice in an instruction stream. Moreover, because various different reference streams may cause these problems, it is recognized that I can deliberately design such instruction streams and thereby generate destructive computer viruses. In addition, no specific instructions are required to generate destructive instruction streams, which means that a large number of different dollar plans can be used to generate any type of attack that will attack any type of Power consumption circuit 2 virus. Therefore, microprocessors, microcontrollers or other integrated circuits that are not responsible or control those voltages that are too low and too high (predictable and unpredictable) will be exposed to such dangers. The effects of computer viruses. For example, child viruses (that is, dangerous code segments) may be transmitted to a personal computer (PC) processor, where they can repeatedly try and After that, it successfully caused the current to oscillate at the resonance frequency of the PC processor, which caused too much damage or too low to destroy the PC processor. In addition, these viruses may also be written to generate fast or large electrical transients, The danger of causing the supply voltage to be too high or too low to irreparably damage the PC processor. Therefore, a single individual can globally spread a computer virus to any computer directly connected to the Internet and this can cause irreparable damage to the code. In addition, as the clock speed becomes higher, the problem caused by the excessively high and low voltage supply will increase. (For example, when the clock speed becomes higher, the resonance frequency will be roughly lightened by using more. It reduces the number of devices. This makes it easier to convert too much, too low, and resonant frequency oscillations in a command stream.) In order to illustrate the problem caused by Figure 2, the power consumption of the power consumption circuit 20 can be stopped. Do this by increasing / decreasing since the increase. Power consumption can be O: \ 77 \ 77830-930109.doc -14- 09110 Cai \ 56 Patent Application Chinese Specification Replacement Page (January 1993) By stopping the whole area or any local clock, stopping the processor flow in the power consumption circuit, interrupting the issuing of new instructions, or reducing the power of some of the power consumption circuit 20 to interrupt. Therefore, any reduced power can be used The consumption device interrupts the consumption of electricity and controls the flow demand of the power consumption circuit. Figure 5 shows the monthly power state from a low power state to a completely private operation that includes interruption of power consumption. Causes a change in vdd. The current waveform 30 and the voltage waveform 34 correspond to the power management transient of FIG. 2. Using the embodiment of the present invention to interrupt the f energy consumption of the power consumption circuit 20, the final current waveform is the waveform 32 and the corresponding Voltage waveform 38. Please note that voltage waveform% no longer includes too low and too high the same amount as voltage waveform 34. That is, the voltage waveform 38 causes a controlled amplitude oscillation to be maintained within a predetermined tolerance range, as allowed by the power consumption circuit 20. Figure 5 also illustrates a higher reduction threshold and a lower reduction threshold for Vdd. Therefore, as shown by tjt in Fig. 5, when the voltage waveform 38 drops from the low power nominal vdd to the lower reduction threshold (at point 36), whenever Vdd is below the lower reduction threshold (in response to an increasing I ), Power consumption is interrupted (thus reducing current demand). The electrical energy remains interrupted as shown by the flat portion (section 31) of waveform 32 until the voltage waveform increases and touches the higher reduction threshold (at point 37). When the higher threshold is reached, the nominal power consumption continues and shifts from the same level that fell before the power consumption was interrupted to full power. This operation is shown in the rising part of waveform 3 2 (immediately after part 3 1) ). Vdd decreases again until the lower reduction threshold is reached (at point 39), where power consumption will be interrupted again (section 33). In the end, Vdd will no longer decrease and exceed the threshold, and the voltage waveform will eventually stabilize near the full power nominal Vdd level. Therefore, the power consumption interruption shifts every O: \ 77 \ 77830-930109.doc -15- No. 091107456 Patent Application Chinese Specification Replacement Page (January 1993) The transient state during the interruption and the entire dt43 is now greater than dt41 and No interruption, resulting in a dl / dt reduction and a controlled voltage supply that is too low. Figure 6 illustrates the transition of the power consumption circuit 20 from full power operation to a low power state. Please note that the waveform is simply the inversion of the waveform in Figure 5. The current waveform 69 and voltage waveform 65 correspond to the power management transient problems discussed above (please note that these waveforms 69 and 65 are the current and voltage waveform inversions of Figure 2). With the specific embodiment of the present invention that intermittently increases the power consumption of the power consumption circuit 20, the final current waveform is a waveform 79 and a corresponding voltage waveform 67. Therefore, in order to reduce dl / dt, power consumption may increase intermittently, as discussed further below. The power consumption (eg, current demand) of the power consumption circuit 20 can be increased by turning on (eg, increasing power) the idle block of the power consumption circuit 20, issuing a high power command, turning on the power consumption load or the like. Therefore, di / d is increased by increasing dt. Increasing wdI / dt helps control the voltage swing oscillation. Figure 6 also illustrates a higher increase threshold and a lower increase threshold for Vdd. Because $, as shown in FIG. 6, when the voltage waveform 67 rises from the high power nominal vdd to a higher increase threshold (at point 57), whenever Vdd rises to a higher increase interval (in response to a decrease in I), Electricity consumption is increased (thus increasing current demand). The electrical energy continues to increase as shown by the rising portion (section 51) of waveform 79 until the voltage waveform 67 decreases and hits the lower increase threshold (at point 59). When the lower increase threshold is reached, the% power consumption continues and from the point shown in waveform 79 (next to the decrease in section ') from the point where the power consumption will reach if the power consumption has been continued without intermittent increases. Transfer to a low power state. 增 Increase again: until the threshold is increased higher (point 61), at this point the power consumption will increase again per person (Shao 53). Finally, the state will no longer increase and exceed the : \ 77 \ 77830-930l09.doc -16- Patent Application Chinese Manual Replacement Page (January 1993) The nominal power consumption of Road 20 continues. When the current continues to switch to full power operation, Vdd continues to respond normally The current consumed by the power consumption circuit 20 is until one of the higher increase threshold or the lower decrease threshold is reached. In the specific embodiment shown in FIG. 7, the next threshold is reached by Vdd, which causes the current demand to change. Is the higher increase threshold (at point 75), at which point power consumption increases (part 50). When Vdd hits the lower increase threshold (at point 77), the increase in electrical energy is interrupted and at this lower increase Threshold, nominal Vdd response before continuing. Please Note that during periods when such power consumption is interrupted (such as sections 48 and 52), the final waveform 42 is shifted by an amount equal to the interrupt period, so the phase offset of waveform 42 is continuously shifted. Power consumption increases ( Periods such as sections 50 and 54) are unlikely to cause further phase shifts of this waveform; however, they help to control the voltage-decreasing oscillation effect shown in waveform 46. Therefore, the power interruption sections 48 and 52 and the power increase The combination of sections 50 and 54 helps to ensure that the current waveform does not match the resonance frequency during the extended cycle time and helps to control the amplitude-reducing oscillation effect of Vdd by ensuring that the level remains within an acceptable range. Please note, Although FIG. 7 illustrates only one interruption or increase during each partial power / full power transient, the voltage thresholds can be designed to generate any number of interrupts or increases in power consumption. FIG. 8 illustrates a portion of the power consumption circuit 20 The block diagram includes a power consumption circuit 62 with a monitoring circuit 60, a power consumption reduction control circuit 64, and a power consumption increase control circuit 66. Power consumption control Route 62 receives a higher decrease threshold, a lower decrease threshold, a higher increase threshold, and a lower increase threshold to interrupt or increase power consumption as needed (as described with reference to Figures 5-7). Therefore, monitoring Comparators 68, 70, 72, and 74 in circuit 60 each receive Vdd O: \ 77 \ 77830-930109doc -18- 584955 Supplement ^ * Patent Application No. Ιό—Replacement page of the instruction manual (January 1993) Circuit, such as the power consumption circuit 20, to reduce the amount of power consumption. Therefore, more intelligent control circuits can be used to achieve more control. Alternatively, Figure ㈣ current control can be combined with some threshold voltage levels and use A single value to simplify. For example, instead of using a single higher reduction threshold and a lower reduction threshold, they can be combined into a single reduction threshold. Similarly, a higher increase threshold and a lower increase threshold can be combined into a single increased interval value. Therefore, the block diagram of Fig. 8 is for a specific embodiment-simple explanation, but it can be more or more complicated, depending on the control period "volume and < However, in an alternative embodiment, all the inter-limit values used in the power consumption circuit 20 may be programmable by the user instead of being fixed. This allows users to have greater flexibility in production. & In the foregoing description, the invention has been described with reference to specific embodiments. In any case, those skilled in the art understand that various improvements and changes can be made without departing from the scope of the invention as described in the scope of the patent application. For example, although the specific embodiment of the present invention has been roughly referred to the microprocessor, the month-to-month consumption control circuit can be used to control the power of any integrated circuit-and is not limited to the microprocessor. The control circuit a is not directly detecting the power supply voltage as shown in FIG. 8, and other devices such as measuring the power supply current, power, signal delay, and signal frequency by measuring at least one of the power supply voltage (t) determine the power supply voltage ⑽). Therefore, These descriptions and diagrams are within the scope of the description. It is not a limitation 'and all such improvements can be included in the present invention. The present invention has been known to a particular potential-conducting artisan who knows that these conduction patterns and potential polarities can be confused. O: \ 77 \ 77830-930I09.doc -21-584 ^ 5 * 5: Annual pick-up, patent application Fangu: L One to control a woman with electric power consumption, two, 丄 ^ package circuit < integrated circuit The internal current needs K million methods, and the tens of thousands of methods include the following steps: Detect if one is pre-determined too high and as thin as the box / ten, at least one of the too low appears or all the members are in a power supply voltage. 1? As The predetermined over- and under-determined—detected, controlled by the power consumption ::: the power supply voltage will remain at—predetermined: the consumed current to ensure a predetermined range. ^ Power supply voltage Level bu 2. If the method of the scope of application for the patent application item 丨, step: ,, the detection step of the child includes a step to compare the power supply voltage with a reference rain and includes the following steps: Exam ^ 'Where the comparison step includes comparing the A power supply voltage and a first reference voltage, and if the power supply voltage is lower than the third predetermined low has occurred; a reference voltage, it is detected that the power supply voltage is compared with a second reference voltage; and if The power supply voltage is higher than the second parameter, and a pre-determined high level has occurred. Soil, 刈 detected the 3 · As in the method of applying for the scope of the first patent application, the method of lean erosion w ... The M control step is not required Use Limahe Electric Passengers. 1. Obligation 4. As the method of patent application scope 0, wherein the control step selectively phase-shifts the electric energy to lighten the current in the circuit. Dagger contains. 5 · If you apply for a patent in the scope of the first item, husband, husband, 7: 4 ;; · Wanfa which includes the steps of control:
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7035785B2 (en) * 2001-12-28 2006-04-25 Intel Corporation Mechanism for estimating and controlling di/dt-induced power supply voltage variations
FI115256B (en) * 2002-11-08 2005-03-31 Nokia Corp Configure Closed System Activity Information
US7137081B2 (en) * 2003-12-17 2006-11-14 International Business Machines Corporation Method and apparatus for performing density-biased buffer insertion in an integrated circuit design
US7483248B1 (en) * 2005-05-19 2009-01-27 Sun Microsystems, Inc. Method and apparatus for detecting current changes in integrated circuits
US7607028B2 (en) * 2006-05-30 2009-10-20 International Business Machines Corporation Mitigate power supply noise response by throttling execution units based upon voltage sensing
US7467050B2 (en) * 2006-05-30 2008-12-16 International Business Machines Corporation Method for detecting noise events in systems with time variable operating points
US7532003B1 (en) * 2006-06-12 2009-05-12 Sun Microsystems, Inc. Method and apparatus for setting VDD on a per chip basis
US7502719B2 (en) * 2007-01-25 2009-03-10 Monolithic Power Systems, Inc. Method and apparatus for overshoot and undershoot errors correction in analog low dropout regulators
US7720621B2 (en) * 2007-08-30 2010-05-18 International Business Machines Corporation Application of multiple voltage droop detection
US7599808B2 (en) * 2007-08-31 2009-10-06 International Business Machines Corporation Application of multiple voltage droop detection and instruction throttling instances with customized thresholds across a semiconductor chip
US7818599B2 (en) * 2007-10-09 2010-10-19 International Business Machines Corporation Statistical switched capacitor droop sensor for application in power distribution noise mitigation
US8145923B2 (en) * 2008-02-20 2012-03-27 Xilinx, Inc. Circuit for and method of minimizing power consumption in an integrated circuit device
KR101249886B1 (en) * 2010-01-11 2013-04-03 서울시립대학교 산학협력단 Frequency compensator, method for compensating frequency of dc-dc converter using the same and dc-dc converter having the same
US9497850B2 (en) 2010-11-04 2016-11-15 Koninklijke Philips N.V. Controlled power dissipation in a lighting system
US9084316B2 (en) 2010-11-04 2015-07-14 Cirrus Logic, Inc. Controlled power dissipation in a switch path in a lighting system
US8539262B2 (en) * 2010-12-09 2013-09-17 Intel Corporation Apparatus, method, and system for improved power delivery performance with a dynamic voltage pulse scheme
US9520794B2 (en) 2012-07-25 2016-12-13 Philips Lighting Holding B.V Acceleration of output energy provision for a load during start-up of a switching power converter
US20150244189A1 (en) * 2012-10-24 2015-08-27 Sharp Kabushiki Kaisha Balancer circuit and battery unit using same
US9454196B2 (en) * 2013-06-27 2016-09-27 Apple Inc. Active peak power management of a high performance embedded microprocessor cluster
JP2019114011A (en) 2017-12-22 2019-07-11 ルネサスエレクトロニクス株式会社 Semiconductor device and control method of semiconductor device
US11444210B2 (en) 2018-06-21 2022-09-13 Drexel University On-chip power supply noise suppression through hyperabrupt junction varactors
CN108983074A (en) * 2018-08-09 2018-12-11 珠海格力智能装备有限公司 Circuit board detection method and device
CN108983005A (en) * 2018-08-09 2018-12-11 珠海格力智能装备有限公司 Detection method and device for manual operator
CN114815952B (en) * 2021-01-18 2024-03-01 瑞昱半导体股份有限公司 Integrated circuit applicable to system protection by dynamic voltage change

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0724209A1 (en) 1995-01-25 1996-07-31 International Business Machines Corporation Power management system for integrated circuits
US5838145A (en) 1996-05-30 1998-11-17 Poon; Franki Ngai Kit Transient load corrector for switching converters
US6069521A (en) 1997-06-27 2000-05-30 Sun Microsystems Voltage regulation method for attenuating inductance-induced on-chip supply variations
US6028417A (en) 1997-06-27 2000-02-22 Sun Microsystems, Inc. Voltage regulator circuit for attenuating inductance-induced on-chip supply variations
US5963023A (en) * 1998-03-21 1999-10-05 Advanced Micro Devices, Inc. Power surge management for high performance integrated circuit
JP2001101364A (en) 1999-10-01 2001-04-13 Fujitsu Ltd Lsi for non-contact ic card

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