TW584913B - Method of etching silicon substrate surface to increase light emission efficiency of device - Google Patents

Method of etching silicon substrate surface to increase light emission efficiency of device Download PDF

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TW584913B
TW584913B TW92103861A TW92103861A TW584913B TW 584913 B TW584913 B TW 584913B TW 92103861 A TW92103861 A TW 92103861A TW 92103861 A TW92103861 A TW 92103861A TW 584913 B TW584913 B TW 584913B
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silicon substrate
etching
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TW200416868A (en
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Ching-Fu Lin
Yi-Jr Liang
Wu-Ping Huang
Shin-Hung Shie
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Univ Nat Taiwan
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Abstract

A kind of method of etching silicon substrate surface to increase the light emission efficiency of device is disclosed in the present invention. Before forming nanometer particle layer and the conduction layer, chemical etching is first used to remove the surface energy state or surface defect of silicon substrate, so as to reduce the non-radiative electron-hole recombination centers of the silicon substrate surface, and to increase the ratio of radiative electron-hole recombination of metal oxide silicon (MOS) emitting device such that the light emitting efficiency is greatly increased when the MOS structure generates light. In addition, the etching step also can cause nanometer scale surface structure and increase the collision probability between electron-hole pairs and phonons, so as to relatively increase the light emitting efficiency.

Description

584913 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關一種金氧矽發光二極體(Metal-Oxide -Silicon Light Emitting Diode,M0SLED)技術,特別 是關於一種利用姓刻石夕基板表面提高金氧石夕元件電激發光 效率之方法。 【先前技術】 按,金氧矽結構(M0S)係在1 9 5 9年由ΜοΠ、Pf ann以 及Garrett所提出,最先是用來做為電壓控制的電容器, 1 9 7 0年B 〇 y 1 e和S m i t h提出了電荷耦合的觀念,而做出了電 荷耦合元件(Charge-Coupled Device,CCJ)),目前是 C C D相機和數位相機的關鍵元件。到了 1 9 8 0年代,Μ 0 S更成 為積體電路(I C)中極重要的結構,由ν型和Ρ型M 0S場效 電晶體(M0SFET)合成之互補式金氧半導體( complementary raetal-oxide-semiconductor,CMOS)係 成為超大型積體電路(VLSI)或極大型積體電路(uLSI) 中最重要的元件,甚至在太陽能電池中,M〇s也是極受重 視的結構。 雖然Μ 0 S結構在電子領域中扮演了非常重要的角色, 但是由於矽(Silicon)半導體是一種間接能隙( indirect bandgap),電子電洞直接復合產生光時還需聲 子(Phonon)參與,才能滿足動量守恒的要求,一般狀況 下,電子、電洞和聲子三個粒子同時碰撞在一起的機率很 小,所以電子電洞直接復合產生光的機率很小,使得M〇s 可能發光的情形不被看好。584913 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a metal-Oxide-Silicon Light Emitting Diode (MOSSLED) technology, and particularly to a method using a family name carved stone eve A method for improving the electro-optical efficiency of a metal oxide element on the surface of a substrate. [Previous technology] According to the metal oxide structure (M0S) was proposed by MοΠ, Pfann and Garrett in 1959, it was first used as a voltage control capacitor, 1970 B 0 1 e and Smith put forward the concept of charge coupling, and made charge-coupled device (Charge-Coupled Device, CCJ)), which is currently the key component of CCD cameras and digital cameras. In the 1980s, M 0 S has become a very important structure in integrated circuits (ICs). Complementary metal oxide semiconductors (composite raetal- The oxide-semiconductor (CMOS) system has become the most important element in very large-scale integrated circuits (VLSI) or very large-scale integrated circuits (uLSI). Even in solar cells, Mos is a highly regarded structure. Although the M 0 S structure plays a very important role in the field of electronics, since silicon semiconductors are an indirect bandgap, the electron holes directly require the participation of phonons to generate light. In order to meet the requirements of conservation of momentum, under normal circumstances, the probability of three particles of electrons, holes and phonons colliding together is very small, so the probability of direct recombination of electron holes to produce light is very small, making M0s possible to emit light. The situation is not bullish.

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五、發明說明(2) 遂發展出一種利用奈米粒子和奈米結構之金氧石夕發光 二極體,使矽不受間接能隙所限制,提高矽發光效率7其 基本原理在於應用量子力學的穿隨效應(Tunneling ef feet)。由量子力學的理論計算得知,當氧化層的厚度 薄到數奈米(nm)時,電子進行穿隧的機率將大幅增加, 此穿遂機率(tunneling probability)會隨正向偏壓之 增加而增加;但是氧化層並不是導體,所以仍有不小的電 壓跨在氧化層的兩端,也就是說,金屬和矽半導體有不同 的電壓,於是導致矽半導體的能帶彎曲。若是N型石夕,在 正向偏壓下(金屬接正電壓,矽半導體接負電壓),在氧 化層和矽半導體的介面附近,矽半導體的能帶彎向下,所 以形成電子的位能井(potential well),而大量累積電 子,此時又有大量的電洞從金屬端藉由穿隧效應到達此電 子的位能井位置,使大量的電子和電洞可在此處復合( recombination),並容易與聲子產生碰撞而發出光子; 若是P型矽,其藉由電激發而產生光子的原理也可依此類 推。 然而,由於金氧矽發光二極體的發光是在矽基板表 面,導致電子和電洞的復合仍受到非幅射式復合中心( nonradiative recombination center)的影響,非幅射 式復合中心係包含雜質、缺陷或表面能階等,a使幅射S 合的比例降低;該等非幅射式復合中心係提供電子和電洞 的額外復合途徑,且由於這些非幅射式復合中心的夂盥, 載子(電子和電洞)的生命期將明顯的縮短。因此,減少;;非V. Description of the invention (2) Then a kind of oxite luminescent diode using nano particles and nano structure was developed, so that silicon is not limited by the indirect energy gap, and the luminous efficiency of silicon is improved. 7 The basic principle lies in the application of quantum Mechanical tunneling ef feet. From the theoretical calculations of quantum mechanics, it is known that when the thickness of the oxide layer is as thin as a few nanometers (nm), the probability of electrons to tunnel will increase significantly, and this tunneling probability will increase with the forward bias. And the increase; but the oxide layer is not a conductor, so there is still a small voltage across the oxide layer, that is, the metal and the silicon semiconductor have different voltages, which causes the energy band of the silicon semiconductor to bend. If it is an N-type stone, under forward bias (metal is connected to a positive voltage, silicon semiconductor is connected to a negative voltage), near the interface between the oxide layer and the silicon semiconductor, the energy band of the silicon semiconductor is bent downward, so the potential energy of the electron is formed. (Potential well), and a large number of accumulated electrons, at this time there are a large number of holes from the metal end through the tunneling effect to reach the position of the potential well of this electron, so that a large number of electrons and holes can be recombined here (recombination ), And easily collide with phonons to emit photons; if it is P-type silicon, the principle of generating photons by electrical excitation can also be deduced by analogy. However, since the light emitting diode is on the surface of the silicon substrate, the recombination of electrons and holes is still affected by the nonradiative recombination center. The nonradiative recombination center contains impurities , Defects, or surface energy levels, etc., a reduces the proportion of radiative S-combination; these non-radiative recombination centers provide additional recombination paths for electrons and holes, and because of the non-radiative recombination centers, The lifetime of carriers (electrons and holes) will be significantly shortened. So reduce;

584913 五、發明說明(3) 唱射式復合中心可以提高幅射式復合的比例,使發光效率 更為提高。 有鑑於此,本發明係在針對上述之缺失,提出一種利 用蝕刻矽基板表面提高元件發光效率之方法的創新構想, 其係可不受矽的間接能隙所限制,以有效提高金氧矽結構 之發光效率。 【發明内容】 本發明之主要目的係在提供一種利用蝕刻矽基板表面 提高元件發光效率之方法,其係可減少矽基板表面的非輻 射式電子電洞之復合中心,使金氧矽發光元件的輻射式電 子電洞之復合比例提高,而不會受到矽的間接能隙所限制 ,故可達到大幅提高元件發光效率之功效者。 本發明之另一目的係在提供一種利用蝕刻矽基板表面 提高元件發光效率之方法,其係可在矽基板表面形成奈米 級的表面結構,此奈米結構可讓電子電洞被侷限在一奈米 區域内,使電子電洞對與聲子碰撞的機率大為提高,進而 使發光效率增強。 本發明之再一目的係在提供一種利用蝕刻矽基板表面 提高元件發光效率之方法,其係可運用現有半導體製造廠 線上的成熟製程與設備來進行半導體製程,故具有製程簡 單、製作成本低廉,且可直接與I C工業結合之優點。 為達到上述之目的,本發明係在一潔淨之半導體矽基 板表面,先利用高濃度之蝕刻液,對該矽基板進行蝕刻, 以移除矽基板表面之非幅射式復合中心,並同時形成奈米584913 V. Description of the invention (3) The sing-radiation recombination center can increase the proportion of radiation recombination, which can further improve the luminous efficiency. In view of this, the present invention is directed to the above-mentioned shortcomings, and proposes an innovative concept of a method for improving the luminous efficiency of a device by etching the surface of a silicon substrate, which is not limited by the indirect energy gap of silicon in order to effectively improve the structure of gold-oxygen silicon. Luminous efficiency. [Summary of the Invention] The main object of the present invention is to provide a method for improving the luminous efficiency of a device by etching the surface of a silicon substrate, which can reduce the compound center of non-radiative electron holes on the surface of the silicon substrate, so that The compound ratio of the radiant electron hole is increased without being limited by the indirect energy gap of silicon, so it can achieve the effect of greatly improving the luminous efficiency of the device. Another object of the present invention is to provide a method for improving the luminous efficiency of a device by etching the surface of a silicon substrate, which can form a nano-scale surface structure on the surface of the silicon substrate. This nano-structure can make electron holes limited to one nanometer. In the area of meters, the probability of an electron hole pair colliding with a phonon is greatly increased, and the luminous efficiency is further enhanced. Another object of the present invention is to provide a method for improving the luminous efficiency of a device by etching the surface of a silicon substrate. The method can use mature processes and equipment on the existing semiconductor manufacturing factory lines to perform semiconductor processes, so the process is simple and the manufacturing cost is low. And can be directly combined with the advantages of the IC industry. In order to achieve the above-mentioned object, the present invention is to etch a silicon substrate with a high-concentration etching solution on the surface of a clean semiconductor silicon substrate to remove the non-radiative compound center on the surface of the silicon substrate and form the same at the same time. Nano

584913 五、發明說明(4) 結 形 製 構,完成後清洗該矽基板;接著,依序在該矽基板表面 成一奈米粒子層及一導電層,以完成金氧矽發光元件之 作。 底下藉由具體實施例配合所附的圖式詳加說明,當更 容易瞭解本發明之目的、技術内容、特點及其所達成之功 效。 【實施方式】 本發明係利用蝕刻矽基板表面之技術,使得金氧矽結 構(MOS)可藉由電激發光而有效率地產生光子,以達到 提咼MOS元件發光效率之功效者。 由電子和電,同的復合(recombination)係受到雜質 、表面缺陷、表面能階等之非幅射式復合中心的影響,使 幅射式復合的比例降低,且由於這些非幅射式復合中心的 參與’使包含電子和電洞之載子的生命期明顯的縮短,載 子的生命期可由以下公式表示: ί 山 JL+i 山... 丄 其中3:幅射式復合的機制,非幅射式復合中缺陷的 影響’ Α是非幅射式復合中雜質的影響,^非幅射式復 合中心表面能階的影響;有此可知,所有非幅射式復合中 心都會讓載子的生命期縮短。就矽基板而言,本發明透過 生命期的實驗量測,發現cz石夕基板,其載子生命期在丨0// s 以内,而FZ石夕基板之生命期可達6〇// s,甚至於1 ms;可見584913 V. Description of the invention (4) Structure, clean the silicon substrate after completion; then, sequentially form a nano particle layer and a conductive layer on the surface of the silicon substrate in order to complete the operation of the gold-oxygen silicon light-emitting device. In the following, detailed descriptions will be made with specific embodiments and accompanying drawings to make it easier to understand the purpose, technical content, features and functions of the present invention. [Embodiment] The present invention uses a technology of etching the surface of a silicon substrate to enable a gold-oxide-silicon structure (MOS) to efficiently generate photons by electrically exciting light to achieve the effect of improving the luminous efficiency of a MOS device. Recombination by electrons and electricity is affected by non-radiative recombination centers such as impurities, surface defects, and surface energy levels, which reduces the proportion of radiative recombination. Participation of 'significantly shortens the lifetime of the carrier containing electrons and holes. The lifetime of the carrier can be expressed by the following formula: 山 山 JL + i 山 ... 丄 Among them 3: the mechanism of radiation recombination, non The effect of defects in radiative recombination 'A is the influence of impurities in non-radiative recombination, ^ the influence of the surface energy level of non-radiative recombination center; it can be known that all non-radiative recombination centers will let the carrier live Period shortened. As far as silicon substrates are concerned, through the experimental measurement of the lifetime, the invention has found that the carrier lifetime of the cz Shixi substrate is within 丨 0 // s, while the lifetime of the FZ Shixi substrate can reach 6〇 // s , Even 1 ms; visible

IH 584913 五、發明說明(5) 得非幅射式復合中心對電子和電洞的額外復合影響極大。 因為金乳矽發光70件的發光是在矽基板表面,表面能 ,和表面缺陷的影響很大’由生命期的實驗量測發現,在 沒^表面能階和表面缺陷(即晶體内部)下,其載子生命 期是1 ms ’但在表面能階的影響下,生命期縮短到6 p, 對金氧矽發光二極體的發光有不好的影響。有鑑於此,本 發明在製作金氧矽發光元件時,先處理矽基板的表面,例 如化學蝕刻等,減少表面能階或表面缺限的影響,即可有 效提高金氧石夕發光元件的發光效率。 第一(a)圖至第一(d)圖分別為本發明在製作金氧矽發 光元件之各步驟構造剖視圖,如圖所示,首先,提供一半 導體矽基板1 0,如第一(a)圖所示,其係經由一標準的清 洗過程’將其清洗乾淨;接著,利用高濃度之氫氧化鉀 (KOH)溶液、氫氧化鈉(NaOH)溶液或是氫氧化四曱銨 (Tetramethy lammonium Hydroxide,TMAH)溶液等之蝕 刻液,對此潔淨之半導體矽基板1 〇進行化學蝕刻,蝕刻時 間係根據蝕刻液之濃度而決定者,通常介於1 〇至4 0秒之 間’且#刻深度係不超過5 0奈米(nm),以藉此14刻步驟 移除該石夕基板1 0表面之非幅射式復合中心,並在該石夕基板 1 0表面形成奈米結構,奈米結構的尺寸則介於1奈米至3 〇 〇 奈米之間。完成化學蝕刻步驟之後,接續用去離子水再次 清洗矽基板,並吹乾之。 然後,將習知原有之二氧化矽奈米粒子溶液稀釋,以 減低奈米粒子之濃度,並利用旋轉塗佈方式,在矽基板1〇IH 584913 V. Description of the invention (5) The non-radiative recombination center has a great influence on the additional recombination of electrons and holes. Because the luminescence of the golden silicon 70 luminescence is on the surface of the silicon substrate, the surface energy, and the surface defects have a great impact. 'Experimental measurement of life found that under no surface energy level and surface defects (that is, inside the crystal) The carrier lifetime is 1 ms. However, under the influence of the surface energy level, the lifetime is shortened to 6 p, which has a bad influence on the luminescence of the gold oxide silicon light emitting diode. In view of this, when the metal oxide silicon light emitting device is manufactured by the present invention, the surface of the silicon substrate, such as chemical etching, is first processed to reduce the influence of the surface energy level or the surface defect, so that the light emission of the metal oxide light emitting device can be effectively improved. effectiveness. The first (a) to the first (d) diagrams are cross-sectional views of the structure of each step in the fabrication of a gold-oxide-silicon light-emitting device according to the present invention. As shown in the figure, first, a semiconductor silicon substrate 10 is provided. As shown in the figure, it is cleaned through a standard cleaning process; then, a high-concentration potassium hydroxide (KOH) solution, sodium hydroxide (NaOH) solution, or Tetramethy lammonium hydroxide (Tetramethy lammonium hydroxide) is used. Hydroxide (TMAH) solution and other etching solutions. This clean semiconductor silicon substrate 10 is chemically etched. The etching time is determined by the concentration of the etching solution, usually between 10 and 40 seconds. The depth is not more than 50 nanometers (nm). In this 14-step step, the non-radiative composite center on the surface of the stone evening substrate 10 is removed, and a nanostructure is formed on the surface of the stone evening substrate 10. The size of the meter structure is between 1 nanometer and 300 nanometers. After the chemical etching step is completed, the silicon substrate is washed again with deionized water and blow dried. Then, the conventional conventional silica nanoparticle solution was diluted to reduce the nanoparticle concentration, and the spin coating method was used on the silicon substrate.

sun 第10頁 584913 五、發明說明(6) 表面形成如第一(b )圖所示之奈米粒子層1 2 ;形成奈米粒 子層1 2之後’將矽基板1 〇烘乾,並去除有機溶劑。之後, 如第一(c )圖所示,於該奈米粒子層丨2表面先蒸鍍一層較 薄之氧化紹層1 4 ’而後再同樣利用蒸鍍法在氧化鋁層丨4表 面再鍍上銀或銀漆’請參閱第一(d )圖所示,以形成一導 電層1 6,至此’即完成金氧矽發光元件之製作。 其中’上述所使用之矽基板丨〇的材質亦可選自鍺、鍺 化矽、碳化矽及其他間接能隙材料所組成之群組;另一方 面,在蝕刻該矽基板1 0之步驟中,除了使用化學蝕刻方式 之外,亦可使用氣體姓刻或離子蝕刻方式。 本發明係在製作金氧矽發光元件時,先利用K0H溶液 餘刻矽基板,蝕刻液餘刻將先從表面缺陷開始,所以可以 讓蚀刻液將表面能階或表面缺限移除,但在適當時間内, 還不至於蝕刻矽基板的良好結晶區;且其蝕刻時間依據蝕 刻液的濃度,但以能夠移除表面能階或表面缺陷,而不嚴 重蝕刻矽基板的良好結晶區為佳。 至此,本發明之精神已說明完畢,以下特藉由幾個實 驗範例來驗證說明上述之原理,並使熟習此項技術者亦可 參酌此等範例之描述而獲得足夠的知識而據以實施。 利用—重量濃度為45%之氫氧化卸溶液,對一 +導體矽基板進行化學蝕刻,蝕刻時間為30秒,此時比對 轴刻前及姓刻後之結構…二圖及第三圖所示, /、係颁不矽基板在蝕刻前和蝕刻後的原子力顒微相片,在 沒有蝕刻之前,矽基板的表面非常平整,々口第二圖所示, 584913 五 矽 、發明說明(7) ___ 矽 深 刻 中 晶 基板的表面高低差只有數個埃( .^ 基板的表面,有些部份被蝕刻了, k麵刻之後, ,約有深1 00 A,如第三圖所示,作右、二部份陷的較 ,而呈現非常平整的表面。此乃因仁化仍二:份沒有被蚀 j格結構最脆弱&處開始發生:二=從石夕基板 格缺陷或表面受到外來原子影 ;、· =弱之處就是 之處)’矽基板表面被蝕刻的部‘,;θ(,面能階較多 多表面能階或表面缺限之處,因::一 原來具有較 前述的緣由1使得非幅射式復合中:口破移除’根據 復合的比例提高,冑而使發光效复;::…因此幅射式 ::钱刻除了可移除表面能 &成奈米級的表面結構,這種 ^ ^外,亦可 被侷限於-柰米區域内,因為電m p f電子和電洞 以聲子很容易加進來,也子和電洞已經在一起,所 子三個粒子的碰撞,現在料:=原來是電子、電洞和聲 子的碰撞,因此碰撞機率子電洞對和聲子兩個粒 增強。 為提面,亦使得發光效率相對 請參閱第四圖所示,直係—知" 對發光效率的影響,由圖;= = 液姓刻時間 可以對發光效率幫助極二=看出適▲的蝕刻時間 面平整的部份也有傷害所’對石夕基板表 接著如第五圖所示,盆^ 強度和電流關係圖,明可達成的光 ,藍色線是發光效率對電汽=發ί強度對電流關係圖 寬机關係圖。本發明係明顯地增強 五、發明說明(8) 光強度,使效率提高了 電流下,輸出光可達i贺倍以上,第五圖顯示在1 〇 〇 in久的 子效率已超過1 〇 μ;然 W W,而在2 0 m A時,對應的外部旦 的部份,大部份的光不而b此光強度只計算由銀漆邊緣射出 出,並未被收集入光 是被銀漆遮住,就是往別的方向 達1 0 -3。第六圖則§員、/則器’因此真正的外部量子坆率= 由此圖中之光譜顯示確^此金氧矽發光元件的發光光t普/ ,不是雜質的光蹲,實是碎基板的電子電洞幅射式胃復八 面能階。 確疋上述之化學钱刻並沒有增知1 此金氧矽發光元件 驗量測’發現電流増:載:(電子、電洞)生命期 < 實 示,由於非幅射式復人哉:子生命期縮短’⑹第七圖: 有透過幅射式復合的;生命期並不受電流影響、 1Ϊ:外差】=表示幅射式復合扮演極重要的角, 幅射式復合在化學蝕刻下,已大幅減少,故使得該金表, 發光元件的發光效率大大提高。 又仗付"金氧矽 因此’本發明確實可減少矽基板表面的非輻 電洞之復合1心,使金氧矽發光元件的輻射式電子^子 復合比例,南,而不會受到矽的間接能隙所限制,二之 到大幅提高元件發光效率之功效者。且由於此金氧二達 2 2 $ MOS結構的製程與傳統M〇s結構的製程接近,且^光 • 在矽晶片上,因此可以和目前之積體電路完全^直 ,使得矽晶片不僅可以有電子產品上的應用,合 584913 五、發明說明(9) 以 做為高效率發光元件,而電子晶片與發光元件的單石整 合(Monolithic integration),可以更加擴大矽晶片及 材料的應用範圍。再者,本發明之金氧石夕發光元件之 M0S結構和製程都相當簡單,製作成本低廉,X可以直接和 1曰有1C工業結合,所以具有相當大的實用性。 以上所述之實施例僅係為說明本發明之技術思想及特 點,其目的在使熟習此項技藝之人士能夠 容並據以實施,當不能以之限定太欲⑽ ^ ^ 凡依本發明所揭示之精神所作之 1固即大 “丄 士 3寺變化或修飾,仍麻、;,¾ 盍在本發明之專利範圍内。 1 5應/1¾ 【圖號說明】 10 半導體矽基板 1 2 奈米粒子層 14 氧化鋁層 1 6 金屬層章節結束sun Page 10 584913 V. Description of the invention (6) A nano particle layer 12 is formed on the surface as shown in the first (b) diagram; after the nano particle layer 12 is formed, the silicon substrate 10 is dried and removed. Organic solvents. Then, as shown in the first (c) diagram, a thin oxide layer 1 4 ′ is vapor-deposited on the surface of the nano-particle layer 丨 2, and then the surface of the alumina layer 丨 4 is again plated by the evaporation method. Applying silver or silver paint 'see the first (d) figure to form a conductive layer 16, and so far, the fabrication of the gold-oxide-silicon light-emitting element is completed. The material of the silicon substrate used above can also be selected from the group consisting of germanium, silicon germanium, silicon carbide, and other indirect energy gap materials; on the other hand, in the step of etching the silicon substrate 10 In addition to chemical etching, gaseous etching or ion etching can also be used. In the present invention, when a metal oxide silicon light-emitting device is manufactured, a silicon substrate is etched first with a KOH solution, and the etching solution will start from a surface defect first. Therefore, the etching solution can be used to remove the surface energy level or the surface defect. In a suitable time, the good crystal area of the silicon substrate is not yet etched; and the etching time depends on the concentration of the etching solution, but it is better to be able to remove the surface energy level or surface defects without seriously etching the good crystal area of the silicon substrate. So far, the spirit of the present invention has been described. The following principles are verified and demonstrated by several experimental examples, and those skilled in the art can also obtain sufficient knowledge by referring to the description of these examples and implement them. The chemical etching of a + conductor silicon substrate is carried out by using a 45% solution of hydroxide in hydrogen concentration, and the etching time is 30 seconds. At this time, the structures before and after the axis engraving are compared. It is shown that // is a microphotograph of the atomic force of the silicon substrate before and after etching. Before the etching, the surface of the silicon substrate is very flat. As shown in the second picture, 584913 Five silicon, description of the invention (7) ___ The surface height difference of the silicon substrate is only a few angstroms. (^ Some parts of the surface of the substrate have been etched. After the k-face is etched, the depth is about 100 A, as shown in the third figure. The two parts are collapsing and present a very flat surface. This is because of benignization. The two are not etched. The j-frame structure is the most fragile & the place begins: two = from the Shixi substrate grid defect or the surface is subject to foreign Atomic shadow ;, · = where the weak point is) 'the etched part of the surface of the silicon substrate' ;; θ (, where there are many surface energy levels, many surface energy levels or surface defects, because: a Reason 1 makes non-radiative compounding: rupture removal 'according to compounding Increasing the proportion, so that the luminous effect is restored; :: ... Therefore, the radiation type :: money can be removed in addition to removable surface energy & nanometer-level surface structure, this ^ ^, can also be limited to-柰In the meter area, because the electric mpf electrons and holes are easily added by phonons, the particles and holes are already together. The collision of the three particles of the soson is now expected to be: electrons, holes and phonons. Collision, so the probability of a collision between the hole and the phonon is enhanced. For the sake of improvement, it also makes the luminous efficiency relatively. Please refer to the fourth figure, the direct-knowing effect on the luminous efficiency. = The liquid crystal engraving time can help the luminous efficiency pole II = Seeing that the flat part of the etching time surface is also harmed. 'The Shi Xi substrate table is shown in the fifth figure. The relationship between the intensity and current of the pot, The light that can be achieved, the blue line is the relationship diagram of the luminous efficiency versus the electric steam = the intensity of the electric current versus the wide machine. The invention is significantly enhanced. V. Description of the invention (8) The light intensity makes the efficiency increase under the current. , The output light can reach more than i times, the fifth picture is displayed at 1 〇 〇in long sub-efficiency has exceeded 10 μ; WW, and at 20 m A, the corresponding part of the external denier, most of the light is not b. This light intensity is calculated only from the edge of the silver paint The light that has not been collected is covered by silver paint, that is, it is 10 to 3 in other directions. In the sixth diagram, the members and / or devices are therefore the true external quantum rate = the spectrum in this diagram It shows that the luminous light t / of this metal oxide light emitting device is not a light squat of impurities, but an electron hole radiation type gastric complex octahedral energy level of a broken substrate. It is confirmed that the above-mentioned chemical money has not increased. Know 1 This metal oxide silicon light-emitting element measurement 'is found the current 载: load: (electron, hole) life time < Actually, due to non-radiative renunciation 哉: the sub-life time is shortened' ⑹ seventh picture: There is a radiation compound; the lifetime is not affected by the current, 1Ϊ: heterodyne] = indicates that the radiation compound plays a very important angle. The radiation compound has been greatly reduced under chemical etching, so the gold Table, the luminous efficiency of the light-emitting element is greatly improved. In addition, "metal oxide silicon" therefore, the present invention can indeed reduce the non-radiation hole composite 1 core on the surface of the silicon substrate, so that the radiation electron electron compound ratio of the metal oxide silicon light emitting device is south, without being affected by silicon. The indirect energy gap is limited, and the second is the effect of greatly improving the luminous efficiency of the device. And because the fabrication process of this metal oxide 2 2 $ MOS structure is close to that of the traditional MOS structure, and it is on the silicon wafer, it can be completely straightened with the current integrated circuit, making the silicon wafer not only There are applications in electronic products, including 584913. V. Description of the invention (9) As a high-efficiency light-emitting element, the monolithic integration of electronic chips and light-emitting elements can further expand the application range of silicon wafers and materials. In addition, the MOS structure and manufacturing process of the alumina element of the present invention are quite simple and the production cost is low. X can be directly combined with 1C industry, so it has considerable practicability. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention, and the purpose is to enable those skilled in the art to tolerate and implement them. When it is not possible to limit it too much ⑽ ^ Revealed by the spirit of 1 is the change or modification of the "Jushi 3 Temple, still numb ,; ¾ 盍 is within the scope of the patent of the present invention. 1 5 shall / 1¾ [Illustration of drawing number] 10 Semiconductor silicon substrate 1 2 Nai Rice particle layer 14 Alumina layer 1 6 Metal layer end of chapter

584913 圖式簡單說明 第一(a)圖至第一(d)圖為本發明在製作金氧矽發光元件之 各步驟構造剖視圖。 第二圖為本發明矽基板表面在化學蝕刻前的原子力顯微相 片。 第三圖為本發明矽基板表面在化學蝕刻後的原子力顯微相 片° 第四圖為本發明使用之氫氧化鉀溶液蝕刻時間對發光強度 的影響。584913 Brief description of the drawings The first (a) to the first (d) diagrams are cross-sectional views of the structure of each step in the fabrication of the metal-oxide-silicon light-emitting device. The second figure is an atomic force micrograph of the surface of the silicon substrate of the present invention before chemical etching. The third picture shows the atomic force micrograph of the silicon substrate surface after chemical etching according to the invention. The fourth picture shows the effect of the etching time of the potassium hydroxide solution used on the invention on the luminous intensity.

第五圖為經由本發明可達成的發光強度及發光效率對電流 關係圖,其中紅色線是發光強度對電流關係圖,藍色線是 發光效率對電流關係圖。 第六圖為本發明之金氧矽發光元件的發光光譜。 第七圖為本發明之金氧矽發光元件的載子生命期和電流關 係圖。The fifth graph is a graph of luminous intensity and luminous efficiency versus current that can be achieved through the present invention, where the red line is a graph of luminous intensity versus current and the blue line is a graph of luminous efficiency versus current. The sixth figure is a light emission spectrum of the metal oxide light emitting device of the present invention. The seventh figure is a relationship diagram of the carrier lifetime and current of the metal oxide light emitting device of the present invention.

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Claims (1)

584913 六、申請專利範圍 1 · 一種利用蝕刻矽基板表面提高元件發光效率之方法, 包括下列步驟: 提供一潔淨之半導體矽基板; 利用適當濃度之蝕刻液,對該矽基板進行蝕刻,以移 除或減少該矽基板表面之非幅射式復合中心,並在 該矽基板表面形成奈米結構; 在該石夕基板表面形成一奈米粒子層;及 於該奈米粒子層表面再形成一導電層。 2 ·如申請專利範圍第1項所述之方法,其中該潔淨之半 導體矽基板係經由一清洗步驟使該矽基板乾淨。 3 ·如申請專利範圍第1項所述之方法,其中該蝕刻液係 選自氫氧化钟溶液、氫氧化納溶液及氫氧化四甲銨( TMAH)溶液所組成之群組。 4 ·如申請專利範圍第1項所述之方法,其中在對該矽基 板進行蝕刻之步驟中,蝕刻該矽基板之蝕刻時間係介 於1 0至4 0秒之間。 5 ·如申請專利範圍第1或第4項所述之方法,其中蝕刻 該矽基板之時間係根據蝕刻液之濃度而決定者。 6 ·如申請專利範圍第1項所述之方法,其中在對該矽基 板進行化學蝕刻之步驟中,其蝕刻深度係不超過5 0奈 米。 7 ·如申請專利範圍第1項所述之方法,其中在該矽基板 表面形成之奈米結構的尺寸係介於1奈米至3 0 0奈米之 間。584913 VI. Application Patent Scope 1 · A method for improving the luminous efficiency of a device by etching the surface of a silicon substrate, including the following steps: providing a clean semiconductor silicon substrate; etching the silicon substrate with an appropriate concentration of etching solution to remove the silicon substrate Or reducing the non-radiative compound center on the surface of the silicon substrate and forming a nanostructure on the surface of the silicon substrate; forming a nanoparticle layer on the surface of the silicon substrate; and forming a conductive layer on the surface of the nanoparticle layer Floor. 2. The method according to item 1 of the scope of patent application, wherein the clean semiconductor silicon substrate is cleaned by a cleaning step. 3. The method according to item 1 of the scope of patent application, wherein the etching solution is selected from the group consisting of a bell hydroxide solution, a sodium hydroxide solution, and a tetramethylammonium hydroxide (TMAH) solution. 4. The method according to item 1 of the scope of patent application, wherein in the step of etching the silicon substrate, the etching time for etching the silicon substrate is between 10 and 40 seconds. 5. The method according to item 1 or 4 of the scope of patent application, wherein the time for etching the silicon substrate is determined according to the concentration of the etching solution. 6. The method according to item 1 of the scope of patent application, wherein in the step of chemically etching the silicon substrate, the etching depth is not more than 50 nm. 7. The method according to item 1 of the scope of patent application, wherein the size of the nano structure formed on the surface of the silicon substrate is between 1 nanometer and 300 nanometers. 第16頁 584913 六、申請專利範圍 8 ·如申請專利範圍第1項所述之方法,其中該奈米粒子 層係利用旋轉塗佈方式所形成者。 9 ·如申請專利範圍第1項所述之方法,其中該奈米粒子 層係由二氧化碎奈米粒子所構成者。 1 0 ·如申請專利範圍第1項所述之方法,其中在蝕刻該矽 基板之步驟中,其所使用之蝕刻方式係選自化學蝕刻 、氣體蝕刻及離子蝕刻所組成之群組。 1 1 ·如申請專利範圍第1項所述之方法,其中該非幅射式 復合中心係包含雜質、表面缺陷及表面能階。 1 2 ·如申請專利範圍第1項所述之方法,其中在清洗該矽 基板之步驟中,係利用去離子水進行清洗。 1 3 ·如申請專利範圍第1項所述之方法,其中在形成該奈 米粒子層之步驟後,更包括一烘乾及去除有機溶劑之 步驟。 1 4 ·如申請專利範圍第1項所述之方法,其中該導電層係 利用蒸鍍法所形成者。 1 5 ·如申請專利範圍第1項所述之方法,其中該導電層係 由銀或銀漆所構成者。 1 6 ·如申請專利範圍第1項所述之方法,其中該矽基板之 材質係可選自矽、鍺、鍺化矽、碳化矽及其他間接能 隙材料所組成之群組。Page 16 584913 VI. Scope of Patent Application 8 • The method described in item 1 of the scope of patent application, wherein the nanoparticle layer is formed by a spin coating method. 9. The method as described in item 1 of the scope of patent application, wherein the nanoparticle layer is composed of nanoparticle of crushed nanoparticle. 1 0. The method according to item 1 of the scope of patent application, wherein in the step of etching the silicon substrate, the etching method used is selected from the group consisting of chemical etching, gas etching and ion etching. 1 1 · The method as described in item 1 of the scope of patent application, wherein the non-radiative composite center system includes impurities, surface defects and surface energy levels. 1 2 The method according to item 1 of the scope of patent application, wherein in the step of cleaning the silicon substrate, cleaning is performed with deionized water. 1 3. The method according to item 1 of the scope of patent application, wherein after the step of forming the nanoparticle layer, the method further comprises a step of drying and removing an organic solvent. 14 · The method according to item 1 of the scope of patent application, wherein the conductive layer is formed by a vapor deposition method. 15 · The method according to item 1 of the scope of patent application, wherein the conductive layer is made of silver or silver paint. 16 · The method according to item 1 of the scope of patent application, wherein the material of the silicon substrate can be selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, and other indirect bandgap materials. 第17頁Page 17
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